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Tunable threshold voltage of an n-type Si nanowire ferroelectric-gate field effect transistor for high-performance nonvolatile memory applications
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2014 Nanotechnology 25 205201 (http://iopscience.iop.org/0957-4484/25/20/205201) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 136.186.1.81 This content was downloaded on 29/08/2014 at 12:05
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Nanotechnology Nanotechnology 25 (2014) 205201 (8pp)
doi:10.1088/0957-4484/25/20/205201
Tunable threshold voltage of an n-type Si nanowire ferroelectric-gate field effect transistor for high-performance nonvolatile memory applications Ngoc Huynh Van3, Jae-Hyun Lee1, Jung Inn Sohn2, SeungNam Cha2, Dongmok Whang1, Jong Min Kim2 and Dae Joon Kang3,4 1
School of Advanced Materials Science and Engineering, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746, Republic of Korea 2 Department of Engineering Science, University of Oxford, Oxfordshire OX1 3PJ, UK 3 Department of Physics, Institute of Basic Science, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746, Republic of Korea E-mail: [email protected] Received 18 December 2013, revised 3 March 2014 Accepted for publication 6 March 2014 Published 30 April 2014 Abstract
We successfully fabricated ferroelectric-gate field effect transistor (FEFET)-based nonvolatile memory devices using an n-type Si nanowire coated with omega-shaped-gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) via a low-temperature fabrication process. Our FEFET memory devices with controllable threshold voltage via adjustment of the doping concentration exhibit excellent memory characteristics with ultra-low ON state power dissipation (⩽3 nW), a large modulation in channel conductance between the ON and OFF states exceeding 105, a long retention time of over 3 × 104 s and a high endurance of over 105 programming cycles whilst maintaining an ION/IOFF ratio higher than 103. This result may be promising for next-generation nonvolatile memory on flexible substrate applications. S Online supplementary data available from stacks.iop.org/NANO/25/205201/mmedia Keywords: Si nanowires, field effect transistor, ferroelectric memory (Some figures may appear in colour only in the online journal)
1. Introduction
transistor (FEFET)-based ferroelectric memory offers exceptional advantages over conventional memory devices including small cell size, low-voltage operation, low power consumption, fast programming/erase speed and nonvolatility. Early on, however, researchers were confronted with significant challenges, such as the depolarization fields and charge trapping that degraded the device performance and seemed to thwart the potential of ferroelectric memory [1–3]. One-dimensional (1D) nanostructures such as nanowires (NWs), nanotubes, and nanocables as conducting channels of
Solid-state disks or nonvolatile memory chips are indispensable in modern portable electronic devices and thus present an application where ferroelectric memory has great potential. In particular, building ferroelectric memory with low power consumption is critical for saving energy and for long-term use of these devices. Ferroelectric-gate field effect 4
Author to whom any correspondence should be addressed.
0957-4484/14/205201+08$33.00
1
© 2014 IOP Publishing Ltd Printed in the UK
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Nanotechnology 25 (2014) 205201
Figure 1. Electric transport properties of a single n-type Si NWFET device under ambient conditions. (a) Ids–Vds output characteristics and (b) Ids–Vg transfer characteristics.
FEFETs have attracted a great deal of attention over the past decade due to their unique physical properties [4–7]. Many reports have suggested that nanowire FEFETs have higher performance, longer retention time and better endurance memory characteristics compared with thin-film-based FEFET memory. For example, the small size of NWs is desirable for increasing the density of devices per area and single crystalline semiconductor NWs can function as a superior carrier transport channel with enhanced field effect mobility (μeff), subthreshold slope (SS) and operation voltage. The superior mobility and small size of carbon nanotubes (CNTs) and graphene ribbons have also been exploited to surpass recent Si technology in device operation speed [8, 9]. Despite great advances in these materials, the graphene FEFET still suffers from a low ION/IOFF ratio and OFF-state leakage problems due to various tunneling mechanisms and ambipolar behavior. The difficulty in selecting metallic or semiconductor CNTs continues to limit their use in industrial applications. So far, Si is still the best candidate as a conducting channel in terms of mobility [10, 11]. Obtaining a good interface between ferroelectric oxide materials such as lead zirconate titanium (PZT) or bismuth titanium oxide (BTO) on Si semiconducting channels requires a buffer layer between them, which can lead to an increase in the depolarization field and working voltage [1, 12]. On the other hand, organic ferroelectric material has been exploited for nonvolatile memory devices because of its light weight, easy fabrication, flexibility, low-temperature processing capability, solution-based large area application, and low-cost construction [13–16]. Among organic ferroelectrics, poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) exhibits ferroelectricity at room temperature and has the largest remnant polarization value of 11.9 μC cm−2 [2]. Furthermore, the process to form ferroelectricity is simply thermal annealing below 140 °C. No interfacial layer is formed during the crystallization process, thereby minimizing the charge trapping effect at the interface. Therefore, a buffer layer can be omitted. Here we report an effective and reliable way to modulate the electrical properties of Si nanowires by controlling the doping concentration, not only for extremely low power
consumption but also for long retention time of ferroelectric memory devices. We overcome the interfacial layer problem by incorporating P(VDF-TrFE) as an organic omega-shaped ferroelectric gate. Thus we have created an n-type Si NW conducting channel FEFET nonvolatile memory device, having chosen n-type Si as the best candidate in terms of mobility and an omega-shaped ferroelectric gate for enhancement of the device performance. Our FEFET memory devices exhibit excellent memory characteristics with a large modulation in channel conductance and high endurance.
2. Experimental The phosphorus-doped n-type Si NWs used in this study were grown on (100) Si substrates with Au catalysts by the vapor–liquid–solid method reported in detail by T Koo et al [17]. In this experiment we grew n-type Si NWs at different phosphorus doping concentrations (silane (SiH4)/phosphine (PH3) gas ratio at 4000:1 to 10 000:1). Single crystal Si NWs with a typical diameter of 50–70 nm were first dispersed by ultra-sonication in isopropanol and then transferred onto a Si substrate by dropping a liquid suspension of Si NWs from a pipette. A heavily doped p-type Si substrate was employed as a back gate with a 100 nm thick thermal oxide layer on top as a gate oxide layer. Source and drain electrodes were patterned by photolithography followed by electron-beam evaporation of 80 nm Ti and 50 nm Au electrodes on a Si NW and a liftoff process. Prior to electrode deposition, Si NWs were etched in a 1% hydrofluoric acid solution for 15 s to remove the native oxide layer on the shell of the nanowires [17]. The 200 nm thick P(VDF-TrFE) ferroelectric layer was prepared by mixing P(VDF-TrFE) at 0.08 wt% in 2-butanone. Then, this solution was coated on the Si nanowire field effect transistors (NWFETs) by spin coating (1 min at 1000 rpm). Before that, the substrate was treated with a 2 min oxygen plasma treatment. Thermal annealing (2 h at 80 °C and 2 h at 130 °C in air) was carried out to form β phase dominant P (VDF-TrFE) [18, 19]. The electrical characteristics of the devices were measured in air using a probe station with a Keithley SCS-4200 system. 2
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Nanotechnology 25 (2014) 205201
conducting channel length of the nanowire (∼5 μm), and r is the radius of the nanowire (∼27.5 nm). For NWFETs on a SiO2/Si substrate, the threshold voltage Vth = −2 V and transconductance gm=116 nS were extrapolated from the linear region of the Ids–Vg curve at Vds = 0.1 V. The field effect electron mobility was also found to be μe = 59.3 cm2 V−1 · s. The resistivity ρ = 0.22 Ω cm of the Si NW was calculated from four probe measurements (see figure S2(b) in the supporting information, available at stacks.iop.org/NANO/25/ 205201/mmedia). The electron carrier concentration (ne) was calculated by ne = 1 ρqμe = 4.8 × 1017 e cm−3. The subthreshold swing S = log ⎡⎣ dV d ( log I ) ⎤⎦ is about 125 g
ds
mV dec−1, which is small for low power consumption devices. The effect of doping concentration on the conductance and threshold voltage of n-type Si NWFETs is shown in figure 2(a). The transfer characteristics of the drain current versus gate-source voltage (Ids–Vg) curves of several n-type Si NWFETs were obtained by sweeping the gate voltage continuously from −5 to +5 V with drain voltage at 0.1 V of devices with Si NWs at four different doping concentrations (silane (SiH4)/phosphine (PH3) ratio at 4000:1 to 10 000:1). The threshold voltage shifts from −3 V to close to 0 V as the doping concentration is reduced. We also estimated the carrier concentrations from the transfer characteristics of the drain current versus the gate-source voltage (Ids–Vg) curves by varying the silane (SiH4)/phosphine (PH3) gas ratios (i.e. by varying the doping concentrations). For instance, the electron carrier concentrations were estimated to be 91.6 × 1017 and 2.4 × 1017 e cm−3 for 4000:1 and 10 000:1 silane (SiH4)/ phosphine (PH3) gas ratios, respectively. Additionally, the reduction of ON current from 10−8 A to 10−11 A was observed when the electron carrier concentrations were lowered with decreasing doping concentrations. Note that we did not observe any variation in the nanowire diameter with the different doping concentrations. Figure 2(b) shows a schematic view of a simplified depletion model for n-type Si NWFETs with different doping concentrations at a constant negative gate voltage. The dark pink gradient shows the electric field distribution under the application of a negative back-gate voltage, resulting in depletion of the electron carriers of ntype Si NW. Furthermore, the less dense electron carriers easily induce full depletion at the same negative gate voltage. Therefore, reducing the doping concentration leads to fewer electron carriers in the conducting channel Si NWs, resulting in reduced conductance and a positive shift of the threshold voltage of Si NWFETs. The schematic diagram of the back-gate FEFET-based nonvolatile memory device and the operation mechanism of the Si nanowire ferroelectric-gate field effect transistor (NWFEFET) are shown in figure 3(a). The FEFET working mechanism has been proposed by Liao et al [5]. In our device structure, instead of using the ferroelectric layer as the backgate dielectric layer, we coated the Si NW with ferroelectric P (VDF-TrFE). When a negative Vg pulse is applied to the gate, under a negative electrostatic field gradient from the gate to the air, the polarization of the ferroelectric film will be aligned
Figure 2. (a) Ids–Vg transfer characteristics of n-type Si NWFETs at different doping concentrations—silane (SiH4)/phosphine (PH3) ratio at 4000:1 to 10 000:1. (b) A schematic view of a simplified depletion model for n-type Si NWFETs with different doping concentrations at a constant negative gate voltage.
3. Results and discussion To investigate the basic electrical properties of n-type Si NWs, we prepared a conventional NWFET on a 100 nm SiO2/ Si substrate with a back gate. Figure 1(a) shows the measured drain current versus drain-source voltage (Ids–Vds) curves of a single Si NWFET. The conductance of the NW increases monotonically as the gate potential increases in the range from −5 to +5 V, demonstrating an n-channel Si NWFET. Figure 1(b) shows the drain current versus gate-source voltage (Ids–Vg) curves by sweeping the gate voltage continuously from −5 to +10 V at a drain voltage from 0 to 0.5 V. The transconductance (gm) and the field effect electron mobility (μe) can be determined from the Ids–Vg curves using the following equations: gm = dIds dVg and μe = gmL 2 CoxVds , respectively, for the back-gate NWFETs [5]. Cox is the gate oxide capacitance of a cylindrical wire on a planar substrate and can be calculated by Cox = 2πεr ε0L cosh−1 ( 1 + tox r ) where εr = 3.9 is the relative dielectric constant, tox = 100 nm is the thickness of the SiO2 gate dielectric layer, L is the 3
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Nanotechnology 25 (2014) 205201
Figure 3. A Si NWFEFET memory device. (a) A schematic view of a back-gate FEFET-based nonvolatile memory device and working
mechanism. (b) Hysteretic behavior for a back-gate Si NWFEFET with P(VDF-TrFE) coated on the NW surface.
Figure 4. Memory properties of a P(VDF-TrFE)-coated Si NWFEFET-based memory: (a) retention times and (b) evolution of endurance tests of the drain currents of the Si NWFEFET device. The gate pulse was ±10 V at 100 ms pulse width, Vds = 0.1 V.
upward. The protons (H+) in the P(VDF-TrFE) are distributed on the nanowire surface, whereas the electronegative fluorine anions (F−) are oriented toward the nanowire surface upon polarization. After the gate voltage pulse is removed, the remnant polarization of the ferroelectrics introduces an effective positive field effect, and further induces an equal amount of negative space charges within the nanowire. This results in the accumulation of electrons in the n-type Si NW conducting channel to form a high conductance state in the ntype Si NW FEFET, representing the ON state of the memory device. Conversely, when a positive pulse at the back gate is applied, an OFF state is obtained due to reduced conduction by electron depletion. The depolarization field and carriers’ charge-trapping are the main problems leading to the short retention time of FEFET-based memory [1, 2]. According to Ma et al [1], the depolarization field is dependent on remnant polarization Pr. For a nanowire FEFET, the remnant polarization of the ferroelectric material should be large enough to create an electric field that induces the OFF state on the conducting nanowire channel field effect transistor (FET). This means the remnant polarization must create an electric field larger than the gate electric field that induces the threshold voltage of the FET. Our goal is to obtain long memory retention time by reducing the threshold voltage of Si NWFET. When the threshold
voltage is lower, less remnant polarization from the ferroelectric layer is required; it not only reduces the depolarization field but also reduces the leakage current and carriers’ charge trapping at the interface of the conducting channel and ferroelectric layer. The effective way to adjust the threshold voltage is to change the doping concentration. However, further reducing the threshold voltage also reduces the performance of the FET with respect to conductivity, transconductance, mobility and the ION/IOFF ratio. For our highperformance and long retention time memory devices, the optimized doping concentration was achieved at a 6 000:1 ratio of silane (SiH4)/phosphine (PH3), and a threshold voltage of ∼−1 V while maintaining a sufficient ION/IOFF ratio exceeding 105. The hysteresis behavior of a back-gate Si NWFEFET as a function of the sweep range of gate voltages is shown in figure 3(b). The positive or negative polarization of P(VDFTrFE) is induced on a Si NW depending on the gate voltage sweep direction, enabling modulation in channel conductance and threshold voltages. The hysteretic window becomes larger at a higher gate voltage sweep range, confirming that the origin of such hysteretic behavior is due to the polarization of the ferroelectric layer. In our devices, a 3 V clockwise hysteresis loop window was observed with conductance changes exhibiting a difference of more than 5 orders of magnitude 4
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Nanotechnology 25 (2014) 205201
Figure 5. Memory properties of a P(VDF-TrFE)-coated Si NW FEFET-based memory device: (a) retention times and (b) evolution of
endurance tests of the drain currents of the Si NWFEFET device. The gate pulse was ±5 V at 100 ms pulse width, Vds = 0.1 V. The inserted figure shows the hysteretic behavior measured when sweeping the back-gate voltage from −5 V to +5 V then back to −5 V, and −10 V to +10 V then back to −10 V.
between high and low conductance states when sweeping the back-gate voltage from −10 V to +10 V and back to −10 V, with a sweeping step of 0.1 V at Vds = 0.1 V in an ambient environment. The memory properties of the P(VDF-TrFE) coated Si NWFEFET-based memory are shown in figure 4(a) (retention times) and figure 4(b) (endurance tests) for the high and low conductance states, i.e., ON and OFF states, respectively. These were measured at Vds = 0.1 V and Vg = 0 V after the device was switched ON and OFF using +10 V writing and −10 V erasing pulses, respectively, with pulse widths of 100 ms. A large change in conductance between the ON and OFF states exceeded 105 and remained over 103 even after 3 × 104 s (8 h). It should be noted that the ON current was ∼30 nA while the OFF current was much lower, ∼200 fA at Vds = 0.1 V, which results in less than 3 nW power dissipation in the ON state. To the best of our knowledge, this is the lowest operation ON state and current power dissipation achieved while maintaining a sufficiently high ION/IOFF ratio. The quality of the Si NWs is highly dependent on the dimension and the surface states. The surface defect-induced p-type conduction of Si NWs was reported by Luo et al [20]. For an n-type Si NWFET, p-type behavior dominates at the negative gate voltage region due to surface defects, thus IOFF becomes higher at lower gate voltage. This will reduce the ION/IOFF ratio of n-type Si NWFETs. Therefore, the p-type Si NWFET is expected to have a higher ION/IOFF ratio compared to an n-type Si NWFET. However, n-type Si NWs are still the best in terms of mobility. That is why we chose n-type Si NWs over p-type Si NWs to realize high-speed memory devices. Furthermore, a high endurance of over 105 programming cycles was observed with an ION/IOFF ratio of over 104. The endurance test for both ON and OFF states was conducted after 4000 programming cycles at a fixed Vds = 0.1 V, a cycle condition of ±10 V pulse peak to peak and a 100 ms pulse width. To the best of our knowledge, this is the best ferroelectric memory performance demonstrated for nanowires as the conducting channel in FEFET memory [4–7]. It is
comparable to CNT- and graphene-based FEFET memory counterparts [8, 9, 21] in terms of retention time and endurance test results, while maintaining much higher ION/IOFF ratios, as well as better performance than thin-film-based FEFETs [22, 23] in terms of retention time. The reasons for the long retention time and high endurance of Si NWFEFET memory are related to the ferroelectricgate NWFET memory structure and Si/ferroelectric interface. These points are discussed in detail in the following paragraphs. The advantage of using nanowires as a semiconducting channel in FEFET memory is the sensitive change in conductance and the inherently small scale of each device, leading to high memory device density. Single crystalline nanowires and nanotubes often feature higher mobility and lower sub-threshold swing, allowing FET devices to work at a higher speed and lower power consumption. The important difference is that the NWFEFET working mechanism is based on the depletion–accumulation mode whereas the conventional thin-film FEFET working mechanism is based on the inversion mode. In the inversion mode, higher gate voltage and longer times are required for minor carriers to travel to form an inversion-conducting channel, compared with the depletion–accumulation mode, where major carriers under gate voltage form the conducting channel. Therefore, NWFEFET devices are expected to work at higher frequency and lower operation voltage than thin-film FEFETs. Lower operation voltage means lower remnant polarization is required for the ferroelectric layer, leading to a longer retention time in ferroelectric memory due to the reduction of the depolarization field and charge trapping effects [1, 2]. Furthermore, when an organic ferroelectric gate is used, no buffer layer is needed and an omega-shaped gate FEFET structure can be created by spin coating the organic ferroelectric layer on the top of the NW. The remnant polarization field of the ferroelectric gate then directly acts on the surface of the nanowire without any dielectric layer in between. Therefore, the remnant polarization field of an omega-shaped ferroelectric gate will be more effective than that of the 5
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Nanotechnology 25 (2014) 205201
omega-shaped gate in a typical NWFET and it will be much better than a NWFEFET with a planar ferroelectric gate [24, 25]. The FEFET in this work is expected to operate at lower voltage, higher ION/IOFF ratio, higher transconductance and higher field effect mobility compared with omega-shape gate NWFET as well as planar gate FEFET counterparts. Even with a small hysteresis window (i.e., less than 2 V), when sweeping the back-gate voltage from −5 V to +5 V and back, we still saw a large change in conductance between the ON and OFF states exceeding 104, which was retained over 103 after 104 s (∼3 h) of retention time and over 5 × 104 programming cycles. Cycle conditions were ±5 V pulse peak to peak with a 100 ms pulse width (see figure 5). The shorter retention time and endurance test time compared to that measured from the ±10 V gate pulses could be due to the ferroelectric P(VDF-TrFE) layer not being fully polarized at ±5 V gate pulses [6]. When compared with Si NWFEFETbased memory devices reported by Das and Appenzeller [26], our devices showed that the retention time was at least three times longer while achieving an ION/IOFF ratio of more than two orders of magnitude (see figure 4). Even at a ±5 V gate pulse (a gate pulse four times lower), our devices showed an ION/IOFF ratio of more than one order of magnitude for the same retention time (see figure 5). Such an achievement was possible because of the low depolarization field and low carrier charge trapping as a result of careful tuning of the threshold voltage of Si NWFETs. It is extremely difficult to fabricate metal oxide ferroelectric materials such as PZT or BTO on Si and form a good interface because of the chemical reaction and inter-diffusion of Si into the ferroelectric layer [27]. Such issues lead to the creation of a gate leakage current and/or the trapping of carriers in the gate dielectric stack, resulting in reduced retention time of the memory devices [1]. To improve the interface properties, the use of a thick buffer layer at the interface such as SiO2, Al2O3 or HfO2 to reduce the leakage current and charge carrier trapping has been applied for thinfilm-based FEFET memory. However, insertion of the buffer layer causes other problems, such that the data retention period becomes shorter and higher gate voltages are required due to the effect of the depolarization field [1–3]. Another solution is to use oxide semiconductors to obtain a good ferroelectric/semiconductor interface [3]. However, the mobility of metal oxide semiconductors is still lower than Si, so this would be a disadvantage in high-performance nonvolatile memory devices. The superior mobility and small size of CNTs and graphene ribbons makes these materials suitable candidates for replacing the Si conducting channel; as such, they are considered to be next-generation FEFET memory devices. CNTs and graphene ribbons used as the conducting channel for FEFET memory applications have demonstrated long retention times, high endurance, and high mobility [8, 28–32]. However, graphene FEFETs still suffer from a low ION/IOFF ratio and OFF-state leakage problems due to various tunneling mechanisms and ambipolar behavior. The difficulty in selecting metallic or semiconductor CNTs continues to limit their use in industrial applications.
In our memory devices, P(VDF-TrFE) is used as a ferroelectric gate. The simple process used to form ferroelectricity, which is just thermal annealing after spin coating above the Curie temperature (lower than 140 °C), results in no interfacial layer formation during the crystallization process. Without an interfacial layer, charge-trapping effects at the interface of the surface organic film and the Si NW semiconductor channel are minimized. When direct contact is realized in a FEFET, the data retention time is likely to be much longer than that in a conventional FEFET because no depolarization field is generated due to the buffer layer. Furthermore, with a low-temperature fabrication process, these devices can be fabricated on flexible substrates for flexible nonvolatile memory applications. Compared with the BTO particle-coated ZnO NWFEFET memory devices reported by Sohn et al [6], our approach allows more uniform coating over a large area and facile control of the ferroelectric layer thickness by simply changing the spin coating speed. In addition, if the P(VDF-TrFE) ferroelectric layer is patterned only on the conducting channel, e.g. by using a water-soluble photoresist [13], soft lithography [14], nanoimprinting lithography [15] or photolithography with a common photoresist (PR) developed by a diluted PR stripper [16], the typical parasitic effects on the electrodes can be minimized. Therefore, further enhancement of memory performance is expected in terms of retention time, offering a great opportunity for viable industrial applications. A smaller hysteresis window was observed in a conventional back-gate FET, exhibiting the typical electrical behavior of an n-type channel Si NWFET (see figure S2(c) in the supporting information). This hysteresis was caused by the trapped charges of carriers at the SiO2/Si interface due to immobile oxide charges or oxide-trapped space charge associated with defects in SiO2 [33]. We also investigated the memory properties due to these effects (see figure 2(d) in the supporting information). A rapid reduction in conductance between the ON and OFF states to over 102 after 1000 s (less than 20 min) was observed after the device was switched ON and OFF using +10 V writing and −10 V erasing pulses, respectively. This provides further confirmation that the measured memory properties of P(VDF-TrFE)-coated Si NW FEFET are due to the remnant polarization of the ferroelectric layer. Our results imply that such NW channel FEFET devices are promising for random access memory applications. For nonvolatile memory applications, where a ten-year retention time is required for a viable nonvolatile semiconductor memory technology, there is still much room for improvement. A primary limitation when using nanowires as a conducting channel is the large diameter of the nanowires (larger than 50 nm). Reducing the nanowire diameter is expected to reduce the operating voltage. When the operating voltage is reduced, other potentially detrimental effects in the device may be suppressed, such as depolarization of the ferroelectric field, leakage current and charge trapping. Moreover, when the diameter of the nanowire reaches that of the Bohr radius of the material (typically
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Tunable threshold voltage of an n-type Si nanowire ferroelectric-gate field effect transistor for high-performance nonvolatile memory applications
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2014 Nanotechnology 25 205201 (http://iopscience.iop.org/0957-4484/25/20/205201) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 136.186.1.81 This content was downloaded on 29/08/2014 at 12:05
Please note that terms and conditions apply.
Nanotechnology Nanotechnology 25 (2014) 205201 (8pp)
doi:10.1088/0957-4484/25/20/205201
Tunable threshold voltage of an n-type Si nanowire ferroelectric-gate field effect transistor for high-performance nonvolatile memory applications Ngoc Huynh Van3, Jae-Hyun Lee1, Jung Inn Sohn2, SeungNam Cha2, Dongmok Whang1, Jong Min Kim2 and Dae Joon Kang3,4 1
School of Advanced Materials Science and Engineering, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746, Republic of Korea 2 Department of Engineering Science, University of Oxford, Oxfordshire OX1 3PJ, UK 3 Department of Physics, Institute of Basic Science, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746, Republic of Korea E-mail: [email protected] Received 18 December 2013, revised 3 March 2014 Accepted for publication 6 March 2014 Published 30 April 2014 Abstract
We successfully fabricated ferroelectric-gate field effect transistor (FEFET)-based nonvolatile memory devices using an n-type Si nanowire coated with omega-shaped-gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) via a low-temperature fabrication process. Our FEFET memory devices with controllable threshold voltage via adjustment of the doping concentration exhibit excellent memory characteristics with ultra-low ON state power dissipation (⩽3 nW), a large modulation in channel conductance between the ON and OFF states exceeding 105, a long retention time of over 3 × 104 s and a high endurance of over 105 programming cycles whilst maintaining an ION/IOFF ratio higher than 103. This result may be promising for next-generation nonvolatile memory on flexible substrate applications. S Online supplementary data available from stacks.iop.org/NANO/25/205201/mmedia Keywords: Si nanowires, field effect transistor, ferroelectric memory (Some figures may appear in colour only in the online journal)
1. Introduction
transistor (FEFET)-based ferroelectric memory offers exceptional advantages over conventional memory devices including small cell size, low-voltage operation, low power consumption, fast programming/erase speed and nonvolatility. Early on, however, researchers were confronted with significant challenges, such as the depolarization fields and charge trapping that degraded the device performance and seemed to thwart the potential of ferroelectric memory [1–3]. One-dimensional (1D) nanostructures such as nanowires (NWs), nanotubes, and nanocables as conducting channels of
Solid-state disks or nonvolatile memory chips are indispensable in modern portable electronic devices and thus present an application where ferroelectric memory has great potential. In particular, building ferroelectric memory with low power consumption is critical for saving energy and for long-term use of these devices. Ferroelectric-gate field effect 4
Author to whom any correspondence should be addressed.
0957-4484/14/205201+08$33.00
1
© 2014 IOP Publishing Ltd Printed in the UK
N H Van et al
Nanotechnology 25 (2014) 205201
Figure 1. Electric transport properties of a single n-type Si NWFET device under ambient conditions. (a) Ids–Vds output characteristics and (b) Ids–Vg transfer characteristics.
FEFETs have attracted a great deal of attention over the past decade due to their unique physical properties [4–7]. Many reports have suggested that nanowire FEFETs have higher performance, longer retention time and better endurance memory characteristics compared with thin-film-based FEFET memory. For example, the small size of NWs is desirable for increasing the density of devices per area and single crystalline semiconductor NWs can function as a superior carrier transport channel with enhanced field effect mobility (μeff), subthreshold slope (SS) and operation voltage. The superior mobility and small size of carbon nanotubes (CNTs) and graphene ribbons have also been exploited to surpass recent Si technology in device operation speed [8, 9]. Despite great advances in these materials, the graphene FEFET still suffers from a low ION/IOFF ratio and OFF-state leakage problems due to various tunneling mechanisms and ambipolar behavior. The difficulty in selecting metallic or semiconductor CNTs continues to limit their use in industrial applications. So far, Si is still the best candidate as a conducting channel in terms of mobility [10, 11]. Obtaining a good interface between ferroelectric oxide materials such as lead zirconate titanium (PZT) or bismuth titanium oxide (BTO) on Si semiconducting channels requires a buffer layer between them, which can lead to an increase in the depolarization field and working voltage [1, 12]. On the other hand, organic ferroelectric material has been exploited for nonvolatile memory devices because of its light weight, easy fabrication, flexibility, low-temperature processing capability, solution-based large area application, and low-cost construction [13–16]. Among organic ferroelectrics, poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) exhibits ferroelectricity at room temperature and has the largest remnant polarization value of 11.9 μC cm−2 [2]. Furthermore, the process to form ferroelectricity is simply thermal annealing below 140 °C. No interfacial layer is formed during the crystallization process, thereby minimizing the charge trapping effect at the interface. Therefore, a buffer layer can be omitted. Here we report an effective and reliable way to modulate the electrical properties of Si nanowires by controlling the doping concentration, not only for extremely low power
consumption but also for long retention time of ferroelectric memory devices. We overcome the interfacial layer problem by incorporating P(VDF-TrFE) as an organic omega-shaped ferroelectric gate. Thus we have created an n-type Si NW conducting channel FEFET nonvolatile memory device, having chosen n-type Si as the best candidate in terms of mobility and an omega-shaped ferroelectric gate for enhancement of the device performance. Our FEFET memory devices exhibit excellent memory characteristics with a large modulation in channel conductance and high endurance.
2. Experimental The phosphorus-doped n-type Si NWs used in this study were grown on (100) Si substrates with Au catalysts by the vapor–liquid–solid method reported in detail by T Koo et al [17]. In this experiment we grew n-type Si NWs at different phosphorus doping concentrations (silane (SiH4)/phosphine (PH3) gas ratio at 4000:1 to 10 000:1). Single crystal Si NWs with a typical diameter of 50–70 nm were first dispersed by ultra-sonication in isopropanol and then transferred onto a Si substrate by dropping a liquid suspension of Si NWs from a pipette. A heavily doped p-type Si substrate was employed as a back gate with a 100 nm thick thermal oxide layer on top as a gate oxide layer. Source and drain electrodes were patterned by photolithography followed by electron-beam evaporation of 80 nm Ti and 50 nm Au electrodes on a Si NW and a liftoff process. Prior to electrode deposition, Si NWs were etched in a 1% hydrofluoric acid solution for 15 s to remove the native oxide layer on the shell of the nanowires [17]. The 200 nm thick P(VDF-TrFE) ferroelectric layer was prepared by mixing P(VDF-TrFE) at 0.08 wt% in 2-butanone. Then, this solution was coated on the Si nanowire field effect transistors (NWFETs) by spin coating (1 min at 1000 rpm). Before that, the substrate was treated with a 2 min oxygen plasma treatment. Thermal annealing (2 h at 80 °C and 2 h at 130 °C in air) was carried out to form β phase dominant P (VDF-TrFE) [18, 19]. The electrical characteristics of the devices were measured in air using a probe station with a Keithley SCS-4200 system. 2
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conducting channel length of the nanowire (∼5 μm), and r is the radius of the nanowire (∼27.5 nm). For NWFETs on a SiO2/Si substrate, the threshold voltage Vth = −2 V and transconductance gm=116 nS were extrapolated from the linear region of the Ids–Vg curve at Vds = 0.1 V. The field effect electron mobility was also found to be μe = 59.3 cm2 V−1 · s. The resistivity ρ = 0.22 Ω cm of the Si NW was calculated from four probe measurements (see figure S2(b) in the supporting information, available at stacks.iop.org/NANO/25/ 205201/mmedia). The electron carrier concentration (ne) was calculated by ne = 1 ρqμe = 4.8 × 1017 e cm−3. The subthreshold swing S = log ⎡⎣ dV d ( log I ) ⎤⎦ is about 125 g
ds
mV dec−1, which is small for low power consumption devices. The effect of doping concentration on the conductance and threshold voltage of n-type Si NWFETs is shown in figure 2(a). The transfer characteristics of the drain current versus gate-source voltage (Ids–Vg) curves of several n-type Si NWFETs were obtained by sweeping the gate voltage continuously from −5 to +5 V with drain voltage at 0.1 V of devices with Si NWs at four different doping concentrations (silane (SiH4)/phosphine (PH3) ratio at 4000:1 to 10 000:1). The threshold voltage shifts from −3 V to close to 0 V as the doping concentration is reduced. We also estimated the carrier concentrations from the transfer characteristics of the drain current versus the gate-source voltage (Ids–Vg) curves by varying the silane (SiH4)/phosphine (PH3) gas ratios (i.e. by varying the doping concentrations). For instance, the electron carrier concentrations were estimated to be 91.6 × 1017 and 2.4 × 1017 e cm−3 for 4000:1 and 10 000:1 silane (SiH4)/ phosphine (PH3) gas ratios, respectively. Additionally, the reduction of ON current from 10−8 A to 10−11 A was observed when the electron carrier concentrations were lowered with decreasing doping concentrations. Note that we did not observe any variation in the nanowire diameter with the different doping concentrations. Figure 2(b) shows a schematic view of a simplified depletion model for n-type Si NWFETs with different doping concentrations at a constant negative gate voltage. The dark pink gradient shows the electric field distribution under the application of a negative back-gate voltage, resulting in depletion of the electron carriers of ntype Si NW. Furthermore, the less dense electron carriers easily induce full depletion at the same negative gate voltage. Therefore, reducing the doping concentration leads to fewer electron carriers in the conducting channel Si NWs, resulting in reduced conductance and a positive shift of the threshold voltage of Si NWFETs. The schematic diagram of the back-gate FEFET-based nonvolatile memory device and the operation mechanism of the Si nanowire ferroelectric-gate field effect transistor (NWFEFET) are shown in figure 3(a). The FEFET working mechanism has been proposed by Liao et al [5]. In our device structure, instead of using the ferroelectric layer as the backgate dielectric layer, we coated the Si NW with ferroelectric P (VDF-TrFE). When a negative Vg pulse is applied to the gate, under a negative electrostatic field gradient from the gate to the air, the polarization of the ferroelectric film will be aligned
Figure 2. (a) Ids–Vg transfer characteristics of n-type Si NWFETs at different doping concentrations—silane (SiH4)/phosphine (PH3) ratio at 4000:1 to 10 000:1. (b) A schematic view of a simplified depletion model for n-type Si NWFETs with different doping concentrations at a constant negative gate voltage.
3. Results and discussion To investigate the basic electrical properties of n-type Si NWs, we prepared a conventional NWFET on a 100 nm SiO2/ Si substrate with a back gate. Figure 1(a) shows the measured drain current versus drain-source voltage (Ids–Vds) curves of a single Si NWFET. The conductance of the NW increases monotonically as the gate potential increases in the range from −5 to +5 V, demonstrating an n-channel Si NWFET. Figure 1(b) shows the drain current versus gate-source voltage (Ids–Vg) curves by sweeping the gate voltage continuously from −5 to +10 V at a drain voltage from 0 to 0.5 V. The transconductance (gm) and the field effect electron mobility (μe) can be determined from the Ids–Vg curves using the following equations: gm = dIds dVg and μe = gmL 2 CoxVds , respectively, for the back-gate NWFETs [5]. Cox is the gate oxide capacitance of a cylindrical wire on a planar substrate and can be calculated by Cox = 2πεr ε0L cosh−1 ( 1 + tox r ) where εr = 3.9 is the relative dielectric constant, tox = 100 nm is the thickness of the SiO2 gate dielectric layer, L is the 3
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Figure 3. A Si NWFEFET memory device. (a) A schematic view of a back-gate FEFET-based nonvolatile memory device and working
mechanism. (b) Hysteretic behavior for a back-gate Si NWFEFET with P(VDF-TrFE) coated on the NW surface.
Figure 4. Memory properties of a P(VDF-TrFE)-coated Si NWFEFET-based memory: (a) retention times and (b) evolution of endurance tests of the drain currents of the Si NWFEFET device. The gate pulse was ±10 V at 100 ms pulse width, Vds = 0.1 V.
upward. The protons (H+) in the P(VDF-TrFE) are distributed on the nanowire surface, whereas the electronegative fluorine anions (F−) are oriented toward the nanowire surface upon polarization. After the gate voltage pulse is removed, the remnant polarization of the ferroelectrics introduces an effective positive field effect, and further induces an equal amount of negative space charges within the nanowire. This results in the accumulation of electrons in the n-type Si NW conducting channel to form a high conductance state in the ntype Si NW FEFET, representing the ON state of the memory device. Conversely, when a positive pulse at the back gate is applied, an OFF state is obtained due to reduced conduction by electron depletion. The depolarization field and carriers’ charge-trapping are the main problems leading to the short retention time of FEFET-based memory [1, 2]. According to Ma et al [1], the depolarization field is dependent on remnant polarization Pr. For a nanowire FEFET, the remnant polarization of the ferroelectric material should be large enough to create an electric field that induces the OFF state on the conducting nanowire channel field effect transistor (FET). This means the remnant polarization must create an electric field larger than the gate electric field that induces the threshold voltage of the FET. Our goal is to obtain long memory retention time by reducing the threshold voltage of Si NWFET. When the threshold
voltage is lower, less remnant polarization from the ferroelectric layer is required; it not only reduces the depolarization field but also reduces the leakage current and carriers’ charge trapping at the interface of the conducting channel and ferroelectric layer. The effective way to adjust the threshold voltage is to change the doping concentration. However, further reducing the threshold voltage also reduces the performance of the FET with respect to conductivity, transconductance, mobility and the ION/IOFF ratio. For our highperformance and long retention time memory devices, the optimized doping concentration was achieved at a 6 000:1 ratio of silane (SiH4)/phosphine (PH3), and a threshold voltage of ∼−1 V while maintaining a sufficient ION/IOFF ratio exceeding 105. The hysteresis behavior of a back-gate Si NWFEFET as a function of the sweep range of gate voltages is shown in figure 3(b). The positive or negative polarization of P(VDFTrFE) is induced on a Si NW depending on the gate voltage sweep direction, enabling modulation in channel conductance and threshold voltages. The hysteretic window becomes larger at a higher gate voltage sweep range, confirming that the origin of such hysteretic behavior is due to the polarization of the ferroelectric layer. In our devices, a 3 V clockwise hysteresis loop window was observed with conductance changes exhibiting a difference of more than 5 orders of magnitude 4
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Figure 5. Memory properties of a P(VDF-TrFE)-coated Si NW FEFET-based memory device: (a) retention times and (b) evolution of
endurance tests of the drain currents of the Si NWFEFET device. The gate pulse was ±5 V at 100 ms pulse width, Vds = 0.1 V. The inserted figure shows the hysteretic behavior measured when sweeping the back-gate voltage from −5 V to +5 V then back to −5 V, and −10 V to +10 V then back to −10 V.
between high and low conductance states when sweeping the back-gate voltage from −10 V to +10 V and back to −10 V, with a sweeping step of 0.1 V at Vds = 0.1 V in an ambient environment. The memory properties of the P(VDF-TrFE) coated Si NWFEFET-based memory are shown in figure 4(a) (retention times) and figure 4(b) (endurance tests) for the high and low conductance states, i.e., ON and OFF states, respectively. These were measured at Vds = 0.1 V and Vg = 0 V after the device was switched ON and OFF using +10 V writing and −10 V erasing pulses, respectively, with pulse widths of 100 ms. A large change in conductance between the ON and OFF states exceeded 105 and remained over 103 even after 3 × 104 s (8 h). It should be noted that the ON current was ∼30 nA while the OFF current was much lower, ∼200 fA at Vds = 0.1 V, which results in less than 3 nW power dissipation in the ON state. To the best of our knowledge, this is the lowest operation ON state and current power dissipation achieved while maintaining a sufficiently high ION/IOFF ratio. The quality of the Si NWs is highly dependent on the dimension and the surface states. The surface defect-induced p-type conduction of Si NWs was reported by Luo et al [20]. For an n-type Si NWFET, p-type behavior dominates at the negative gate voltage region due to surface defects, thus IOFF becomes higher at lower gate voltage. This will reduce the ION/IOFF ratio of n-type Si NWFETs. Therefore, the p-type Si NWFET is expected to have a higher ION/IOFF ratio compared to an n-type Si NWFET. However, n-type Si NWs are still the best in terms of mobility. That is why we chose n-type Si NWs over p-type Si NWs to realize high-speed memory devices. Furthermore, a high endurance of over 105 programming cycles was observed with an ION/IOFF ratio of over 104. The endurance test for both ON and OFF states was conducted after 4000 programming cycles at a fixed Vds = 0.1 V, a cycle condition of ±10 V pulse peak to peak and a 100 ms pulse width. To the best of our knowledge, this is the best ferroelectric memory performance demonstrated for nanowires as the conducting channel in FEFET memory [4–7]. It is
comparable to CNT- and graphene-based FEFET memory counterparts [8, 9, 21] in terms of retention time and endurance test results, while maintaining much higher ION/IOFF ratios, as well as better performance than thin-film-based FEFETs [22, 23] in terms of retention time. The reasons for the long retention time and high endurance of Si NWFEFET memory are related to the ferroelectricgate NWFET memory structure and Si/ferroelectric interface. These points are discussed in detail in the following paragraphs. The advantage of using nanowires as a semiconducting channel in FEFET memory is the sensitive change in conductance and the inherently small scale of each device, leading to high memory device density. Single crystalline nanowires and nanotubes often feature higher mobility and lower sub-threshold swing, allowing FET devices to work at a higher speed and lower power consumption. The important difference is that the NWFEFET working mechanism is based on the depletion–accumulation mode whereas the conventional thin-film FEFET working mechanism is based on the inversion mode. In the inversion mode, higher gate voltage and longer times are required for minor carriers to travel to form an inversion-conducting channel, compared with the depletion–accumulation mode, where major carriers under gate voltage form the conducting channel. Therefore, NWFEFET devices are expected to work at higher frequency and lower operation voltage than thin-film FEFETs. Lower operation voltage means lower remnant polarization is required for the ferroelectric layer, leading to a longer retention time in ferroelectric memory due to the reduction of the depolarization field and charge trapping effects [1, 2]. Furthermore, when an organic ferroelectric gate is used, no buffer layer is needed and an omega-shaped gate FEFET structure can be created by spin coating the organic ferroelectric layer on the top of the NW. The remnant polarization field of the ferroelectric gate then directly acts on the surface of the nanowire without any dielectric layer in between. Therefore, the remnant polarization field of an omega-shaped ferroelectric gate will be more effective than that of the 5
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omega-shaped gate in a typical NWFET and it will be much better than a NWFEFET with a planar ferroelectric gate [24, 25]. The FEFET in this work is expected to operate at lower voltage, higher ION/IOFF ratio, higher transconductance and higher field effect mobility compared with omega-shape gate NWFET as well as planar gate FEFET counterparts. Even with a small hysteresis window (i.e., less than 2 V), when sweeping the back-gate voltage from −5 V to +5 V and back, we still saw a large change in conductance between the ON and OFF states exceeding 104, which was retained over 103 after 104 s (∼3 h) of retention time and over 5 × 104 programming cycles. Cycle conditions were ±5 V pulse peak to peak with a 100 ms pulse width (see figure 5). The shorter retention time and endurance test time compared to that measured from the ±10 V gate pulses could be due to the ferroelectric P(VDF-TrFE) layer not being fully polarized at ±5 V gate pulses [6]. When compared with Si NWFEFETbased memory devices reported by Das and Appenzeller [26], our devices showed that the retention time was at least three times longer while achieving an ION/IOFF ratio of more than two orders of magnitude (see figure 4). Even at a ±5 V gate pulse (a gate pulse four times lower), our devices showed an ION/IOFF ratio of more than one order of magnitude for the same retention time (see figure 5). Such an achievement was possible because of the low depolarization field and low carrier charge trapping as a result of careful tuning of the threshold voltage of Si NWFETs. It is extremely difficult to fabricate metal oxide ferroelectric materials such as PZT or BTO on Si and form a good interface because of the chemical reaction and inter-diffusion of Si into the ferroelectric layer [27]. Such issues lead to the creation of a gate leakage current and/or the trapping of carriers in the gate dielectric stack, resulting in reduced retention time of the memory devices [1]. To improve the interface properties, the use of a thick buffer layer at the interface such as SiO2, Al2O3 or HfO2 to reduce the leakage current and charge carrier trapping has been applied for thinfilm-based FEFET memory. However, insertion of the buffer layer causes other problems, such that the data retention period becomes shorter and higher gate voltages are required due to the effect of the depolarization field [1–3]. Another solution is to use oxide semiconductors to obtain a good ferroelectric/semiconductor interface [3]. However, the mobility of metal oxide semiconductors is still lower than Si, so this would be a disadvantage in high-performance nonvolatile memory devices. The superior mobility and small size of CNTs and graphene ribbons makes these materials suitable candidates for replacing the Si conducting channel; as such, they are considered to be next-generation FEFET memory devices. CNTs and graphene ribbons used as the conducting channel for FEFET memory applications have demonstrated long retention times, high endurance, and high mobility [8, 28–32]. However, graphene FEFETs still suffer from a low ION/IOFF ratio and OFF-state leakage problems due to various tunneling mechanisms and ambipolar behavior. The difficulty in selecting metallic or semiconductor CNTs continues to limit their use in industrial applications.
In our memory devices, P(VDF-TrFE) is used as a ferroelectric gate. The simple process used to form ferroelectricity, which is just thermal annealing after spin coating above the Curie temperature (lower than 140 °C), results in no interfacial layer formation during the crystallization process. Without an interfacial layer, charge-trapping effects at the interface of the surface organic film and the Si NW semiconductor channel are minimized. When direct contact is realized in a FEFET, the data retention time is likely to be much longer than that in a conventional FEFET because no depolarization field is generated due to the buffer layer. Furthermore, with a low-temperature fabrication process, these devices can be fabricated on flexible substrates for flexible nonvolatile memory applications. Compared with the BTO particle-coated ZnO NWFEFET memory devices reported by Sohn et al [6], our approach allows more uniform coating over a large area and facile control of the ferroelectric layer thickness by simply changing the spin coating speed. In addition, if the P(VDF-TrFE) ferroelectric layer is patterned only on the conducting channel, e.g. by using a water-soluble photoresist [13], soft lithography [14], nanoimprinting lithography [15] or photolithography with a common photoresist (PR) developed by a diluted PR stripper [16], the typical parasitic effects on the electrodes can be minimized. Therefore, further enhancement of memory performance is expected in terms of retention time, offering a great opportunity for viable industrial applications. A smaller hysteresis window was observed in a conventional back-gate FET, exhibiting the typical electrical behavior of an n-type channel Si NWFET (see figure S2(c) in the supporting information). This hysteresis was caused by the trapped charges of carriers at the SiO2/Si interface due to immobile oxide charges or oxide-trapped space charge associated with defects in SiO2 [33]. We also investigated the memory properties due to these effects (see figure 2(d) in the supporting information). A rapid reduction in conductance between the ON and OFF states to over 102 after 1000 s (less than 20 min) was observed after the device was switched ON and OFF using +10 V writing and −10 V erasing pulses, respectively. This provides further confirmation that the measured memory properties of P(VDF-TrFE)-coated Si NW FEFET are due to the remnant polarization of the ferroelectric layer. Our results imply that such NW channel FEFET devices are promising for random access memory applications. For nonvolatile memory applications, where a ten-year retention time is required for a viable nonvolatile semiconductor memory technology, there is still much room for improvement. A primary limitation when using nanowires as a conducting channel is the large diameter of the nanowires (larger than 50 nm). Reducing the nanowire diameter is expected to reduce the operating voltage. When the operating voltage is reduced, other potentially detrimental effects in the device may be suppressed, such as depolarization of the ferroelectric field, leakage current and charge trapping. Moreover, when the diameter of the nanowire reaches that of the Bohr radius of the material (typically
