Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system Jia-Jia Jiang, Fa-Jie Duan, Yan-Chao Li, and Xiang-Ning Hua Citation: Review of Scientific Instruments 85, 034701 (2014); doi: 10.1063/1.4868440 View online: http://dx.doi.org/10.1063/1.4868440 View Table of Contents: http://scitation.aip.org/content/aip/journal/rsi/85/3?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Analysis on multiple-component synchronization of ultra-fast time-interleaved analog-to-digital conversion systems and its novel parameterized hardware solution Rev. Sci. Instrum. 85, 105107 (2014); 10.1063/1.4899064 VHDL Implementation of Sigma‐Delta Analog To Digital Converter AIP Conf. Proc. 1324, 381 (2010); 10.1063/1.3526239 Flexible lock-in detection system based on synchronized computer plug-in boards applied in sensitive gas spectroscopy Rev. Sci. Instrum. 78, 113107 (2007); 10.1063/1.2813346 Delta-sigma digital magnetometer utilizing bistable spin-dependent-tunneling magnetic sensors J. Appl. Phys. 99, 08B320 (2006); 10.1063/1.2171942 An optoelectronic thyristor-based analog-to-digital converter for parallel processing Appl. Phys. Lett. 73, 2372 (1998); 10.1063/1.122464

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REVIEW OF SCIENTIFIC INSTRUMENTS 85, 034701 (2014)

Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system Jia-Jia Jiang, Fa-Jie Duan, Yan-Chao Li, and Xiang-Ning Hua State Key Lab of Precision Measuring Technology and Instruments, Tianjin University, Tianjin 300072, China

(Received 28 August 2013; accepted 26 February 2014; published online 19 March 2014) Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. We first present a master-slave synchronization sampling model, and then design a high accuracy phase-locked loop to synchronize all delta-sigma ADCs to a reference clock. However, when the master-slave synchronization sampling model is used, both the time-delay (TD) of messages traveling along the wired transmission medium and the jitter of the clocks will bring out synchronization sampling error (SSE). Therefore, a simple method is proposed to estimate and compensate the TD of the messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks. An experimental system with three ANs is set up, and the related experimental results verify the validity of the synchronization sampling method proposed in this paper. © 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4868440] I. INTRODUCTION

Synchronization sampling is essential for distributed wired and wireless data acquisition system.1 The underwater towed array system2, 3 is a special distributed wired data acquisition system due to both its chain distribution structure along the linear cable and a large number of acquisition nodes (ANs), and thus it also requires a good synchronization sampling method so as to achieve a high precision synchronization. This is a foundation4 of the relevant array signal processing. For example, for a sonar detection system 5, 6 using an underwater towed array system, time difference of arrival localization requires the sensors to be synchronized accurately in sampling the received signals.7–9 Several solutions have been proposed to achieve synchronization sampling in distributed data acquisition systems, such as Network Time Protocol (NTP),10 IEEE 1588 Precision Time Protocol (PTP),11 and GPS synchronization method.12 The SSE that is usually obtained using NTP is on the order of a few milliseconds.1 The SSE of IEEE 1588 PTP is superior to NTP and reaches on the order of a few microseconds.1 GPS can guarantee a higher level of SSE (about 100 ns), while it is inapplicable for underwater system, such as the underwater towed array system. In addition, for the underwater towed array system, several synchronization sampling methods13–16 have also been presented to decrease the SSE. Reference 2 gives a simple analysis about the synchronization sampling. Moreover, the synchronization sampling method proposed by Harold16 gains lower SSE than some previous synchronization sampling methods,13–15 but its SSE is still up to tens of microseconds, which is unacceptable for some high accuracy time difference of arrival localization.17 The master-slave synchronization technique2, 18 is a kind of valuable synchronization method for the distributed system. Its working mechanism is

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that, a high-performance clock (master clock) is set in master node, and then all slave nodes extract the clock from the data stream with master clock information. The clock which the slave node obtains is usually called as the recovery clock, and the recovery clock is able to obtain the same frequency and phase with the master clock when ignoring the TD and jitter of clock. Some other methods,2, 18 based on the master-slave synchronization technique, have also been proposed to achieve the synchronization sampling. However, the synchronization technique in Ref. 18 is designed for an application scenario of wireless communication, and thus it is unsuitable for underwater systems. Although based on the master-slave synchronization technique, the synchronization method in Ref. 2 did not consider both the TD and jitter of clocks.19 In this paper, in order to attain a high-performance synchronization sampling for the underwater towed array system, a simple and effective synchronization sampling method is proposed based on delta-sigma analog-digital converter (ADC). The main contribution of this paper can be summarized as follows: (1) a synchronization sampling model, which is suitable for underwater distributed wired data acquisition systems, is proposed; (2) then, based on this synchronization sampling model, the mechanisms, that both the TD and jitter of clocks cause the SSE, are analyzed; (3) finally, a simple method is proposed to estimate and compensate the TD of messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks; (4) the outstanding advantage of this paper is that it achieves a higher level of synchronization accuracy (the SSE is below 10 ns). II. STRUCTURE OF TOWED ARRAY SYSTEM

The towed array system2 mainly consists of analysis and control system (ACS), a large number of ANs and

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FIG. 1. The towed array system.

hydrophones (see Fig. 1). The ACS is used to send various messages to all ANs through the wired downlink transmission medium. In each AN, K channels analog signals are sampled and then converted synchronously into digital detection data by multiple delta-sigma ADCs. Then, each AN sends the detection data back to ACS.

III. PROPOSED SYNCHRONIZATION SAMPLING MODEL

The master-slave synchronization sampling model for the underwater towed array system is shown in Fig. 2. A temperature controlled crystal oscillator (TCXO) is set in ACS and serves as a reference clock (its frequency is denoted by f1 ). This reference clock is called as the master clock (MC) and other various clocks are derived from this MC. Based on a synchronous transmission technique at the frequency f1 , the ACS sends various messages to all ANs through the wired downlink transmission medium. A synchronization reference clock (SRC) module is designed in ACS. It is used to generate a SRC to synchronize the conversion process of all delta-sigma ADCs, and thus the frequency of this SRC is equal to the sampling rate (it is denoted by fm ) of ADCs. In each AN, one driver and one receiver are used to drive and equalize the signal along the wired downlink transmission medium respectively so as to enlarge the transmission distance of signal. Note that a special driver and a receiver, which can bring out a constant TD on the signal, are chosen in this underwater towed array system, such as the driver chip LTC1688 (it is produced by Linear Technology Corporation and its TD is equal to 8 ns) and receiver chip LTC1518 (it is produced by Linear Technology Corporation and its TD is equal to 18.5 ns). In each AN, a digital phaselocked loop (DPLL)20 is used to extract and recover the MC from the downlink data stream and then the sampling clock is obtained from the recovered MC in order to drive the deltasigma ADC. Note that the synchronization of the sampling clocks depends on the type of the ADC used in the AN; the sigma-delta ADCs need an N-times greater clock frequency

than the sampling rate (fm ), as the sigma-delta modulation is based on over-sampling (N is typically 512 for chip ADS1278 which is produced by Texas Instruments corporation), and we call this clock as over-sampling clock (OSC) (obviously, its frequency f2 is equal to Nfm ). A node process module (NPM) in each AN is also used to generate a SRC to synchronize the conversion process of all delta-sigma ADCs in the same AN, and send the detection data back to ACS. In each AN, multiple delta-sigma ADCs are used to convert the analog signal into digital detection data. Remark 1: It is noted that, generally, each delta-sigma ADC chip has a “data ready (DRDY) output” pin, such as the 29th pin of chip ADS1278, and when data are ready, this DRDY pin goes low. Meanwhile, since the “group delay” caused by a typical oversampling delta-sigma ADC is constant, therefore, the level change (from high to low or from low to high) of DRDY pin, which indicates that data are ready, can be used to synchronize all delta-sigma ADC. IV. ANALYSIS OF SSE BASED ON THE PROPOSED SYNCHRONIZATION SAMPLING MODEL

Although the master-slave synchronization sampling model is presented in Sec. III, a high accuracy synchronization sampling result cannot be attained with only this model, which is because the TD of messages traveling along the wired transmission medium and the jitter of the clocks will bring out the SSE. In the following content, we will analyze the mechanism that the TD of messages traveling along the wired transmission medium and the jitter of the clocks result in the SSE. In Fig. 3, the SRC in ACS is generated by dividing the MC (see Fig. 2), and its frequency is equal to the sampling rate fm . The SRC in AN(i) is generated by the NPM. The TD ti , i = 1, 2, . . . , n between the SRC in ACS and the SRC in AN(i) is caused by the TD of messages traveling along the wired transmission medium, the reason of which will be stated in detail in Sec. V B. The falling edge of DRDY output signal of delta-sigma ADC in AN(i) is locked to the SRC in AN(i) through the high accuracy phaselocked loop (HAPLL), whose implementation process will be shown in Sec. V C. In this underwater towed array system, in order to inform all ANs to start the process of sending detection data, the ACS sends a command of “starting to send data (SSD)”, at the falling edge of SRC in ACS, to all ANs. And then when receiving the command of “SSD”, each AN will start to send its detection data back to the ACS

FIG. 2. The synchronization sampling model.

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FIG. 4. Generation of the synchronization reference clock (SRC) in AN(i). FIG. 3. The time-delay (TD) of messages and the jitter of clocks.

from the falling edge of its subsequent SRC. ts,i , i = 1, 2, . . . , n denotes the TD of “SSD” traveling from the ACS to AN(i). On the one hand, AN(i) completes once data conversion through ADC at ti , i = 1, 2, . . . , n (this corresponds to the falling edge of DRDY output signal). Since t1 = . . . = ti due to the TD, the SSE is brought out. On the other hand, since there exists the jitter of clocks (such as jitter of SRC and DRDY signals), the relationship between ti and ts,i can be divided into two cases: ti > ts,i or ti ≤ ts,i . Further, if ti > ts,i , AN(i) will start to send detection data, which has been converted just by ADC at ti , back to the ACS; and if ti ≤ ts,i , AN(i) will start to send detection data, which has been converted just by ADC at ti + Tm , back to the ACS, where Tm = 1/fm denotes the sampling period of ADCs. From the above analysis, one can find that when only the synchronization sampling mode proposed in Sec. III is used, the SSE cannot be overcome. Therefore, in order to compensate and overcome the SSE (it is caused by the jitter of the clocks and the TD of messages traveling along the wired transmission medium), other SSE calibration methods must be applied. In the following content, we will first describe the implementation methods of key modules of system, including how to extract and recover the MC through the DPLL, how to generate the SRC in ACS, SRC in AN(i), and how to design the HAPLL in Sec. V. And then in Sec. VI, we propose a SSE calibration method to compensate and overcome the SSE caused by the TD of messages traveling along the wired transmission medium and the jitter of the clocks.

B. Generation of the SRC in AN(i)

The generation procedure of the SRC in AN(i) is as follows (see Fig. 4). Step 1: the ACS periodically sends a special characters 10B code21 (such as K28.1) to all ANs in a T1 period. Step 2: in each AN, the NPM divides the recovered MC into the SRC by means of a frequency divider whose divider ratio is f1 /fm . Considering the phase ambiguity caused by the frequency divider, the SRCs in different ANs have different initial phases; however, in Fig. 3, there only exists a constant TD among SRCs of different ANs. Therefore, in order to overcome the initial phase ambiguity and obtain a constant TD among SRCs, we design an asynchronous reset pin (ARP) to reset the original value of the frequency divider to zero. Further, when the decoder recognizes the special characters 10B code K28.1, the ARP become active high, and the frequency divider is forced to output a logical low level straight away and then the counter of the frequency divider starts counting from zero again (see Fig. 4). Accordingly, from Fig. 5, we can observe that before receiving the special characters 10B code K28.1, ANs output the SRCs complying with their initial phase value; however, when receiving the special characters 10B code K28.1, ANs output the matching SRCs and the TD differences among SRCs in different ANs become constant, which is consistent with the result in Fig. 3. Note that T1 between two APRs must be an integer multiple of Tm , and it is easy to achieve this point. C. Design of HAPLL

Since there may exists multiple ADCs in the same AN, in order to synchronize all ADCs in the same AN, an HAPLL in

V. IMPLEMENTATION METHODS OF KEY MODULES A. Recovery of the MC through the DPLL and generation of the SRC in ACS

In each AN, a DPLL is designed to extract and recover the MC from the downlink data stream, and the frequency of the recovered MC is equal to f1 . The DPLL can be designed according to the method of Ref. 20 or is achieved by a clock data recovery integrated chip, such as ADN2816 which is produced by Analog Devices Corporation. Moreover, in ACS, the MC (f1 ) is converted into the SRC (fm ) by the frequency divider (see Fig. 2).

FIG. 5. Waveform of the synchronization reference clock (SRC) in AN(i) (i = 1,2, . . . ,n).

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FIG. 6. Structure of the high accuracy phase-locked loop (HAPLL) in each AN.

AN(i) is designed to achieve two goals: (1) lock the frequency and phase of the DRDY output signal to that of the SRC in AN(i); and (2) lock the phase of the OSC to that of the SRC in AN(i). The HAPLL is composed of a phase/frequency detector (PFD), a loop filter (LF), a voltage controlled and temperature compensated oscillator (VCTCXO) and an ADC, which plays the role of a frequency divider with a division ratio of N (Fig. 6). Depending on the HAPLL in each AN, the OSC can be obtained so as to drive all ADCs to synchronously achieve the conversion process of analog signals. Note that in order to guarantee that the OSC, which is used to drive the ADC, has small fluctuation, we use a high-stability VCTCXO. The center frequency of this VCTCXO is 16.384 MHz, and its frequency pulling range, frequency stability, and phase noise are ±10 ppm, ±1 ppm, and −138 dBc/Hz at 1KHz, respectively. When the HAPLL is “locked,” the falling edges of relevant signals can be aligned as Fig. 7. VI. SSE CALIBRATION METHOD

In order to calibrate the SSE (see Fig. 3) caused by the TD of messages traveling along the wired transmission medium and the jitter of the clocks, a simple method is proposed to first estimate and compensate the TD of messages transmission, and then overcome the SSE caused by the jitter of the clocks. Figure 8 shows the inductive process of SSE calibration, including waveforms of related signals before the SSE calibration and ones after the SSE calibration. In the following content, we will describe the calibration process of SSEs in detail. A. Estimate TD

In practice, the number of ANs is large, and thus it is difficult to measure all TD ti for i = 1, 2, . . . , n. Therefore,

FIG. 7. Waveforms of synchronization reference clock (SRC) and oversampling clock (OSC) in AN(i), and DRDYs of ADC(1) and ADC(2).

FIG. 8. Waveforms of the proposed calibration method.

in this paper, in order to overcome this issue, we first propose a simple method to estimate the TD ti for i = 1, 2, . . . , n. The TD caused by the wired transmission medium includes two parts: (1) the TD caused by the transmission wire and (2) the TD caused by signal driver/receiver. Therefore, the total TD caused by the wired transmission medium can be estimated by ti = tdr + itdr + itre + lda tw + (i − 1)laa tw ,

(1)

where tdr denotes the TD caused by the signal driver (see Fig. 2), tre denotes the TD caused by the signal receiver, tw denotes the TD caused by the unit length (1 m) transmission wire, lda denotes the length of the transmission wire between the ACS and AN(1), and laa denotes the length of the transmission wire between ANs (Note that, in practice, the length of the transmission wire between ANs is constant and known). Therefore, we have td,i = tn − ti = (n − i)(tdr + tre + laa tw ),

(2)

where td,i denotes the TD between AN(i) and AN(n). From (2), it can be seen that td,i is associated with two variables (i and laa ) and four constants (tdr , tre , tw and n). When a “precision delay line driver and a receiver (such as signal driver LTC1688 whose TD is equal to 8 ns and signal receiver LTC1518 whose TD is equal to 18.5 ns)” are used, tdr and tre are easy to be obtained; for example, the TD caused by the signal driver LTC1688 is a known constant (8 ns), and the TD caused by the signal receiver LTC1518 is also a known constant (18.5 ns). tw is also easy to be computed, and when i is known, the lda is also known. Therefore, according to the analysis above, the TD td,i between AN(i) and AN(n) is easy to be estimated.

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B. Calibrate TD

In Sec. V C, we have designed the HAPLL to ensure the conversion synchronization of different delta-sigma ADCs in the same AN; however, due to the TD of messages transmission, the conversion synchronization of different delta-sigma ADCs in different ANs cannot be achieved (see Fig. 3 or Fig. 8), that is to say, the SSE exists in different ANs. Therefore, in order to calibrate the SSE caused by the TD, we propose a TD compensation method. In AN(i) (i = 1,2,. . . ,n), a TD module (TDM) is set, and this TDM performs a constant TD td,i to the SRC of AN(i). From (2), one can know td,i = tn − ti , i = 1, 2, · · · , n, and thus after each AN performs a constant TD td,i to its SRC, the waveforms of “region B” in Fig. 8 can be obtained. From the waveforms of “region B,” one can see that the SSE caused by the TD has been calibrated and thus the conversion synchronization of different delta-sigma ADCs in different ANs is achieved since the DRDY output signals of all ADCs have the same falling edge at the same moment tn (see Fig. 8). Note that, although the SSE caused by the TD has been calibrated depending on the above TD compensation method, according to the analysis in Sec. IV the SSE may be caused by the jitter of clocks (such as jitter of both SRC and DRDY signals). Therefore, in the following Sec. VI C, we will propose a method to overcome the SSE caused by the jitter of clocks.

FIG. 10. Frame format of sending time-delay (TD) calibration time.

Since the TD calibration time td,i + Tcon (see Fig. 9) can help to avoid the SSE caused by both the TD of messages traveling along the wired transmission medium and the jitter of the clocks, td,i + Tcon can be called as “safe time.” D. Distribution of the TD calibration time

Since all ANs have the same hardware and software, it is not practical that a unique TD calibration time td,i + Tcon is, one by one, set to AN(i). Therefore, we let the ACS send the TD calibration time td,i + Tcon to AN(i) according to the address of AN(i) via the downlink wire with a special frame format (Fig. 10). So far, the calibration results in “region C” of Fig. 8 are achieved, which indicates that AN(i)(i = 1,2,. . . ,n) receives “SSD” command at ti , all ANs complete one conversion of analog signals at the falling edge of DRDY output signals (tn + Tcon ), and all ANs send the detection data, which are converted at tn + Tcon , back to the ACS. VII. EXPERIMENTAL RESULTS AND ANALYSIS

C. Overcome jitter of clocks

As the analysis in Sec. IV shows, the SSE of a sampling period Tm may exist due to the jitter of clocks, which is because if ti > ts,i , AN(i) will start to send detection data, which has been converted just by ADC at ti , back to the ACS; and if ti ≤ ts,i , AN(i) will start to send detection data, which has been converted just by ADC at ti + Tm , back to the ACS. Therefore, to overcome the effect of jitter of clocks on the synchronization sampling, an extra TD Tcon is added to the TDM of each AN (see Fig. 9) and then the conversion synchronization of different delta-sigma ADCs in different ANs is achieved since the falling edges of DRDY output signals of all ADCs are synchronized to the same moment tn + Tcon (see the waveforms of “region C” in Fig. 8). Note that in order to overcome the effect of the jitter of both SRC and DRDY signals, Tcon must satisfy (|θS | + |θD |) · Tm < Tcon , (3) 2π where |θ S | denotes the largest phase jitter of SRCs and |θ D | denotes the largest phase jitter of DRDY output signals.

FIG. 9. Setup and operating principle of time-delay module (TDM).

In order to verify the validity of the proposed synchronization sampling model and method, we setup an experimental system with three ANs (Fig. 11). The maximum sampling rate of this system is fm = 4000 Hz as Ref. 2 and thus the highest acoustic frequency which this system can detect is less than 2000 Hz. When the sampling rate of this system is set to fm = 4000 Hz, the maximum number of this system multiplexing is 128 channels. The distance between two consecutive ANs was set to 6.25 m (the minimum distance between two consecutive nodes can reach up to 1 m in this system). Each AN contains 16 signal acquisition channels (two ADS1278 chips are used to digitalize 16 channels analog signal). The signal sampling rate was set to fm = 4000 Hz.2 The unshielded cat twisted-pair cable was used as the wired transmission medium. The length of the transmission wire from the ACS to AN(1) was 110 m, and the length of the transmission wire between ANs was 100 m. The frequency f1 of the MC was set to f1 = 16.384 × 106 Hz, which indicated that the data transmission bit rate of downlink data stream was 16.384 Mbps, and the signal driver and receiver used LTC1688 (8 ns TD) and LTC1518 (18.5 ns TD), respectively. The TDM in each AN was achieved by a Field Programmable Gate Array (FPGA) whose clock frequency was 196.608 MHz. Note that to facilitate the observation of the measurement results, the waveforms of both DRDY and SRC signals first were inputted to the NOT gate and then output. The TD tw caused by the unit length (1 m) transmis√ sion wire can be derived from Ktr = 3.35 × 10−9 ξr (see Ref. 22) or can be measured easily, where ξ r denotes the effective relative permittivity. In the first experiment, we compared the estimates and measurements of TDs t1 , t2 , and t3 . The estimates of

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FIG. 11. The experimental setup.

TDs t1 , t2 , and t3 are denoted by tˆ1 , tˆ2 , and tˆ3 respectively, and the measurements are denoted by t¯1 , t¯2 , and t¯3 respectively. Since tdr , tre , and lda are known, tw can be computed if the TD ta,b between a point and b point in Fig. 2 can be measured. The TD measured result ta,b from a point to b point in Fig. 2 was shown in Fig. 12. From Fig. 12, one could know that the TD ta,b , which is caused by one driver, one receiver and 110 m transmission wire, is 305 ns. And thus tw can be computed as tw = (ta,b − tdr − tre )/ lda = 2.53 ns. Then, according to (1), one could obtain the estimates tˆ1 = 305 ns, tˆ2 = 610 ns, and tˆ3 = 915 ns of TDs t1 , t2 , and t3 , respectively. At the same time, through measurement, the measurements t¯1 , t¯2 , and t¯3 of TDs t1 , t2 , and t3 were shown in Figs. 13(a), 13(b), and 13(c). From Figs. 13(a), 13(b), and 13(c), one could see that the measurements t¯1 , t¯2 , and t¯3 were 305 ns, 612 ns, and 918ns, respectively. After comparing the estimates and measurements of TDs t1 , t2 , and t3 , one could find that the estimates tˆ1 , tˆ2 , and tˆ3 were very close to the measurements t¯1 , t¯2 , and t¯3 respectively, which verified the validity of the proposed TD estimation method. At the same time, considering that in a normal working state the DRDY output signal in each AN is locked to the SRC signal, thus t¯2 − t¯1 = 307 ns can denote the SSE between AN(1) and AN(2) before the SSE, which is caused by both the TD of messages traveling along the wired transmission medium and the jitter of the clocks, is calibrated and over-

FIG. 13. (a) The measurement t¯1 Fig. 13, (b) the measurement t¯2 Fig. 13, and (c) the measurement t¯3 .

FIG. 12. The measured TD ta, b from a point to b point.

come, and t¯3 − t¯2 = 306 ns can denote the SSE between AN(2) and AN(3) before the SSE is calibrated and overcome. In the second experiment, the operating state of the HAPLL was shown in Fig. 14. From Fig. 14, it could be seen that when the HAPLL was in the normal working state, the DRDY output signal could be locked to the SRC signal and the HAPLL hold steady at the “locked” state.

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FIG. 14. The status of the HAPLL being “locked.”

In the third experiment, the SSE, which was caused by both the jitter of the clocks and the TD of messages traveling along the wired transmission medium, was calibrated and overcome first. And then by observing the time difference of DRDY output signals of different ANs, we measured the residual SSE between different ANs. Figure 15(a) showed the time difference of DRDY output signals between AN(1) and

FIG. 15. (a) The time difference of DRDY output signals between AN(1) and AN(2) Fig. 15(b). The time difference of DRDY output signals between AN(2) and AN(3).

Rev. Sci. Instrum. 85, 034701 (2014)

AN(2), and Fig. 15(b) showed the time difference of DRDY output signals between AN(2) and AN(3). From Fig. 15(a) and 15(b), it could be seen that when the SSE was calibrated and overcome by the proposed method in this paper, the SSEs between ANs were less than 10 ns (it is much smaller than t¯2 − t¯1 and t¯3 − t¯2 in the second experiment), which was obviously and signally superior to the tens of microseconds SSEs of the existing synchronous sampling method in Ref. 16. Therefore, the proposed synchronization sampling method achieves a high accuracy synchronization sampling. Further, the TDM in each AN was achieved by a FPGA whose clock frequency is 196.608 MHz, so the minimal operation period TF _clk of the TDM was about TF _clk = 1/196.608 MHz ≈ 5.086 ns. However, the TD calibration time td,i + Tcon is not always an integral multiple of TF _clk ; therefore, the TD calibration error caused by the TDM is brought out, and the size of this error is no more than TF _clk . Meanwhile, the TDs of both the signal driver (LTC1688) and the receiver (LTC1518) also have small error. Therefore, after all calibration procedures were accomplished, the residual

FIG. 16. (a) Output waveforms of representative 8 channels when a sine is simultaneously inputted into 48 channels of three ANs. Figure 16(b) in different time, the output waveforms of representative 1, 2, 13, 14, 18, 19 channels and ones of representative 27, 28, 35, 36, 41, 42 channels when discrete impulse acoustic signal are simultaneously inputted into 48 channels of three ANs.

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SSE with less than 10 ns still existed. Therefore, in order to decrease the SSE, an FPGA, whose clock frequency is more than 196.608 MHz, can be used. At the same time, based on the measurement and calibration principle of SSE proposed in Sec. II–VI, one could know that none accumulative error can appear, and thus the error difference could not be enlarged when the number of AN grew; and the experiment results in Figs. 2 and 3, that the DRDY in AN(1) was ahead of one in AN(2), while the DRDY in AN(2) was behind of one in AN(3), also proved this conclusion that none accumulative error was able to appear. In the last experiment, we observed the result of field tests performed on the underwater towed array system. First, we generated a sine wave, whose frequency and signal-to-noiseratio (SNR) are 50 Hz and 5 dB respectively, and then input it into 48 analog signal input channels of three ANs. Each AN converted the analog signal into digital detection data and then send them back to the ACS. Finally, the detection data were shown on the computer screen, as shown in Fig. 16(a). Note that in Fig. 16(a), waveforms of only representative 8 channels were shown. Then, 48 hydrophones were connected to 48 analog signal input channels of three ANs respectively, and discrete impulse acoustic signals with SNR ≈ 6 dB were generated. Each AN converted the analog signal into digital detection data and then send them back to the ACS, and the detection data were shown on the computer screen, as shown in Fig. 16(b). Note that it was not convenient for us to simultaneously observe the output waveforms of 48 channels, and thus the output waveforms of representative {1, 2, 13, 14, 18, 19} channels and those of representative {27, 28, 35, 36, 41, 42} channels were shown respectively in different time. From Fig. 16(a) and 16(b), it can be seen that the towed array system designed in this paper has a high phase congruency and superior synchronization sampling accuracy. VIII. CONCLUSION

In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. A master-slave synchronization sampling model first is designed to serve as a physical structure and foundation of the proposed synchronization sampling method. Then based on the synchronization sampling model, a novel method is presented to generate SRC to each AN for constant time difference between ANs. An HAPLL is designed to generate an OSC to drive the ADCs and lock the DRDY output signals of each ADC to its SRC. The effects, of the TD of messages traveling along the wired transmission medium and the jitter of the clocks, on SSE are analyzed, and then a simple and effective method is proposed to avoid the effects. The related experimental results are consistent with the theoretical analysis, and demonstrate the validity of the proposed synchronization sampling method in this paper. Depending on the proposed synchronization sampling method in this paper, the SSE can be reduced to be less than 10 ns, which is obviously superior to the existing synchronization sampling method.

Rev. Sci. Instrum. 85, 034701 (2014)

ACKNOWLEDGMENTS

This work was supported in part by the National Natural Science Foundation of China under Grant Nos. 51275349 and 50375110, by the China New Century Excellent Talents under Grant NECT, by the China Tianjin Science and Technology to support key projects under Grant No. 11ZCKFGX03600, and by the China Tianjin Science and Technology Sea Project under Grant No. KX2010-0006. 1 A.

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Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system.

Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog...
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