Article

Smart Capture Modules for Direct Sensor-to-FPGA Interfaces Óscar Oballe-Peinado 1,2 , Fernando Vidal-Verdú 1,2, *, José A. Sánchez-Durán 1,2 , Julián Castellanos-Ramos 1,2 and José A. Hidalgo-López 1,2 Received: 10 October 2015; Accepted: 11 December 2015; Published: 16 December 2015 Academic Editor: Vittorio M. N. Passaro 1

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Departamento de Electrónica, Universidad de Málaga, Andalucía Tech, Campus de Teatinos, Málaga 29071, Spain; [email protected] (O.O.-P.); [email protected] (J.A.S.-D.); [email protected] (J.C.-R.); [email protected] (J.A.H.-L.) Instituto de Investigación Biomédica de Málaga (IBIMA), Málaga 29010, Spain Correspondence: [email protected]; Tel.: +34-952-133-325; Fax: +34-952-133-324

Abstract: Direct sensor–digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor. Keywords: direct sensor-to-digital device interface; FPGAs; parallel analog data acquisition

1. Introduction The incorporation of advanced technology into daily life requires complex smart systems able to face tasks in unstructured environments where events cannot be predicted. This means that smart systems that can acquire a huge amount of data from sensors and other processing devices have to be developed. Several solutions are possible to cope with this, and a tradeoff between throughput and complexity can determine which is chosen for a specific application. The number of input channels is a key aspect in the complexity of the system. Analog sensors make up around 50% of the sensors on the market [1]. The common approach for data acquisition from analog sensors is some signal conditioning circuitry, mostly based on operational amplifiers, plus an analog to digital converter. As the number of sensors increases, i.e., they become more complicated, several analog to digital converters are required. Microcontrollers usually have a multiplexer to share one analog to digital converter between a set of analog input channels [2]. Therefore, data acquisition is carried out in a sequential way. Since processing is also performed sequentially by the CPU of the microcontroller, the input-output delay to respond to a certain event increases. Therefore, the cost and size of the system also increases owing to the need for external signal conditioning circuitry. Finally, this realization is limited by the number of A/D channels of the microcontroller. An alternative to the above approach is the direct sensor-microcontroller interface [3]. This approximation consists basically in measuring a time interval whose length is determined by the Sensors 2015, 15, 31762–31780; doi:10.3390/s151229878

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resistance or capacitance of a resistive or capacitive sensor respectively. Such implementation requires few external components. Regarding the microcontroller resources, a general purpose I/O pin can be used as input interface. However, to reduce error in measuring the time caused by other activity in the microcontroller, it must be kept in sleep mode or a specific capture module must be used. The former will obviously reduce the system throughput, while the latter is quite limited in number. Such restrictions are overcome if a Field Programmable Gate Array (FPGA) is used instead of a microcontroller. The reason is that the internal hardware can be configured to have many blocks working in parallel. This has been exploited to execute complex processing algorithms in real time [4], and the same strategy can be applied to carry out massive parallel data acquisition from analog capacitive or resistive sensors [5]. The lack of Schmitt Trigger input buffers is a drawback of the FPGAs when compared to microcontrollers in the context of direct interface with sensors. The hysteresis of these buffers reduces uncertainty due to trigger noise associated with the detection of the instant when the input signal (with a slow slew rate) crosses the threshold of the input buffer. This event signals the end of the time interval to be measured, so trigger noise limits the precision of measurement. Moreover, the threshold VIL related to low logical value of the Schmitt Trigger input buffers is more robust against noise superimposed on the power supply [6]. The proposal in [7] introduces hysteresis by implementing a block composed of an input buffer, an output buffer to add positive feedback, and two external resistors. Together with the RC network R or C can both be the sensor) the resulting circuit is a relaxation oscillator whose output waveform, i.e., its period or the duration of a semi-cycle, can be used to obtain the measurand value. The hysteresis size can be controlled by the resistance of the external resistors. Though robust to trigger noise, the input impedance of the implemented block is low, and the voltage excursion at the output node of the RC network is limited by the hysteresis value. As a consequence, the dynamic range is not clearly improved by this strategy. This paper presents some capture input blocks implemented in an FPGA. They take the input from the common RC networks used in direct interfaces and provide an output to signal the end of the time interval to be measured. The resources in the FPGA allow digital circuits to be built that detect the first change of logical value at the input buffer when the input signal reaches the threshold. Instead of adding analog positive feedback [7], such feedback is implemented in digital circuits to achieve the memory of the hysteresis cycle. Moreover, smarter capture modules can be used to improve performance and precision. For instance, modules that are robust enough to isolated glitches in the input signal. In addition, the flexibility of the storage elements in the FPGA to be synchronized with both edges of the clock signal, and also the detection of, not only the first but the last transition at the output of the input buffer is exploited to carry out averaging. This actually filters part of the trigger noise and achieves more precision without losing bandwidth. Regarding accuracy, it is mainly limited by the impedance of the input buffers of the FPGA [8,9]. Single-point or two-point calibration techniques can be used to improve accuracy. They require one external resistor and one additional FPGA pin, or two external resistors plus two additional FPGA pins, respectively. This paper compares the performance obtained with both methods. Moreover, it explores the implementation of another strategy that stores parameters obtained from previous characterization of the input buffers in the FPGA. Such strategy uses less external resources than the two-point technique and achieves similar accuracy, though it requires a previous characterization step. 2. Direct Interface with Sensors Figure 1 illustrates the procedure to implement direct interfaces between digital input ports and capacitive or resistive sensors. The measurement is taken in two steps. Firstly, the capacitor C is charged through the port M configured as output buffer with output corresponding to a logical value “1” (see Figure 1a). Secondly, the capacitor is discharged through the resistor R x and the port D configured as output buffer with output corresponding to a logical value “0” (see Figure 1b).

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value ‘1’ (see Figure 1a). Secondly, the capacitor is discharged through the resistor Rx and the port Sensors 2015, 15, 31762–31780

D configured as output buffer with output corresponding to a logical value ‘0’ (see Figure 1b). The measurand value is related to the time it takes to discharge the capacitor, and it can be obtained if the voltage drop in value it is monitored. can be donetowith the Port configured high The measurand is related toThis the time it takes discharge the M capacitor, and as it can beimpedance obtained if (HZ) input drop buffer. internal output this with bufferthe changes high logical value when its the voltage in The it is monitored. This node can beofdone Port M to configured as high impedance of the input buffer. Assuming that the capacitor has input reaches the low threshold voltage V (HZ) input buffer. The internal output node TL of this buffer changes to high logical value when its inputcharged reachesup thetolow voltage of the buffer. 1a), Assuming the capacitor been the threshold voltage supply in the firstinput step (Figure the timethat interval between has the VCCVTL been charged up to the voltage supply V in the first step (Figure 1a), the time interval between the beginning of the second step in Figure 1bCCand this event is beginning of the second step in Figure 1b and this event is  VCC  V0  ˙ Tx  RxC lnˆ (1)  V ´ V0 Tx “ R x Cln  VTLCC V0  (1) VTL ´ V0 Therefore, provided we know VCC , VTL , V0 (usually 0 volts) and C we can obtain the value Therefore, provided we know VCC , VTL , V0 (usually 0 volts) and C we can obtain the value of the of the resistance Rx from Tx in Equation (1). Tx is readily measured with a high frequency clock resistance R x from Tx in Equation (1). Tx is readily measured with a high frequency clock and a timer and a timer count iswhen registered when the threshold VTL is reached. whose countwhose is registered the threshold VTL is reached.

Figure 1. (a) (a) Direct Direct interface interface configured configured to to charge charge the capacitor; capacitor; (b) (b) direct interface interface configured configured to the capacitor capacitor and and monitor monitorits itsvoltage voltagedrop; drop;and and(c) (c)voltage voltagedrop dropininthe thecapacitor capacitorversus versustime. time. discharge the

2.1. Precision Precision The statistical statistical spread spreadofofthe theresults results this count provided by different measurements forsame the of of this count provided by different measurements for the same resistance the uncertainty or precision. The sources of uncertainty are quantization the quantization error, resistance is theisuncertainty or precision. The sources of uncertainty are the error, the the instability of the reference oscillator to generate the clock signal, and the trigger noise or noise instability of the reference oscillator to generate the clock signal, and the trigger noise or noise added added to the signal input signal and the threshold . If only the quantization is taken account, to the input and the threshold VTL . IfVTL only the quantization errorerror is taken into into account, the precision expressed in number of bits M is M the precision expressed in number of bits

is ˆ ˙ TxT,min TTx,max  x ,max ´ x,min  lb  MM “ lb  TT s s  

(2)(2)

where TTx,max and thethe maximum and and minimum valuesvalues of Tx for and minimum andTx,min maximum minimum of the for the maximum and Tx maximum Tx ,minareare x ,max values of the measurand R x respectively, and Ts is the period of the clock signal. The precision M in minimum values of the measurand Rx respectively, and Ts is the period of the clock signal. The Equation (2) is the maximum obtained under ideal conditions. If the other sources of uncertainty are taken into account, the precision is lower and it is expressed in the effective number of bits ENOB. 3 If we use the terminology given in [10], the discharging time Tx is the measurand Y and the resulting 31764

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digital number multiplied by Ts is the observed input quantity X. The relationship between Y and X is modeled by Y “ X ` Z, where Z takes into account the quantization effects. As the beginning of the interval is synchronized with the start of the counting, the quantization error in time is 0 ď EQ ď Ts . Then Z is described by a rectangular probability density function, and its standard uncertainty is ? upzq “ Ts { 12. Thus, the ENOB can be obtained as [11] ˆ ENOB “ M ´ lb where

umax pyq upzq

˙ (3)

b upyq “

u2 pxq ` u2 pzq

(4)

The term u(x) models the noise in the measurement with the circuit in Figure 1 [11]. 2.2. Accuracy The values of VCC , VTL or C in Equation (1) change with time and temperature. Therefore, a calibration procedure should be implemented to compensate for these sources of error in the measurement of Tx . A straightforward strategy consists in measuring the discharging time Tc1 corresponding to a known resistance value Rc1 , then the value of the unknown resistance R x is obtained as Tx Nx Ts Nx R˚x “ R “ R “ R (5) Tc1 c1 Nc1 Ts c1 Nc1 c1 where Nx and Nc1 are the integer numbers produced during the discharging through R x and Rc1 , respectively. If the measurements of Tc1 and Tx are taken under similar conditions, the multiplicative interference is the same for both and is cancelled in Equation (5). This technique is called single point calibration. However, Equation (5) does not take into account the input resistance of the ports Dc1 and Dx in Figure 2a. If these resistances are considered as constants, the actual transfer characteristic is not that given by Equation (5), depicted by a dashed, red line in Figure 2b, but by a solid blue one. Therefore, there is a difference between the value R˚x obtained from Equation (5) and the actual value R x . Figure 3 illustrates the two-point calibration procedure based on the measurement of two known resistance values Rc1 and Rc2 . The unknown resistance is then calculated as: R˚x “

Nx ´ Nc1 pRc2 ´ Rc1 q ` Rc1 Nc2 ´ Nc1

(6)

where Nc1 and Nc2 are the digital numbers of the discharging times for the calibration resistances Rc1 and Rc2 , respectively. The red dashed line in Figure 3b represents the calibration line in Equation (6), and the solid line represents the actual transfer characteristic if the input resistance of the ports in Figure 3a is taken into account. The error is now minimum for R x “ Rc1 and R x “ Rc2 . This error is now of the order of the difference of the input resistances of Dc1 , Dc2 and Dx in Figure 3a, while it is of the order of the absolute value of the input resistance of ports Dc1 and Dx in Figure 2a, therefore the zero and sensitivity errors are smaller. This paper proposes a method that achieves similar accuracy to that obtained with the two-point calibration technique but with only one calibration resistor.

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This error is now of the order of the difference of the input resistances of Dc1c1, Dc2c2 and Dxx in Figure 3a, while it is of the order of the absolute value of the input resistance of ports Dc1c1 and Dxx in Figure 2a, therefore the zero and sensitivity errors are smaller. This paper proposes a method that achieves similar accuracy to that obtained with the two-point calibration technique but with only one Sensors 2015, 15, 31762–31780 calibration resistor.

(a)

(b)

Figure 2. Single calibration transfer transfer characteristics. characteristics. Figure 2. Single point point calibration: calibration: (a) (a) circuit circuit and and (b) (b) actual actual and and calibration

(a)

(b)

Figure Two-point calibration technique:technique: (a) circuit and(a) (b) actual calibration transfer characteristics. Figure 3.3. Two-point calibration circuitand and (b) actual and calibration transfer characteristics.

3. Capture Modules on FPGAs

−6 3. Capture Modules on FPGAs If a crystal oscillator, with a stability greater than 50–100 × 10−6 [11], is used to generate the clock signal, the precision is mainly limited by the quantization and the trigger The latter has If a crystal oscillator, with a stability greater than 50–100 ˆ 10´6 [11], is noise. used to generate the three clock components: the noise superimposed input signal; and the noise superimposed onlatter the threshold signal, the precision is mainly limited on by the the quantization the trigger noise. The has three on the capacitor at the endinput of thesignal; charging sources ofonnoise make the VTL TL ; and the noise components: the noise superimposed on the thestage. noise These superimposed the threshold

VTL ; andoutput the noise on the capacitor at port the end of Figure the charging stage. These of noise make the internal of the input buffer of M in 2 oscillate when thesources input signal reaches internal output of the 4). input buffer ofthere portisMnot in Figure 2 oscillate when the input signal reaches threshold (see Figure Therefore, only one event that signals the end of the countthe to , but many. In the following, different capture modules are proposed to detect the end of measure T(see threshold Figure 4). Therefore, there is not only one event that signals the end of the count to xx measure In the the following, different in capture are proposed to detect the end of x , but many. the countTtaking into account noisy transition Figuremodules 4. the count taking into account the noisy transition in Figure 4.

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Figure 4. 4. Transitory Transitoryatatthe the output of the input buffer the threshold (routed VILIL is reached output of the input buffer whenwhen the threshold VIL is reached (routed through another to buffer a port to of athe FPGA to FPGA be measured). throughbuffer another port of the to be measured).

3.1. Capture Module 3.1. Capture Module 11 (CM1)—Synchronous (CM1)—Synchronous Circuit Circuit to to Signal Signal the the Input Input Fall Fall Edge Edge with with aa Pulse Pulse Figure 5 shows shows aa simple simple way wayto todetect detectaafalling fallingedge edgeatatthe theinput inputsignal signal and generate a pulse and generate a pulse of of period of the clock signal duration (signal LOAD at Figure When pulse is detected, oneone period of the clock signal duration (signal LOAD at Figure 5b).5b). When thisthis pulse is detected, the the content of timer the timer is stored the register REG_COUNT. However, since the signal input signal is content of the is stored in theinregister REG_COUNT. However, since the input is noisy, noisy, the circuit does not generate only one pulse but many (see Figure 5b), and the count stored in the circuit does not generate only one pulse but many (see Figure 5b), and the count stored REG_COUNT pulse. Note that thethe pulse at the LOAD signal is not REG_COUNT isisthe theone onecorresponding correspondingtotothe thelast last pulse. Note that pulse at the LOAD signal is generated at the edge edge of theof clock input This is This because the twothe signals not generated atfirst the rising first rising the after clockthe after the changes. input changes. is because two are not synchronized and the input signal has to have logical at the rising edge of the clock signals are not synchronized and the input signal hasatolow have a lowvalue logical value at the rising edge of signal. Since trigger noise makes thismakes input this oscillate, is uncertain what clock cycleclock the event the clock signal. Since trigger noise inputitoscillate, it is at uncertain at what cyclewill the be captured. event will be captured.

Figure 5.5.Capture CaptureModule Module 1—Synchronous circuit to signal the fall input edge with(a) a circuit pulse: 1—Synchronous circuit to signal the input edgefall with a pulse: and (b) example (a) circuit and (b)chronogram. example chronogram.

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3.2. Capture Module 2 (CM2)—Synchronous Circuit to Signal the Input Fall Edge with a Single Pulse The circuit in Figure 6a slightly modifies thattoin Figure by adding NotePulse that once 3.2. Capture Module 2 (CM2)—Synchronous Circuit Signal the5a Input Fall Edgefeedback. with a Single Q2 has changed to logical low value the input of the second flip-flop is set to low value so Q2 will be The circuit in Figure 6a slightly modifies that in Figure 5a by adding feedback. Note that once a logical ‘0’ until the inputs of the flip-flops are set to high value by a preset signal, and the circuit is Q2 has changed to logical low value the input of the second flip-flop is set to low value so Q2 will be ready to detect another falling edge at the input. a logical “0” until the inputs of the flip-flops are set to high value by a preset signal, and the circuit is The digital feedback introduces memory and the circuit is able to store a bit that indicates that a ready to detect another falling edge at the input. falling edge at the input has already been detected. This memory actually replaces the analog The digital feedback introduces memory and the circuit is able to store a bit that indicates that memory present in proposals with analog circuits with hysteresis, such as Trigger Schmitt buffers or a falling edge at the input has already been detected. This memory actually replaces the analog the proposal in [7]. memory present in proposals with analog circuits with hysteresis, such as Trigger Schmitt buffers or Figure 6b shows a chronogram to illustrate how this circuits works. Again, the uncertainty due the proposal in [7]. to the lack of synchronization between the input and clock signals is present, and the pulse at the Figure 6b shows a chronogram to illustrate how this circuits works. Again, the uncertainty due to LOAD signal is generated at the second rising edge of the clock after the input signal begins the lack of synchronization between the input and clock signals is present, and the pulse at the LOAD to oscillate. signal is generated at the second rising edge of the clock after the input signal begins to oscillate.

Figure 6. Capture Capture Module Module 2—Synchronous 2—Synchronous circuit circuit to to signal signal the the input input fall fall edge edge with with aa single single pulse: pulse: Figure (a) circuit and (b) example chronogram.

3.3. 3.3. Capture Capture Module Module 33 (CM3)—Circuit (CM3)—Circuit Based on Front End Interface with Latch Figure 7a shows showsanother anotherway way memory present the hysteresis of Schmitt Figure 7a to to addadd memory like like that that present in theinhysteresis of Schmitt Trigger Trigger buffers to the basic 5a. The circuit theofflexibility FPGA to buffers to the basic circuit in circuit Figure in 5a.Figure The circuit exploits theexploits flexibility the FPGAoftothe design with design with different storage elements and uses a level triggered latch to store one bit. Specifically, different storage elements and uses a level triggered latch to store one bit. Specifically, when the input when input to signal changes to logical low the value because theinvoltage drop inreaches the capacitor reaches signalthe changes logical low value because voltage drop the capacitor VTL , the latch , the latch stores the logical ‘0’. Note that the Q0 keeps the value whatever the following value of V stores the logical “0”. Note that the Q0 keeps the value whatever the following value of the input is, TL so the circuit provides a single input at LOAD_RE the firstafter transition from high to from low value of the input is, so the circuit provides a single input atafter LOAD_RE the first transition high to the input. low value of the input.

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Figure front end end interface with with latch: (a)(a)circuit circuit and Figure7.7. 7. Capture Capture Module Module 3—Circuit 3—Circuit based Figure Capture Module 3—Circuit based on on front front end interface interface with latch: latch: (a) circuit and and (b)(b) example chronogram. example chronogram. (b) example chronogram.

3.4. CaptureModule Module444(CM4)—Circuit (CM4)—CircuitBased Basedon on Front Front End Interface 3.4. Capture with Latch LatchRobust Robustagainst againstSpikes Spikes 3.4. Capture Module (CM4)—Circuit Based on Front End End Interface Interface with with Latch Robust against Spikes A drawbackofof ofthe thecircuit circuitin inFigure Figure 7a 7a is is that that it is sensitive AA drawback spurioustransitions transitionsto lowvalue value drawback the circuit in Figure 7a is that it it is is sensitive sensitive to to spurious spurious transitions totolow low value or glitches at the input due to isolated noise spikes. The circuit in Figure 8a is more robust ororglitches The circuit circuit in in Figure Figure8a 8aisismore morerobust robustagainst against glitchesatatthe theinput inputdue duetotoisolated isolated noise noise spikes. spikes. The against such events.ItIt Ituses usesthe theclock clocksignal signal to to preset preset the the input semi-cycle. such events. latchevery everyclock clockcycle, cycle,at thehigh high semi-cycle. such events. uses the clock signal to preset input latch latch every clock cycle, atatthe the high semi-cycle. Therefore, if there is a short glitch at INPUT, Q0 will not keep the low value and the circuit bebe Therefore, the low low value valueand andthe thecircuit circuitwill will Therefore,ififthere thereisisaashort shortglitch glitchat atINPUT, INPUT, Q0 Q0 will will not keep the will be ready to generate another pulse at the output to register the content of the timer. However, since Q1 readytotogenerate generateanother anotherpulse pulseat atthe the output output to register the ready the content contentof ofthe thetimer. timer.However, However,since sinceQ1 Q1 does not change until the rising edge of the clock signal, a low value of the input in the preceding doesnot not change until the rising edge clock signal, a low value of the input in the preceding does change until the rising edge of of thethe clock signal, a low value of the input in the preceding low low semi-cycle will set a ‘0’ again at Q0 and Q1 will not change, so there will be no pulse at the low semi-cycle will set again a ‘0’ again Q0Q1 andwill Q1not willchange, not change, so there will no pulse the semi-cycle will set a “0” at Q0atand so there will be nobe pulse at theat circuit circuit output. In other words, if INPUT is at high value at least for a high clock semi-cycle then the circuit In output. other if words, if INPUT is at highat value least for aclock high semi-cycle clock semi-cycle thenglitch the output. otherIn words, INPUT is at high value leastatfor a high then the glitch is considered as noise caused by an isolated spike and a new LOAD_RE event could be glitch is considered as noise caused by an isolated spike and a new LOAD_RE event could be is considered as noise caused by an isolated spike and a new LOAD_RE event could be generated. generated. Therefore, the capture module in Figure 8a provides a load pulse for the first isolate generated. the capture module in Figurea load 8a provides a the loadfirst pulse for transition the first isolate Therefore, theTherefore, capture module in Figure 8a provides pulse for isolate to low transition to low at the input caused by the trigger noise, but discards it with a new pulse when the transition to low at the input caused by the trigger noise, but discards it with a new pulse when the at the input caused by the trigger noise, but discards it with a new pulse when the oscillation starts. oscillation starts. As a result, the circuit reduces the uncertainty in determining Tx . starts. As areduces result, the reduces uncertainty Asoscillation a result, the circuit thecircuit uncertainty in the determining Txin . determining Tx .

Figure 8. Capture Module 4—Circuit based on front end interface with latch robust against spikes: Figure 8. Capture Module 4—Circuit based on front end interface with latch robust against spikes: (a) circuit and (b)Module chronogram. Figure 8. Capture 4—Circuit based on front end interface with latch robust against spikes: (a) circuit and (b) chronogram. (a) circuit and (b) chronogram.

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3.5. Capture Module 5 (CM5)—Circuit Triggered with the Rising and Falling Edge of the Clock Signal to Average two Module Counts 5 (CM5)—Circuit Triggered with the Rising and Falling Edge of the Clock Signal to 3.5. Capture Average Two Counts Another interesting feature of the FPGAs is the possibility to use flip-flops triggered by rising or falling edges. Figure 9a feature shows aofcircuit similar to that in Figure 8a but with the flip-flop Another interesting the FPGAs is the possibility to use flip-flops triggered by whose rising outputs Q1 are triggered by a falling edge, and the latch preset at the low semi-cycle of thewhose clock or falling edges. Figure 9a shows a circuit similar to that in Figure 8a but with the flip-flop signal. Figure shows by a possible to at both This is of only example, outputs Q1 are 9b triggered a fallingchronogram edge, and theassociated latch preset the circuits. low semi-cycle the an clock signal. the output pulses of both circuits can be separated in time. The reason is that the input signal is Figure 9b shows a possible chronogram associated to both circuits. This is only an example, the output complex not synchronized with the clock.The However, observe experimentally that if we pulses of and bothiscircuits can be separated in time. reason we is that the input signal is complex anduse is both circuits in parallel and the readings of the timer are stored in two registers, their average not synchronized with the clock. However, we observe experimentally that if we use both circuits in provides a more precise of value of Tx are . Anstored explanation for this istheir the average ability to store the countprecise in the parallel and the readings the timer in two registers, provides a more value Tx . An explanation for this the ability to store count the timer of with resolution timer of with a higher resolution in is time, actually with the twice theinfrequency thea higher clock. Therefore, in time, actually the clock. Therefore, although the time base does not although the timewith basetwice does the not frequency change, theofeffect is similar to reduce the quantization error. This is change, effect is reduce the quantization This in Figure 9b,average where two the case the in Figure 9b,similar wheretotwo consecutive counts (nerror. + 1 and n +is2)the arecase stored, so their will consecutive counts (n + 1 and n + 2) are stored, sofor their will provide a higher resolution. provide a higher resolution. Another explanation thisaverage improvement in the precision is the low Another explanation for thisby improvement the output precision is theinlow pass filtering implemented by pass filtering implemented the average.inThe pulses LOAD, or the counts registered, the average. output pulses in LOAD, or the counts registered, could be not consecutive. could be not The consecutive.

Figure 9. 9. Capture Capture Module Module 5—circuit 5—circuit triggered triggered with with the the rising rising and and falling falling edge edge of of the the clock clock signal signal to to Figure average two two counts: counts: (a) circuit circuit and and (b) (b) example example chronogram. chronogram. average

3.6. Capture Capture Module Module 66 (CM6)—Circuit (CM6)—Circuit Triggered Triggeredwith withthe theRising Risingand andFalling FallingEdge Edgeofofthe theClock ClockSignal Signaltoto 3.6. Average Four four Counts Average The above above mentioned mentioned filtering function performed by the average average can be be exploited exploited to to improve improve The the precision precision of of measurement measurement while while preserving preserving the the bandwidth bandwidth thanks thanks to to the the parallel parallel operation operation in in the the the FPGA. Note Notethat thatthe the voltage trigger noise is translated a trigger noise time, therefore an FPGA. voltage trigger noise is translated into ainto trigger noise in time,intherefore an average average in time of this noise will filter part of the noise. This can be done if circuits which detect the 9 31770

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in time of this noise will filter part of the noise. This can be done if circuits which detect the end of the noisy change the input ofinput the capture modules are proposed and developed. Then the counts end of the noisy at change at the of the capture modules are proposed and developed. Then the registered by the circuits that signal the start of the noisy transition at the input and those registered counts registered by the circuits that signal the start of the noisy transition at the input and those byregistered the circuits detect the of this averaged. by that the circuits thatend detect the noisy end oftransition this noisyare transition are averaged. Figure 10a shows a circuit able to detect the end of the noisy at the input flip-flops Figure 10a shows a circuit able to detect the end of the transition noisy transition at thewith input with synchronized with the rising of theedge clock The circuit works as works follows. theSince clock flip-flops synchronized with edge the rising of signal. the clock signal. The circuit as Since follows. signal makes a PRESET every clock cycle, the signal Q0 toggles every clock cycle as long as the INPUT the clock signal makes a PRESET every clock cycle, the signal Q0 toggles every clock cycle as long as signal takes asignal high takes logicala value at least onceatinleast the low However, as soon as as thesoon INPUT the INPUT high logical value oncesemi-cycle. in the low semi-cycle. However, as signal stays stable atstays low logical also stabilizes highstabilizes logical value. Then a pulse is generated the INPUT signal stable value, at lowQ0 logical value, Q0atalso at high logical value. Then a atpulse the circuit outputat LOAD_RE. make the circuitTo robust isolated noise spikes, a feedback is generated the circuit To output LOAD_RE. makeagainst the circuit robust against isolated noise with a logical gate OR is added at the whose is Q2. This causes the is logical high spikes, a feedback with a logical gatelast ORflip-flop is added at theoutput last flip-flop whose output Q2. This causes logical at high to be the stored at Q2 whatever the value of Q1 is, as as one thereatisINPUT not a value to the be stored Q2value whatever value of Q1 is, as long as there is not a long logical one at INPUTofinthe theclock low semi-cycle to Note the clock edge.10c, Note inlogical the low semi-cycle signal prioroftothe theclock clocksignal risingprior edge. that,rising in Figure the that, in Figure 10c,(red the last isolated glitch (red dottedascircle) considered noiseinto andaccount it is not by taken last isolated glitch dotted circle) is considered noiseisand it is notas taken this into account by this capture module. capture module.

Figure and falling fallingedge edgeof ofthe theclock clocksignal signaltoto Figure10. 10.Capture CaptureModule Module6—circuit 6—circuittriggered triggered with with the the rising rising and average four counts: (a)(a) circuit triggered with thethe rising edge; (b) (b) circuit triggered withwith the falling edge; average four counts: circuit triggered with rising edge; circuit triggered the falling and (c) chronogram. edge; and (c) chronogram.

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Similarly to the proposal in Section 3.5, another circuit synchronized with the clock falling edge can be used in parallel with that in Figure 10a to improve the precision in the detection of the end of the noisy transition. This circuit is shown in Figure 10b. In this way the average of four registered counts (from the circuits in Figures 9 and 10) is calculated and the result is more precise than the measurement of Tx obtained with the other capture modules, as can be seen in Section 6. 4. Proposed Calibration Techniques In addition to the capture modules to improve resolution described above, this paper also proposes calibration techniques with higher accuracy. As mentioned in Section 2.1, error estimation of resistance R x is mainly due to the input resistance of the ports of the FPGA that drive R x , as well as the calibration Rc1 . If the input internal resistance of the ports is taken into account, the result of Equation (5) is not R x but [12] Nx Rc1 Rc1 Rn,x R˚x “ R “ Rx ` (7) Nc1 c1 Rc1 ` Rn,c1 Rc1 ` Rn,c1 where Rn,x and Rn,c1 are the internal resistances of the ports Dc1 and Dx in Figure 2, respectively, the following relationship is readily obtained from Equations (5) and (7) between the actual value of the measurand R x and the ratio Nx {Nc1 ˆ Rx “

Nx Rc1 Rn,x Rc1 ´ Nc1 Rc1 ` Rn,c1

˙

Rc1 Rn,c1 Nx “ pR ` Rn,c1 q ´ Rn,x Rc1 Nc1 c1

(8)

Therefore, the measurement of the input resistances (Rn,c1 and Rn,x ) obtains a more accurate value of R x from Equation (8). This measurement can be done with an ad-hoc circuit, or the values of Rn,c1 and Rn,x can be estimated with the same direct interface that is depicted in Figure 2a. Note that Equation (8) corresponds to a line whose slope and zero are determined by the value of the internal and calibration resistances. Therefore, if the slope and zero are found, Equation (8) provides the “actual” value of R x . These are readily obtained if we measure two known resistances, because in this way two equations are obtained where the slope and zero are the unknown parameters. This procedure will be referred to as “calibration with two-point linear characterization” (CLchar2). This technique can be generalized to contemplate a more precise linear approximation or a possible non-linear dependence of R x on the ratio Nx {Nc1 due to a more accurate model of the input impedance of the ports. This has also been done in this paper, where eight resistances of known value have been measured with the circuit in Figure 2a. Figure 11 depicts the resistance R x versus the ratio Nx {Nc1 for the measured resistances and also the linear approximation obtained by the least mean square regression as Nx R x “ 3704.79 ´ 14.07 (9) Nc1 which provides the “actual” value of Rx for a given ratio Nx {Nc1 . This is referred to as “technique calibration with 8-point linear characterization” (CLchar8). Finally, if a two degree polynomial fit is carried out from the same eight points, the expression for Rx is ˆ R x “ ´0.31

Nx Nc1

˙2 ` 3705.45

Nx ´ 14.28 Nc1

(10)

This technique is referred to as “calibration with 8-point square characterization” (CSQchar8). All these approximations are used to improve accuracy in the measurement of R x and the results are shown in Section 6.

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This technique is referred to as “calibration with 8-point square characterization” (CSQchar8). All these approximations are used to improve accuracy in the measurement of Rx and the results

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are shown in Section 6.

Figure with linear linear interpolation interpolation used used to to obtain obtain Equation Equation (9). (9). Figure 11. 11. Experimental Experimental transfer transfer characteristic characteristic with

5. Materials 5. Materialsand andMethods Methods The circuit circuit to to test test the the proposals proposals of of this this paper paper is is based based on on an an FPGA FPGA Spartan3AN Spartan3AN from from Xilinx Xilinx The (XC3S50AN-4TQG144C) [13]. The clock signal is generated with a crystal oscillator at 50 MHz. The (XC3S50AN-4TQG144C) [13]. The clock signal is generated with a crystal oscillator at 50 MHz. circuit is implemented in a in four layer FR4FR4 printed circuit board. TheThe design rules recommended by The circuit is implemented a four layer printed circuit board. design rules recommended the vendor of the FPGA for the PCB are carefully followed to minimize the noise superimposed on by the vendor of the FPGA for the PCB are carefully followed to minimize the noise superimposed on the supply supply voltage voltagebecause becauseititcouples coupleswith withthe the threshold voltage in Equation (1) C C Equation (1) and the threshold voltage VTLVTL andand to VtoCCVin and hence contributes the trigger noise and degrades precision. Theworks FPGAwith works two hence contributes to theto trigger noise and degrades precision. The FPGA twowith different differentvoltages, supply one voltages, one forand thethe core andfor thethe other the I/O buffers. Note this fact supply for the core other I/O for buffers. Note that this factthat reduces the reduces the noise contribution of the activity in the core of the FPGA on the voltage supply of the noise contribution of the activity in the core of the FPGA on the voltage supply of the output buffers, and in Equation The for voltage output buffers, so it added reduces the noiseVTL added to VCC(1). so it reduces the noise to V in Equation TheVvoltage regulators(1). chosen both CC and TL supplies are the TPS79633 and the TPS79912 from Texas Instruments that provide 3.3 V and 1.2 V, regulators chosen for both supplies are the TPS79633 and the TPS79912 from Texas Instruments that respectively. dropout voltages andlow verydropout low output voltage set of RMS ). A provide 3.3 VBoth andhave 1.2 V,low respectively. Both have voltages andnoise very(40 lowµV output voltage decoupling capacitors of different values are connected between voltage supply and ground pins (four noise (40 µVRMS). A set of decoupling capacitors of different values are connected between voltage supply pins for the I/O buffers and one for the core). The capacitors are physically close to the supply supply and ground pins (four supply pins for the I/O buffers and one for the core). The capacitors pins. The inner layers of the PCBpins. are dedicated to the of ground plane and the 3.3 voltage are physically close to the supply The inner layers the PCB are dedicated to V the groundsupply plane plane. Note that the supply plane is connected to the voltage supply of the I/O buffers, since the noise and the 3.3 V voltage supply plane. Note that the supply plane is connected to the voltage supply of superimposed thisthe voltage the precision. the I/O buffers,on since noisedegrades superimposed on this voltage degrades the precision. Two target target devices devices are are used used to to show show the the performance performance of of the the proposed proposed modules: modules: a custom piezoresistive tactile sensor; and a PT-1000 temperature sensor. Piezoresistive tactile sensors are PT-1000 temperature sensor. basically arrays of force sensing resistors which are considered suitable to illustrate the proposals of this paper. The The PT-1000 PT-1000 sensor sensor also alsoallows allowsdifferent differentoutput outputranges rangestotobe betested testedasaswell wellasasallowing allowinga acomparison comparisonofofperformance performancewith withother otherreported reportedimplementations. implementations. For the thethe timers to to measure Tx have 14 bits time the results resultsin inSection Section66related relatedtotoprecision, precision, timers measure 14 and bits their and their Tx have base is 20 ns. Since trigger noise mainly affects the measurement of low slew rate signals, the largest time base is 20 ns. Since trigger noise mainly affects the measurement of low slew rate signals, the resistance in the range interest chosenistochosen assess the performance of the proposal. resistance largest resistance in theofrange of isinterest to assess the performance of the The proposal. The is measured 500 times with the circuit in Figure 1 and the standard deviation σpxq is calculated resistance is measured 500 times with the circuit in Figure 1 and the standard deviation  ( x) to is estimate upxq. A capacitor of 47 nF was used since a larger capacitance does not improve precision calculated to estimate u( x) . A capacitor of 47 nF was used since a larger capacitance does not significantly [11] and reduces bandwidth and increases power consumption. improve precision significantly [11] and reduces increases power consumption. Regarding accuracy, the circuit in Figure 12bandwidth is used to and implement and compare the results of Regarding accuracy, the circuit in Figure 12 is used to implement and compare the technique results of three calibration techniques: one-point calibration; two-point calibration; and the proposed three calibration calibration; calibration; and the proposed described in Sectiontechniques: 4. The valuesone-point of the resistances Rc1 , Rtwo-point c2 and Rc3 in Figure 12 are taken with values technique described in Section 4. The values of the resistances , Rc 2 set andofRknown in Figure 12 are R c1 c3 in 50%, 15%, and 85% of the range of interest respectively [14]. Another resistances taken values in 50%, 15%, and 85%ofofthe theports range respectively [14]. Another set of is usedwith to characterize input impedance of of theinterest FPGA as well as to assess the proposed known resistances is used to characterize impedance ports of the FPGA as well as to technique and compare it with the others. input The “actual” valueofofthe these resistances is measured with themultimeter proposed technique and compare with theof others. The value of these Finally, resistances aassess digital (Agilent 34401) with anitaccuracy 0.011% in ‘actual’ the range of interest. the capture module implemented is that described in the Section 3.6. 12

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is measured with a digital multimeter (Agilent 34401) with an accuracy of 0.011% in the range of module implemented is that described in the Section 3.6.

Sensors 2015, 15, 31762–31780 interest. Finally, the capture

Figure Circuit to Figure 12. 12. Circuit to implement implement and and compare compare different different calibration calibration techniques. techniques.

6. Resultsand andDiscussion Discussion 6. Results To To test test and and compare compare the the performance performance of of the the capture capture modules modules proposed proposed in in Section Section 3, 3, the the range range of of resistance of the piezoresistive tactile sensor between 200 Ω and 7350 Ω was chosen. Figure 13 shows resistance of the piezoresistive tactile sensor between 200 Ω and 7350 Ω was chosen. Figure 13 shows the of 500 500 digital digitalnumbers numbersfor for R R x == 7350 and CC ==47 the histograms histograms of 7350 Ω Ω and 47nF, nF,and andfor forthe the capture capture modules modules x described in Section 3. Moreover, Table 1 summarizes the data related to the precision obtained with described in Section 3. Moreover, Table 1 summarizes the data related to the precision obtained with the capture modules. It shows the results for the standard deviation σpxq, the uncertainty upyq given the capture modules. It shows the results for the standard deviation  ( x) , the uncertainty u ( y ) by Equation (4) (taking the quantization error into account), the effective number of bits (ENOB) and given by Equation (4) (taking the quantization error into account), the effective number of bits the resolution for the example resistance. A slight improvement can be observed with the module (ENOB) and the resolution for the example resistance. A slight improvement can be observed with CM2 in Section 3.2 regarding the simplest CM1 in Section 3.1. The module CM3 in Section 3.3 based the module CM2 in Section 3.2 regarding the simplest CM1 in Section 3.1. The module CM3 in on a front end with a latch does not perform better than the others, actually its results are worse than Section 3.3 based on a front end with a latch does not perform better than the others, actually its those achieved with CM2. However, the module CM4 that filters noisy spikes obtains better results. results are worse than those achieved with CM2. However, the module CM4 that filters noisy spikes Finally, the capture modules that exploit both the rising and the falling edges of the clock signal to obtains better results. Finally, the capture modules that exploit both the rising and the falling edges synchronize the flip-flops and carry out the average of two (CM5) of four (CM6) counts provide the of the clock signal to synchronize the flip-flops and carry out the average of two (CM5) of four (CM6) best results, with resolution as low as 1.70 Ω. counts provide the best results, with resolution as low as 1.70 Ω. Table 1. Precision data of the capture modules (R x = 7350 Ω). Table 1. Precision data of the capture modules ( Rx = 7350 Ω). σ(X) (counts)

σ(X) (µs)

u(y) (µs)

ENOB (bits)

Resolution (Ω)

σ(X) (counts) σ(X) (µs) u(y) (µs) ENOB (bits) Resolution (Ω) CM 1 2.14 0.043 0.043 10.98 3.54 CM 1 CM 2 2.14 1.83 0.043 0.043 10.98 3.54 0.037 0.037 11.20 3.04 CM 2 CM 3 1.83 2.13 0.037 0.037 3.04 0.043 0.043 10.9811.20 3.53 0.038 0.038 11.1410.98 3.16 CM 3 CM 4 2.13 1.90 0.043 0.043 3.53 0.026 0.027 11.6711.14 2.19 CM 4 CM 5 1.90 1.31 0.038 0.038 3.16 CM 6 1.00 0.020 0.021 12.04 1.70 CM 5 1.31 0.026 0.027 11.67 2.19 CM 6 1.00 0.020 0.021 12.04 1.70 Regarding bandwidth, especially relevant if data from many sensors are acquired, it is limited by the time constant R x C in especially Equation (1) and there is afrom clearmany tradeoff with are precision, because direct Regarding bandwidth, relevant if data sensors acquired, it is limited interfaces exploit the quantization of time(1) soand the longer time tradeoff constantwith the larger the precision only by the time constant there isthe a clear precision, becauseifdirect R x C in Equation the quantization error is taken into account. However, for increasing time constants, the influence interfaces exploit the quantization of time so the longer the time constant the larger the precisionof if trigger noise is larger than that of the quantization error [11] and the standard deviation grows linearly only the quantization error is taken into account. However, for increasing time constants, the with the time constant. can be seen in of Figure 14, where the standard deviation is represented influence of trigger noiseThis is larger than that the quantization error [11] and the standard deviation versus the time constant for C = 47 nF and a set of resistance values (200 Ω, 762 Ω, 1300 Ω, 1890 Ω, grows linearly with the time constant. This can be seen in Figure 14, where the standard deviation is 2400 Ω, 3070 Ω, 3680 Ω, 4100 Ω, 4840 Ω, 5300 Ω, 5820 Ω, 6400 Ω, 7000 Ω and 7350 Ω). Nevertheless, represented versus the time constant for C = 47nF and a set of resistance values (200 Ω, 762 Ω, 1300 Ω, if bothΩ,sources of 3070 errorΩ, are3680 added Equation the Ω, relative behaves as shown in 1890 2400 Ω, Ω, using 4100 Ω, 4840 Ω,(4), 5300 5820 uncertainty Ω, 6400 Ω, 7000 Ω and 7350 Ω). Figure 15. It can be observed that the relative uncertainty grows for small time constants. As mentioned 13the main source or error, so if the range of time above, the reason is that the quantization error is 31774

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Nevertheless, if both sources of error are added using Equation (4), the relative uncertainty behaves Nevertheless, if both sources of error are added using Equation (4), the relative uncertainty behaves as shown in Figure 15. It can be observed that the relative uncertainty grows for small time Sensors 2015, 15, as shown in 31762–31780 Figure 15. It can be observed that the relative uncertainty grows for small time constants. As mentioned above, the reason is that the quantization error is the main source or error, constants. As mentioned above, the reason is that the quantization error is the main source or error, so if the range of time is short the precision is limited by the period of the clock signal. For increasing soshort if the the range of time is is limited short thebyprecision is limited by thesignal. period For of the clock signal. Forof increasing is precision the period of the clock values values of the time constant, the relative uncertainty decreases, but itincreasing changes very little the for time time values of the time constant, the relative uncertainty decreases, but it changes very little for µs time constant, the relative uncertainty decreases, but it changes very little for time constants above 100 in constants above 100 µs in Figure 15. Therefore, this value can be a good compromise between constants above 100 µs in Figure 15. Therefore, this value can be a good compromise between Figure 15.and Therefore, this value good compromise precision and bandwidth. Note precision bandwidth. Note can thatbe thea capacitor chosen to set the required time constant C can bebetween precision and bandwidth. that the be chosenfor to set the required time constant C can that capacitor C can range. beNote chosen set capacitor the required constant a given resistance range. This for athe given resistance Thistocapacitor has totime be changed if the resistance range varies to for a given resistance range.if the Thisresistance capacitorrange has to be changed if the resistance range varies to capacitor has to be changed varies to maintain the same relative uncertainty. maintain the same relative uncertainty. This can require an increase in the number of bits of the maintain the same relative in uncertainty. This canofrequire an increase in the the number of bits of but the This canthat require an increase the number ofdoes bits counter that measure time, counter measure the discharge time, but notthe affect the performance of thedischarge capture modules. counter that measure the discharge time, but does not affect the performance of the capture modules. does not affect the performance of the capture modules.

Figure 13. Histograms of 500 digital numbers for Rx = 7350 Ω and C = 47 nF and for the capture Figure 13. Histograms Histograms of of 500 500 digital digital numbers numbers for for R 7350 Ω Ω and and C C== 47 47 nF nF and and for the capture Rxx == 7350 modules: CM1 Section 3.1, 3.1, CM2 CM2 in in Section Section 3.2, 3.2, CM3 CM3 in in Section Section 3.3, 3.3, CM4 CM4 in in Section Section 3.4, 3.4, CM5 CM5 in in modules: CM1 in in Section modules: CM1 in Section 3.1, CM2 in Section 3.2, CM3 in Section 3.3, CM4 in Section 3.4, CM5 in Section 3.5 and CM6 in Section 3.6. Section 3.5 and CM6 in Section 3.6. Section 3.5 and CM6 in Section 3.6.

Figure Experimentalstandard standarddeviation deviation σpxq ( x)versus Figure 14. 14. Experimental versusthe thetime timeconstant constantof ofthe the capture capture module module  ( x ) Figure 14. Experimental standard deviation versus the time constant of the capture module in Section 3.6. in Section 3.6. in Section 3.6.

14 14 31775

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Figure Relative standard standard uncertainty uncertainty versus versus the the time time constant constant for for the the capture capture module module in in Section Section 3.6. 3.6. Figure 15. 15. Relative

Relatingtotopower power consumption, its main component that involved in theofcharge of the Relating consumption, its main component is thatisinvolved in the charge the capacitor 2 1 1 2 f ,by capacitor given f , frequency where fof is frequency of thecycle. charging-discharging cycle. given by CV where f CC is the thethe charging-discharging Obviously, the larger the 2 CV 2 CC Obviously, the the larger larger the the power bandwidth the largerand the the power consumption, the lower the precision bandwidth consumption, lower the precisionand because the time constant because the time constant must be shorter. must be shorter. With respect respect to to the the cost, cost, Table Table 22summarizes summarizes the the hardware hardware resources resources consumed consumed by by the the capture capture With modules. CM5 and CM6 obviously need more resources. However, this is not a serious limitation modules. resources. not a serious limitation because there there are are aa wide wide range range of of FPGA FPGA devices devices and and more more powerful powerful ones ones can can be be chosen chosen if if the the target target because application requires requires many many computational computationalresources. resources. application Table Table 2. 2. Hardware Hardware resources resources consumed consumedby bythe thecapture capturemodules. modules.

CM1 CM2 CM2 CM3 CM3 CM4 CM4 CM5 CM5 CM6 CM6 CM1 Slices 3 3 3 3 24 45 Slices 3 3 3 3 24 45 44 inputs Look Up Tables 19 19 19 19 39 99 inputs Look Up Tables 19 19 19 19 39 99 FlipFlops Flops 56 92 Flip 3535 3535 3535 3535 56 92 Latches 0 0 00 11 11 22 44 Latches With regard regard to to accuracy, accuracy, the the circuit circuit in in Figure Figure 12 12 was was used used to to perform perform the the different different calibration calibration With techniques as explained in Section 5. Table 3, Figures 16 and 17 show the results. The maximum techniques as explained in Section 5. Table 3, Figures 16 and 17 show the results. The maximum error is that obtained for the set of resistance values in the first column of Table 3. error e max obtained for the set of resistance values in the first column of Table 3. emax is that The best bestresults results obtained the proposed technique as with wellthe astwo-point with the calibration. two-point The areare obtained withwith the proposed technique as well as calibration. The only former only one calibration so the cost in hardware is lower and its The former uses oneuses calibration resistor, so theresistor, cost in hardware is lower and its implementation implementation is more than thatcalibration. of the two-point calibration. Moreover, since only one is more compact than thatcompact of the two-point Moreover, since only one calibration resistor calibration resistor has tocycle be measured cycle of data bandwidth is also improved. has to be measured per of data per acquisition, the acquisition, bandwidth the is also improved. The price to The is price payfor is the need forcharacterization a previous characterization the FPGA to infer value of pay the to need a previous of the FPGAofports to inferports the value ofthe their input resistance, it can be doneitwith same direct interface replacing R x in 12 with their inputalthough resistance, although can the be done with the same by direct interface byFigure replacing in Rx the characterization resistances and measuring the ratio N {N . If a linear dependence is supposed, the c1 Figure 12 with the characterization resistances andx measuring the ratio N x / N c1 . If a linear slope and zero can be derived with two resistances at 15% and 85% of the range of interest (CLchar2), dependence is supposed, the slope and zero can be derived with two resistances at 15% and 85% of and also with eight different resistances in the range of interest (CLchar8). If a quadratic dependence the range of interest (CLchar2), and also with eight different resistances in the range of interest is presumed (CSQchar8), the Equation (10) in Section 4 provides R x for a given Nx {Nc1 . The results in (CLchar8). If a quadratic dependence is presumed (CSQchar8), the Equation (10) in Section 4 Table 3, Figures 16 and 17 do not show an improvement for the use of the techniques CLchar8 and provides Rx for a given N x / N c1 . The results in Table 3, Figures 16 and 17 do not show an CSQchar8 with respect to CLchar2. Therefore, since the cost of implementing CLchar2 is lower because improvement for the use of the istechniques CLchar8 and CSQchar8 with respect to CLchar2. the number of calibration resistors lower, it is the best choice for the device of this paper. Therefore, since the cost of implementing CLchar2 is lower because the number of calibration resistors is lower, it is the best choice for the device of this paper. 31776 15

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Table 3. Accuracy data for the tactile sensor and different calibration techniques. Table 3. Accuracy data for the tactile sensor and different calibration techniques.

Maximum Absolute Error (Ω) Maximum Absolute Error (Ω) 1 Point Calib. 2 Point Calib. CLChar2 CLChar8 CSQChar8 1 Point Calib. 2 Point Calib. CLChar2 CLChar8 CSQChar8 0.22 0.37 199.96 13.44 0.60 0.20 0.22 0.37 199.96 13.44 0.60 0.20 Table 3. Accuracy data10.80 for the tactile sensor calibration 0.36 techniques. 0.32 0.39 763.34 0.47and different0.39 0.36 763.34 10.80 0.47 0.32 0.56 0.55 1297.32 8.50 0.76 0.54 0.56 0.55 1297.32 8.50 0.76 0.54 Maximum Absolute Error (Ω) Measurand (Ω) 0.67 0.81 1887.55 6.00 0.84 0.86 0.67 0.81 1887.55 6.00 0.84 0.86 1 Point Calib. 2 Point Calib. CSQChar8 CLChar2 CLChar8 1.34 1.20 2401.95 2.96 0.79 1.11 1.34 1.20 2401.95 2.96 0.79 1.11 199.96 13.44 0.60 0.20 0.22 0.37 1.05 1.19 3070.25 1.08 1.46 1.32 1.05 1.19 3070.25 1.08 1.46 1.32 763.34 10.80 0.47 0.32 0.39 0.36 1.34 1.21 3684.25 4.40 1.66 1.07 1297.32 8.50 0.76 0.54 0.56 0.55 1.34 1.21 3684.25 4.40 1.66 1.07 1887.55 6.00 0.84 0.86 0.67 0.81 1.20 1.24 4083.85 6.13 1.96 1.38 1.20 1.24 4083.85 6.13 1.96 1.38 2401.95 2.96 0.79 1.11 1.34 1.20 1.55 1.41 4836.05 9.99 2.10 1.31 1.55 1.41 3070.25 1.08 1.46 1.32 1.05 1.19 4836.05 9.99 2.10 1.31 2.03 2.16 5269.05 11.10 3.20 2.26 3684.25 4.40 1.66 1.07 1.34 1.21 2.03 2.16 5269.05 11.10 3.20 2.26 4083.85 6.13 1.96 1.38 1.20 1.24 1.73 1.86 5813.45 14.68 2.54 1.91 1.73 1.86 5813.45 14.68 2.54 1.91 4836.05 9.99 2.10 1.31 1.55 1.41 2.06 2.19 6373.15 17.25 3.21 2.19 5269.05 11.10 3.20 2.26 2.03 2.16 2.06 2.19 6373.15 17.25 3.21 2.19 2.44 2.31 5813.45 14.68 2.54 1.91 1.73 1.86 6983.15 20.91 3.00 2.39 2.44 2.31 6983.15 20.91 3.00 2.39 6373.15 17.25 3.21 2.19 2.06 2.19 2.29 2.42 7349.15 21.90 3.54 2.28 2.29 2.42 7349.15 21.90 3.54 2.28 6983.15 20.91 3.00 2.39 2.44 2.31 18.87 19.28 Total Error 149.13 26.12 19.13 7349.15 21.90 3.54 2.28 2.29 2.42 18.87 19.28 Total Error 149.13 26.12 19.13 Total Error 149.13 26.12 19.13 18.87 19.28 Max. Relative Error (%) 6.72 0.30 0.11 0.18 0.10 Max. Relative Error (%) 6.72 0.30 0.11 0.18 0.10

Measurand (Ω) Sensors 2015, 15, 31762–31780 Measurand (Ω)

Max. Relative Error (%)

6.72

0.30

0.11

0.18

0.10

Figure 16. Absolute Absolute value of of the error error for the the calibration techniques techniques described in in Sections2.1 2.1 and4. 4. Figure Figure 16. 16. Absolute value value of the the error for for the calibration calibration techniques described described in Sections Sections 2.1 and and 4.

Figure Figure 17. 17. Relative Relative error error for for the the calibration calibration techniques techniques described described in in Sections Sections 2.1 2.1and and4. 4. Figure 17. Relative error for the calibration techniques described in Sections 2.1 and 4.

The resolutionand and accuracy tests described above were also carried out for the common The tests described above werewere also carried out forout the common PT-1000 The resolution resolution andaccuracy accuracy tests described above also carried for the common PT-1000 temperature sensor. Thistheillustrates the ofperformance of the proposed strategies for a temperature sensor. This illustrates performance the proposed strategies for a different resistance PT-1000 temperature sensor. This illustrates the performance of the proposed strategies for a different resistance range, and allows it to be compared with that achieved by other reported range, andresistance allows it to be compared withitthat achieved by other implementations. For the different range, and allows to be compared withreported that achieved by other reported implementations. Forthe theresolution range of obtained this sensor, theEquation resolution obtained from Equationdata (3) is and the range of this sensor, from (3) and the experimental 11.48 implementations. For the range of this sensor, the resolution obtained from Equation (3) and the experimental data is 11.48 effective number of bits (0.50 Ω), which isthe close to that achieved for the effective number (0.50 Ω), which is close to that foris range of the tactile sensor. experimental dataofisbits 11.48 effective number of bits (0.50achieved Ω), which close to that achieved for the Regarding accuracy, Table 4 shows the results for the one-point, two-point, and the proposed CLChar2 calibration techniques. 16 16

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Table 4. Accuracy data for the PT-1000 temperature sensor and different calibration techniques. Maximum Absolute Error (Ω)

Measurand (Ω)

1 Point Calib.

2 Point Calib.

CLChar2

4.13 2.69 1.79 0.87 0.87 2.09 3.47 4.78 7.42 10.02 11.15 15.11 64.40 0.69

0.59 1.04 1.17 1.39 1.78 2.03 2.64 2.79 3.50 4.38 4.73 5.99 32.03 0.27

0.24 0.30 0.31 0.34 0.34 0.42 0.52 0.52 0.62 0.65 0.60 0.71 5.57 0.04

759.75 876.75 948.55 1016.35 1106.65 1196.15 1296.25 1398.75 1598.25 1798.95 1891.95 2193.85 Total Error Max. Relative Error (%)

Finally, Table 5 shows a comparison between the results obtained with the CM6 capture module and the CLChar 2 calibration technique, and those reported by other authors using direct interface of a PT-1000 sensor with other devices such as microcontrollers, CPLDs or an FPGA from a different vendor [9,12]. Note that the conditions are not the same for all the tests in Table 5, and this should be taken into account for a more thorough comparison. Firstly, the larger the voltage supply the higher the slew rate at the threshold level, which improves precision performance [9]. Secondly, the quantization noise is reduced by increasing values of the time constant [11], although the measurement time is longer and the sample rate decreases. Note that the implementation based on the microcontroller PIC16F87 conducts the two-point calibration technique, therefore it requires the measurement of three resistances per sample. Finally, the results in this paper and those in [12] are given for the worst case of the 500 samples measured, while the average of these samples is reported in [9]. Table 5. A comparison between this proposal and other implementations for the resistors range of PT-1000 temperature sensor ( * worst case, ** averaging 500 samples). Device PIC16F87 [12]* PIC18F458 [9]** CPLD EMP3064A [9]** Cyclone II EP2C20 [9]** Spartan 3AN*

TriggerCalibration Single Event 2 Point Cal. Single Event 1 Point Cal. Single Event 1 Point Cal. Single Event 1 Point Cal. CM6 CLChar2 Cal.

Resistors Range (Ω)

Voltage Supply

RC Constant

Max. Rel. Max. Abs. Uncertainty Error (Ω)

Max. Rel. Error (%)

825´1470

5V

3.23 ms

0.005

0.30

0.02

817.41´2193.95

5V

21.94 ms

0.121

8.89

0.73

817.41´2193.95

3.3 V

21.94 ms

0.497

3.40

0.21

817.41´2193.95

3.3 V

21.94 ms

0.481

26.27

2.57

759.75´2193.85

3.3 V

0.37 ms

0.010

0.71

0.04

7. Conclusions This paper presents circuits to implement smart direct sensor–FPGA interfaces. The proposal is especially interesting for complex systems that collect analog data from many sensors. It is suitable for resistive and capacitive sensors, though the paper shows its performance for two example resistive sensors. Since the hardware in the FPGA is configured to work in parallel, processing and data acquisition can be done in parallel to achieve high throughput and real time operation. A number of capture modules have been proposed and implemented with the aim of improving the precision of measurement. The target is the emulation of the hysteresis present in the input buffers 31778

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of other devices such as microcontrollers by adding memory and smart processing in the digital capture module. The flexibility of the storage elements in the FPGA allows us to work with flip-flops, synchronized with the rising or the falling edge of the clock signal, and to implement strategies that average the count stored by two or four capture modules working in parallel. The idea behind this approach is to filter part of the trigger noise without degrading the bandwidth. Several different design possibilities arise to use the presented capture modules, depending on the target application. If a high precision is required, for instance in the case of non-linear sensors with regions of different sensitivity, the smart module CM6 achieves a precision which is as high as 12 ENOBs for the example tactile sensor of this paper, and a measurement time of 348 µs (taking into account the charging and discharging times of the capacitor). Other capture modules can be chosen if such precision is not necessary to save resources in the FPGA. Besides the capture modules, a calibration technique has been proposed to improve accuracy. It uses the same external resources that the one-point calibration technique based on the measurement of one known calibration resistance. However, it achieves an even better performance than that obtained by calibration with two known resistors. The bandwidth is also better because only one calibration resistance is measured per acquisition. The drawback is that a previous characterization of the input ports of the FPGA is required, since the technique actually infers the value of the input impedance of these ports. Nevertheless, there is no need for specific hardware to characterize the ports, but the same direct interface is used for this purpose. An extension of the technique makes non-linear interpolation to contemplate possible variations of the input impedance of the ports depending on the resistance to be measured, though no significant improvements have been observed for the device of this paper. The proposed technique achieves a resolution as low as 2.42 Ω for an example tactile piezoresistive sensor with a range of interest between 200 Ω and 7350 Ω. Finally, a comparison between the results obtained for a PT-1000 temperature sensor and those reported by other authors, shows improved performance. Acknowledgments: This work has been funded by the Spanish Government and by the European ERDF program funds under contract TEC2012-38653. Author Contributions: This paper is part of the PhD Thesis of Oscar Oballe-Peinado and he is the main contributor. Fernando Vidal-Verdú and José Antonio Hidalgo-López are co-advisors of his PhD Thesis, so both have oriented the work and have helped in the writing and revision of the text. José A. Sánchez-Durán and Julián Castellanos-Ramos have assisted in testing and characterization tasks. Conflicts of Interest: The authors declare no conflict of interest.

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Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programma...
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