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Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system To cite this article: Hyungjin Kim et al 2017 Nanotechnology 28 405202

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Nanotechnology Nanotechnology 28 (2017) 405202 (10pp)

https://doi.org/10.1088/1361-6528/aa86f8

Silicon synaptic transistor for hardwarebased spiking neural network and neuromorphic system Hyungjin Kim , Sungmin Hwang, Jungjin Park and Byung-Gook Park Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea E-mail: [email protected] Received 16 May 2017, revised 15 August 2017 Accepted for publication 18 August 2017 Published 11 September 2017 Abstract

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability. Keywords: synaptic transistor, spike-timing dependent plasticity (STDP), neuromorphic system, spiking neural network, pattern recognition (Some figures may appear in colour only in the online journal) 1. Introduction

and resistive switching memory, based neuromorphic systems have shown great potential towards non-von Neumann computing paradigm with great result of cognitive functions due to high integration density, low power consumption, and gradual switching characteristics [23–27]. However, the twoterminal memristor requires additional selection device because artificial synapses have to transfer signals to the postsynaptic neurons and receive back-propagation signals from the post-synaptic neurons for learning under spike timingdependent plasticity (STDP) rules through the same electrodes [28–33]. Therefore, the selection component of memristor, including transistor, diode, and built-in tunnel barrier, is another important research field which has gained intensive attention in the neuromorphic system community to avoid undesirable current loss as well as to interact with the postsynaptic neurons [34–38]. Kim et al reported the system-level design including the connection between neuron circuits and synaptic devices with carbon nanotube transistors; however, one synapse unit consisted of three transistors because the

Current computing systems based on von Neumann architecture have been suffering from the way they operate through serial information processing [1]. To solve this fundamental problem, there have been a lot of interesting researches about neuromorphic systems by imitating a biological nervous system. Brain-inspired neuromorphic systems have been considered as beyond von Neumann architecture computing systems for their energy-efficiency, parallel signal processing and fault tolerance [2–6]. Above all, synaptic devices are considered as one of the most important parts of neuromorphic systems because it is believed that biological synapses are in charge of signal transmissions and memory effects in our nervous systems [7–11]. Recently, various synaptic devices have been demonstrated to realize hardware-based neural network systems [12–22]. Among them, memristor, one of the strongest candidates for artificial synapses including phase change memory 0957-4484/17/405202+10$33.00

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Nanotechnology 28 (2017) 405202

H Kim et al

Figure 1. Schematic diagram of the direct connection between the synaptic transistors and a neuron circuit.

[40–42]. The G1 with a single SiO2 layer is used to receive signals from pre-synaptic neuron circuit and the second gate (G2) with oxide-nitride-oxide stacks is used to receive signals from post-synaptic one and store charges in its nitride layer. This structural feature makes it possible that multiple presynaptic neuron inputs are transferred to each synaptic transistor and the currents flowing through them are collected at one single node in parallel, called synaptic summation in a biological nervous system [43–45]. Electrical measurement was conducted with a Keithley 4200-SCS semiconductor parameter analyzer in a probe station (MST 8000C). All the pulsed signals were generated and applied with a Keithley 4225 PMU.

inverter made up of two transistors was used as the selection component [39]. Previously, we reported a silicon-based synaptic transistor with short- and long-term memories using asymmetric double-gate structure [40]. In this paper, STDP characteristics of the device are characterized using triangular spikes which can be generated from an integrate-and-fire neuron circuit, and a spiking neural network (SNN) system composed of them is verified. The SNN is constructed without selection devices because of direct interaction between synaptic transistors and neuron circuits through the electrically independent two gates. STDP characteristics are statistically measured and the behavioral model of the device is developed based on the measured data. With the help of the device model, pattern recognition and classification ability of the neural network system is demonstrated using the binary modified national institute of standards and technology (MNIST) handwritten dataset through supervised learning.

3. Results and discussion 3.1. Synaptic characteristics

Triangular pre- and post-synaptic spikes are applied to the device to verify its STDP characteristics as shown in figure 2(a). The pre-synaptic spikes are applied to G1 and drain (D); the post-synaptic spikes are applied to G2. Both spikes are applied together with different timing (Δt) for STDP learning process and only a pre-synaptic spike follows to check conductance changes after that; Δt varied from –5 to 5 μs. The applied spiking waveforms of pre- and postsynaptic spikes, potential difference between two spikes, and the source current response of the device to them at the initial state are plotted in figures 2(b) and (c). When both spikes overlap and potential difference between them is large (small Δt), hot carriers are generated, injected and trapped into the nitride layer, and the type of injected carriers is determined upon the direction of potential difference across two gates. When the device receives the pre-synaptic spike before the post-synaptic spike (Δt>0), the negative part of the post-synaptic spike induces hot hole injection into the nitride

2. Device structure and experimental details The schematic block diagram of the connection between the fabricated synaptic transistors and neuron circuit is shown in figure 1. The main feature of the fabricated synaptic transistor is electrically independent two gates with different gate stacks. The fabrication was carried out following two-step chemical mechanical planarization (CMP) processes to obtain the asymmetric dual-gate structure with different gate stacks. The first CMP was processed after depositing a hard mask stack of 300 nm of SiO2 and 100 nm of Si3N4 layer, etching the first gate (G1) region, and filling it with thermally grown 3.5 nm SiO2 and polycrystalline silicon. The second CMP was done after the fin formation using 50 nm of SiO2 sidewall and deposition of G2 gate stack. The more-detailed description of the process method has been described elsewhere 2

Nanotechnology 28 (2017) 405202

H Kim et al

Figure 2. Experimental results of spike timing-dependent plasticity. (a) Timing diagrams of pre- and post-synaptic spikes with a width of 5 μs and an interval of 30 μs. (b), (c) Measured transient responses of source current when the devices learned under STDP rules for positive Δt and negative Δt at initial state.

on the device state as shown in figure 3(b). The conductance is decreased very slightly when the device is at the depressed state, but there is larger decrease of conductance when the device is at the potentiated state compared to its initial state. The source current changes after applying spikes with different Δt are plotted in figure 4 depending on the device state (initial, potentiated, depressed). The most important feature of the STDP characteristics is that the conductance changes can be obtained by nothing but the spike timing scheme. In addition, the conductance is increased a lot more at the depressed state, and decreased easily at the potentiated state. This strong dependence of the device’s plasticity on its initial state is in line with the previous studies on charge trap flash cells having the nitride layer [47–49]. The shifted transfer curves obtained by applying pre- and post-synaptic spikes 10 times while keeping Δt as 0.5 and −0.5 μs are plotted in figure 5(a). The retention characteristics of multiple threshold voltage (VT) states induced by trapped carriers in G2 stack were demonstrated in [41]. The amount of threshold voltage change (ΔVT) per a spike becomes smaller when those spikes are applied to the device repeatedly, meaning that VT modulation amount at the same

layer and synaptic potentiation as shown in figure 2(b). The source current response to the pre-synaptic spike is increased for small positive delay (Δt=1 μs); however, there is little change in the source current response for large positive delays (Δt=3, 5 μs). This is because the potential difference is dependent on Δt, and the amplitude of potential difference is exponentially related to hot carrier gate current [46]. In contrast, the conductance is decreased for negative delay (Δt1. This result comes from the fact that the output nodes cannot fire by any test samples if Win is too wide because II is higher than IE in most cases, leading to IE−II

Silicon synaptic transistor for hardware-based spiking neural network and neuromorphic system.

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silico...
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