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Roll-to-roll embedded conductive structures integrated into organic photovoltaic devices
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2013 Nanotechnology 24 484014 (http://iopscience.iop.org/0957-4484/24/48/484014) View the table of contents for this issue, or go to the journal homepage for more
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IOP PUBLISHING
NANOTECHNOLOGY
Nanotechnology 24 (2013) 484014 (8pp)
doi:10.1088/0957-4484/24/48/484014
Roll-to-roll embedded conductive structures integrated into organic photovoltaic devices H J van de Wiel1,2 , Y Galagan2 , T J van Lammeren2 , J F J de Riet2 , J Gilot2 , M G M Nagelkerke2 , R H C A T Lelieveld2 , S Shanmugam2 , A Pagudala2 , D Hui3 and W A Groen2 1 2 3
TNO, Materials for Integrated Products, De Rondom 1, 5612 AP, Eindhoven, The Netherlands Holst Centre, PO BOX 8550, 5605 KN Eindhoven, The Netherlands DuPont (UK) Limited, Bristol Business Park, Coldharbour Lane, Frenchay, Bristol BS16 1QD, UK
E-mail: [email protected]
Received 3 June 2013, in final form 30 July 2013 Published 6 November 2013 Online at stacks.iop.org/Nano/24/484014 Abstract Highly conductive screen printed metallic (silver) structures (current collecting grids) combined with poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) are a viable replacement for indium tin oxide (ITO) and inkjet printed silver as transparent electrode materials. To provide successful integration into organic photovoltaic (OPV) devices, screen printed silver current collecting grids should be embedded into a substrate to avoid topology issues. In this study micron-thick conductive structures are embedded and integrated into OPV devices. The embedded structures are produced roll-to-roll with optimized process settings and materials. Topology measurements show that the embedded grids are well suited for integration into OPV devices since the surface is almost without spikes and has low surface roughness. JV measurements of OPV devices with embedded structures on a polyethylene terephthalate/silicon nitride (PET/SiN) substrate show an efficiency of 2.15%, which is significantly higher than identical flexible devices with ITO (1.02%) and inkjet printed silver (1.48%). The use of embedded screen printed silver instead of ITO and inkjet printed silver in OPV devices will allow for higher efficiency devices which can be produced with larger design and process freedom. (Some figures may appear in colour only in the online journal)
1. Introduction
the material to be built up consistently and reproducibly. Moreover, ITO offers good electrical conductivity (on glass) while being sufficiently transparent (>80%) at layer thicknesses below 380 nm. However, flexible OPVs require substitution of glass by flexible substrates such as polyethylene naphthalate (PEN) or polyethylene terephthalate (PET) which significantly reduce the electrical conductivity of ITO [1]. The relatively low glass transition temperatures of both PEN (∼120 ◦ C) and PET (∼78 ◦ C) limit the allowable annealing temperature of ITO which is required to improve its conductivity. This results in higher sheet resistance. The sheet resistance of ITO on PEN or PET is between 20 and 60 / depending on the allowable annealing temperature [1]. The
The demand for flexible large area electronics such as organic light-emitting diodes (OLEDs) and organic photovoltaics (OPVs) is growing [1]. These flexible electronics, when produced with roll-to-roll (R2R) [2–7] compatible processes, promise cost reductions with respect to conventional (rigid) electronics [8, 9]. Moreover, the flexibility of these macroelectronics allows for new uses and/or different form-factors. For OPVs one of the electrodes must be transparent. Transparent conducting oxides (TCOs) [10] can meet these requirements. Often for macro-electronic devices the TCO is indium tin oxide (ITO) [10]. High vacuum deposition of ITO, like sputtering, is a mature technology which allows 0957-4484/13/484014+08$33.00
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c 2013 IOP Publishing Ltd Printed in the UK & the USA
Nanotechnology 24 (2013) 484014
H J van de Wiel et al
higher resistance limits the use of ITO to small areas of 1 cm2 on glass and 0.5 cm2 on a flexible substrate [11–13]. On larger areas the Ohmic losses are too high, which will result in lower current transport (OPV). Increasing the ITO thickness will reduce the sheet resistance, however at an unaffordable cost of transparency. Finally, ITO is relatively brittle; relatively low thermo-mechanical loads damage the ITO electrode. The damage will result in degrading performance during its life-time [14, 15]. Possible replacements for ITO are highly conductive printed metallic (silver) structures (current collecting grids) combined with poly(3,4-ethylenedioxythiophene): poly(styrene sulfonate) (PEDOT:PSS). Inkjet printed current collecting grids have sheet resistance in the range of 5–15 / with surface coverage below 10% [16–19]. The sheet resistance of screen printed current collecting grids is in the order of 0.1–1 / [17]. This is significantly lower than the sheet resistance of both ITO and inkjet printed grids, and as a result screen printed silver grids combined with PEDOT:PSS allow for larger area OPVs [20]. Moreover, it is expected that silver is less susceptible to fracture than ITO. However, the grid height of the silver structures must be in the order of several microns to achieve the low sheet resistances. The topology of the screen printed structures often shows high spikes and roughness which prohibits its use in OPVs [21], since this will result in electric short circuits. A possible solution is to embed the high and the rough conductive structures into a substrate or resist deposited on top of a substrate [17, 22, 23]. The embedded micron-thick conductive structures leave a very smooth surface almost without spikes, which may be suited to allowing embedded structures to be integrated into flexible macro-electronics. This paper discusses the integration of R2R produced embedded conductive silver structures into OPV devices. The composite electrode containing embedded current collecting grids in combination with high conducting PEDOT:PSS is a good alternative to ITO electrodes. Flexible OPV devices with embedded current collecting grids have significantly improved efficiencies over large areas compared to ITO-based devices.
Figure 1. Typical topology height profile of a conductive grid design as screen printed.
Figure 2. Schematic overview of the R2R embedding process including lamination, curing and delamination.
The high and rough topology of the silver grid lines as printed does not allow for integration into OPVs. To allow for integration of the silver into OPV devices the peak height should be less than 500 nm, while the RMS roughness and spike height should be less than 50 nm. [21]. A low and smooth topology can be achieved by an R2R embedding process. This comprises three phases, which are lamination, curing and delamination, as is depicted in figure 2. Firstly, prior the embedding process silver structures are screen printed on the so-called donor PEN substrate. The conductive structures can be printed R2R by rotary screen printing. The silver is subsequently sintered in at 150 ◦ C. Then the donor substrate with the sintered screen printed structures is laminated with the so-called acceptor substrate: the silver screen printed structures are submerged into a resist which is deposited on the acceptor PEN substrate. Figure 3(a) depicts the lamination of donor and acceptor substrates. Secondly, the resist is cured by UV light while applying pressure on both donor and acceptor substrates as is depicted in figure 3(b). The UV light illuminates the resist through the acceptor substrate. The curing time depends on the UV curing agent and the resist layer thickness. Thirdly, the donor substrate is delaminated which is presented in figure 3(c). To allow for complete transfer of the silver without inducing any damage to both resist and silver during the delamination, the adhesion of both the silver and resist to the donor substrate should be lower than the adhesion of the silver to the resist and the adhesion of the resist to the acceptor substrate, in order to minimize the energy required to release the donor substrate. Moreover, the cohesion of both
2. Background of embedded structures Conductive structures screen printed on PEN substrate show high topology with high roughness and spikes. A typical measured topography of a screen printed silver grid line on PEN substrate is presented in figure 1. The peak height of the grid line is ∼5500 nm. The root mean square (RMS) roughness is 500 nm. The spike heights are maximum 2000 nm. Moreover, plastic deformation of the (thermoplastic) PEN substrate is observed as is depicted by the red-dotted line in figure 1. The topography shows a deformation of approximately 300 nm below the grid line. The PEN is plastically deformed during the sintering process of the silver. The deformation of the substrate below the grid line can be approximated by fitting a parabolic function through the measured substrate deformations at the edges of the grid line. 2
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Figure 3. (a) Lamination of the donor substrate on which the conductive structures are printed with the acceptor substrate on which the resist is deposited; (b) curing of the resist using UV light while applying pressure on both donor and acceptor substrates; (c) delamination of the donor substrate leaving the silver embedded into the cured resist.
Agfa-Gevaert) is spin coated on top of the embedded current collecting grids. The devices with ITO electrode are used as a reference. The thickness of PEDOT:PSS, with conductivity of 500 S cm−1 , is 100 nm. It provides sheet resistances of 200 / for PEDOT:PSS layers. Poly(3hexylthiophene) (P3HT) (Plextronics, Plexcore OS 2100) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) (99%, Solenne BV) with a concentration of 2 wt% each are dissolved in 1,2-dichlorobenzene. The solution is stirred for 24 h at 80 ◦ C. The photoactive layer is obtained by spin coating of the blend at 1000 rpm for 60 s, which corresponds to a thickness of 220 nm. The experiments are performed in a clean-room environment at ambient atmosphere. The metal cathode (1 nm LiF, 100 nm Al) is thermally evaporated in a vacuum chamber through a shadow mask. A schematic illustration of the devices with current collecting grids is shown in figure 4(a). The geometry of the grids and top evaporated electrode (LiF/Al) is shown in figure 4(b). The finished OPV devices are encapsulated with Holst Centre thin film barrier to allow current–voltage measurements outside the glove box [24]. Current–voltage curves are measured with simulated AM 1.5 global solar irradiation (100 mW cm−2 ), using a xenon-lamp-based solar simulator, an Oriel (LS0104) 150 W. The light source is calibrated with a standard Si photodiode detector.
resist and silver should be high, to minimize the chances for damage at weak spots such as the edges of the silver grid line (limited load-bearing volume). The embedded screen printed conductive silver structures have significantly lower peak height, spikes and surface roughness. The topology of the embedded structures is similar to the donor PEN substrate including the sinter deformation (resulting in the peak height).
3. Experimental approach R2R embedding experiments are performed using different process settings, resists and silver inks in order to optimize both the process and materials for lowest topography and roughness. Firstly, different silver inks are screen printed using the DEK Horizon 03i with Stork Prints PlanoMesh (electroformed nickel) on PEN donor substrate after which these are sintered at a temperature of 150 ◦ C for 30 min. One of the silver inks which is used is specifically designed for embedding by DuPont Limited. After embedding, the substrate with the embedded screen printed conductive silver structures for nine OPV devices is cut to 6 in × 6 in. Subsequently, the printed structures are R2R embedded with different process settings into different resists which are deposited on the acceptor substrate. The embedding is performed with a custom setup which is schematically displayed in figure 2. Two different acceptor substrates are R used: PEN (Teijin DuPont Films, Teonex Q65FA, 125 µm thick) and PET/SiN. The PET/SiN substrate is PET substrate with PCVD deposited silicon nitride (Six Ny ) layer. The SixNy layer has water and oxygen barrier properties which are required to extend the life-time of OPV devices. The embedded structures are characterized for their topology to determine the quality of embedding in terms of the average peak height, valley depth, ratio of embedding, RMS roughness and spike height. The topology of the embedded structures is measured with a Bruker Dektak XT surface profiler. The Dektak measurements are performed with a tip radius of 12.5 µm, a tip load of 3 mg and a scan resolution of 0.071 µm/point. For the preparation of OPV devices with both ITO and embedded grids, highly conductive PEDOT:PSS (OrgaconTM ,
4. Results and discussion The embedding experiments are performed with different process settings and materials. Firstly, a typical height profile of an embedded grid line produced on PEN substrate with non-optimized embedding process settings, resist and silver is presented in figure 5(a). The peak height, which is defined as the maximum height of the embedded structure above the resist, is on average 247 nm with a standard deviation of 104 nm based on 15 measurements at random locations. The embedded area is used to calculate the embedding ratio, which is equal to the cross-sectional area which is not embedded divided by the average area of the grid line as printed. In the case of a fully embedded structure the embedding ratio is equal to 100%. For the structure in figure 5(a) 3
Nanotechnology 24 (2013) 484014
H J van de Wiel et al
through the height profile. The line is fitted with a robust weighted quadratic least squares regression method. The valley depth, RMS roughness and spike height of the non-optimized embedded grid line is determined using a filtered height profile which is presented in figure 5(b). The filtered profile is calculated by subtracting the fitted height profile (red-dotted line in figure 5(a)) from the measured height profile. The valley depth is equal to the minimum height. The valley depth is on average 115 nm with a standard deviation of 87 nm. The RMS roughness is equal to the root mean square of the height profile minus the average height of the filtered height profile. The average RMS roughness is 28 nm with a standard deviation of 15 nm. Finally, the spike height is equal to the highest spike in the filtered height profile. The average spike height is measured as 134 nm with a standard deviation of 119 nm. The deep valleys, RMS roughness (including the variation) and high spikes of the embedded grids produced with non-optimized process settings and materials do not allow for integration of the embedded grids into OPV devices. In particular, the high spikes will most likely cause electric short circuits. The process settings and materials are optimized to achieve smooth topology of the embedded grids. The process parameters which are optimized include the lamination methodology, the resist deposition technique, the lamination and delamination pressure and the web speed. The resist is selected for highest adhesion to both the acceptor substrate and the silver. Finally, a silver ink is specifically developed for embedding by DuPont Limited. The cohesion of the silver ink is high while adhesion to the donor substrate is low. A typical height profile of an embedded grid line produced on PEN acceptor substrate with optimized embedding process settings and materials including the DuPont Limited silver ink is presented in figure 6. The height profile and filtered height profile show a smooth topology. The peak height is on average 275 nm with a standard deviation
Figure 4. Schematic illustration of the devices with embedded current collecting grids (a) and geometry of current collecting grids, PEDOT:PSS, top electrode (b).
the embedding ratio is on average 92% with a standard deviation of 1.8%. Moreover, the height profile shows that the embedded structure is damaged at the edges. Pieces of embedded structure have broken loose during delamination of the donor substrate. Finally, a line is fitted (red-dotted line)
Figure 5. (a) The height profile of an embedded structure produced with non-optimized materials and embedding process settings. The height profile shows the peak height, the embedded area and damage at the edges of the grid line. Furthermore, a line is fitted through the height profile (red-dotted line) to allow us to determine valley depth, RMS roughness and spike height. (b) The filtered height profile of the embedded grid line produced with non-optimized process settings and materials. The filtered profile is used to calculate the valley depth, RMS roughness and spike height. 4
Nanotechnology 24 (2013) 484014
H J van de Wiel et al
Figure 6. (a) Typical height profile of an embedded grid and (b) the filtered height profile of the embedded grid produced with optimized process settings and materials (DuPont embedding silver ink).
Figure 7. Optical microscope image of the PET/SiN/resist substrate with embedded Ag grids, and SEM image of embedded Ag track.
of 38 nm. The embedding ratio is 97% with a standard deviation of 0.5%. The valley depth is 5 nm with a standard deviation of 2 nm. The RMS surface roughness is 2 nm with a standard deviation of 0.5 nm. Finally, the spike height is on average 8 nm with a standard deviation of 4 nm. The optical microscope image of the PET/SiN/resist substrate with embedded Ag grids, and the SEM image of embedded Ag track, are shown in figure 7. The embedded structures produced with the optimized process settings and materials on PEN acceptor substrate show smooth topology suitable for integration into OPV devices. The peak height is well below 500 nm and the valley depth, RMS roughness and spike height are well below 50 nm. The embedding ratio of 97% is near maximum and is the result of the substrate deformation during the sintering process of the silver. Moreover, the variation within a product and between different products is small. The standard deviation is maximum 38 nm (variation of the peak height). The small variation indicates that the embedding of conductive structures can be performed repeatedly and reproducibly.
Using the optimized process settings and silver ink, embedded grids are produced on PET/SiN. The resist which is used for embedding on PEN substrate is replaced by another resist which better adheres to the PET/SiN substrate. It is anticipated that the produced embedded grids will have similar topology with respect to the embedded grids produced on PEN acceptor substrate. Photographs of the embedded structure on PET/SiN substrate and the complete OPV device are presented in figure 8. OPV devices are produced on both PEN and PET/SiN substrates using embedded grids produced with optimized process settings and materials. The thickness of highly conductive PEDOT:PSS (OrgaconTM , Agfa-Gevaert) of 100 nm, as well as the grid spacing of 2 mm, were optimized to provide for an optimal ratio of conductivity and transparency in order to gain maximum device performance [18, 21]. The optical transmission spectra of the PEN and PET/SIN foils covered with the resist material are shown in figure 9. The average optical transmittance of the PEDOT:PSS layer in the visible range is 93%, as is shown in figure 9. The optical transmission spectrum of 5
Nanotechnology 24 (2013) 484014
H J van de Wiel et al
Figure 8. Left side, photograph of embedded structures on PET/SiN. The outer dimensions of the embedded screen printed structures are 2.4 × 2.5 cm2 . The right side shows a detail of the OPV device with embedded structures on PET/SiN.
Figure 9. Optical transmission of the PEN and PET/SiN foils covered with resist, PEDOT:PSS layer and PET/SiN/resist/PEDOT:PSS foil.
Figure 10. JV curves of the OPV device with embedded structure on PET/SiN and the OPV device with ITO electrode.
the PET/SiN/resist foil with the PEDOT:PSS layer gives an average transmittance of 82% in the wavelength range of 450–600 nm (absorption maximum of P3HT) as is shown in figure 9. The area covered with grids remains completely non-transparent in the visible region. The grid coverage in the devices is 4.5%, which reduces the total transparency of the substrate/electrode by 4.5%. The measured JV characteristics of 2 × 2 cm2 ITO-free OPV devices with embedded grids produced on both types of substrate (PEN and PET/SiN) are identical. For comparison, a reference device with the same dimensions is produced on PET/SiN using an ITO electrode. The typical JV curves for both the ITO-based and ITO-free devices with embedded grids are presented in figure 10. The sheet resistance of the bottom electrode and photovoltaic performance parameters (the open circuit voltage (Voc ), the fill factor (FF) and the Power Conversion Efficiency (PCE)) of the respective devices are summarized in table 1. The ITO-based devices with an active area of 2 × 2 cm2 show an efficiency of only 1%. The ITO-free devices with embedded grids have an average efficiency of 2.15%, which is more than twice as high as the efficiency of ITO-based devices with the same active area.
The lower efficiency of the ITO-based devices can be explained by the higher resistance of the ITO electrode. A higher sheet resistance increases the series resistance, which in its turn decreases the fill factor, the Jsc and the efficiency. The strong dependence of the OPV device efficiency on the sheet resistance is depicted in figure 11 using results from previous and present experiments [17, 21]. The figure shows that the efficiency of the 2 × 2 cm2 devices decreases with increasing sheet resistance. The OPV devices of the present paper produced with embedded screen printed current collecting grids combined with PEDOT:PSS have the highest power conversion efficiency of 2.15% and the lowest sheet resistance of 0.21 / (the resistivity of the printed line is 5.12 × 10−8 m) for a grid surface coverage of 4.5%. The second highest efficiency is measured for devices produced with embedded screen printed current collecting grids combined with highly conductive PEDOT from [17]. The devices have an efficiency of 1.92% and a sheet resistance of 1 /. The devices with the inkjet printed current collecting grids have the third highest efficiency of 6
Nanotechnology 24 (2013) 484014
H J van de Wiel et al
Table 1. Characteristics of the OPV devices. Transparent electrode
Sheet resistance (/)
Voc (V)
Jsc (mA cm−2 )
FF
PCE (%)
ITO-substrate Embedded screen printed Ag-grid/PEDOT
60 0.21/500
0.49 0.53
6.96 8.00
0.30 0.51
1.02 2.15
well below the tolerable 500 nm and valley depths, RMS roughness and spike heights below a tolerable 50 nm are possible, enabling the successful integration of these foils into OPV devices. JV measurements of OPV devices with embedded structures on PET/SiN substrate show significantly higher PCE than identical flexible devices with ITO (1.02%) and inkjet printed silver (1.48%). This is mainly the result of the much lower sheet resistance of the embedded grid structure. The efficiency of 2 × 2 cm2 devices decreases with increasing sheet resistance. The lower sheet resistance of silver in comparison to inkjet printed silver and ITO (0.21 / versus 4.83 / and 60 / respectively) opens up the potential of producing large area OPV devices with greater process and design freedom. Furthermore, silver is more suited for flexible macroelectronics because of its higher thermo-mechanical robustness in comparison to ITO. The brittle behavior of ITO puts a limit on the amount of thermo-mechanical load it can withstand. Moreover, the brittle ITO does not allow for small bend radii. At relatively low loads ITO will degrade and crack. Silver however is less brittle. For this reason it is expected that silver will be able to withstand higher thermo-mechanical loads.
Figure 11. Power conversion efficiency of 2 × 2 cm2 OPV devices on plastic substrates versus sheet resistance of transparent electrode.
1.48% for a sheet resistance of 4.83 / (the resistivity of the printed lines is 2.4 × 10−7 m) [21]. The devices produced with the ITO transparent electrode of the present paper have an efficiency of 1.02% for a sheet resistance of 60 /. Finally, the devices produced with the PEDOT:PSS transparent electrode have the lowest efficiency of 0.71% and the highest sheet resistance of 200 / [21]. The influence of the sheet resistance on the device efficiency is less pronounced for small devices, however it becomes more pronounced when scaling up the active area of organic solar cells [25]. Increasing the active area is required to allow for reduction of the cost price. However, the allowable cell and module dimensions are restricted by the sheet resistance of the electrode. The low resistivity of the embedded screen printed current collecting grids allows us to scale up the cell dimensions. This is a significant advantage over the ITO electrode for which the cell dimension (maximum 0.5 cm2 on flexible substrate) is strongly limited by the high series resistance due to the higher sheet resistance of the electrode.
Acknowledgments The authors would like to acknowledge and thank the Dutch Ministry of Economic Affairs, NanoNextNL, the financial support of the European Community’s Seventh Framework Programme (FP7/2007–2013) under Grant No. 287818 of the X10D project and DuPont (UK) Limited gratefully.
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5. Conclusions R2R embedding of screen printed metal structures is a technology which allows the production of functional foils combining low sheet resistances and high optical transparencies with minimal surface topologies. After optimization of the process settings and materials, embedding ratios of up to 97% can be achieved with high reproducibility on both PEN and PET/SiN acceptor substrates. Peak heights 7
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[16] Galagan Y, Coenen E W C, Abbel R, Van Lammeren T J, Sabik S, Barink M, Meinders E R, Andriessen R and Blom P W M 2013 Photonic sintering of inkjet printed current collecting grids for organic solar cell applications Org. Electron. 14 38–46 [17] Galagan Y, Rubingh J E J M, Andriessen R, Fan C C, Blom P W M, Veenstra S C and Kroon J M 2011 ITO-free flexible organic solar cells with printed current collecting grids Sol. Energy Mater. Sol. Cells 95 1339–43 [18] Galagan Y et al 2012 Current collecting grids for ITO-free solar cells Adv. Energy Mater. 2 103–10 [19] Galagan Y, Manor A, Andriessen R and Katz E A 2012 Analysis of light intensity dependence of organic photovoltaics: towards efficient large-area solar cells 38th IEEE Photovoltaic Specialists Conf. (Austin, TX) pp 2750–2 [20] van Lammeren T J and Rubing E Apparatus and method for providing an embedded structure and for providing an electro-optical device including the same WO Patent Specification WO2012134286 [21] Galagan Y, Coenen E W C, Sabik S, Gorter H H, Barink M, Veenstra S C, Kroon J M, Andriessen R and Blom P W M 2012 Evaluation of ink-jet printed current collecting grids and busbars for ITO-free organic solar cells Sol. Energy Mater. Sol. Cells 104 32–8 [22] Li Y, Mao L, Gao Y, Zhang P, Li C, Ma C, Tu Y, Cui Z and Chen L 2013 ITO-free photovoltaic cell utilizing a high-resolution silver grid current collecting layer Sol. Energy Mater. Sol. Cells 113 85–9 [23] Yu J S, Kim I, Kim J S, Jo J, Larsen-Olsen T T, Søndergaard R R, H¨osel M, Angmo D, Jørgensen M and Krebs F C 2012 Silver front electrode grids for ITO-free all printed polymer solar cells with embedded and raised topographies, prepared by thermal imprint, flexographic and inkjet roll-to-roll processes Nanoscale 4 6032–40 [24] van Assche F, Rooms H, Young E, Michels J, van Mol T, Rietjens G, van de Weijer P and Bouten P 2008 Thin-film barrier on foil for organic LED lamps AIMCAL Fall Technical Conf. and 22nd Int. Vacuum Web Coating Conf. [25] Galagan Y, Coenen E W C, Zimmermann B, Slooff L H, Verhees W J H, Veenstra S C, Kroon J M, Jørgensen M, Krebs F C and Andriessesn A 2013 Adv. Energy Mater. at press doi:10.1002/aenm.201300225
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Roll-to-roll embedded conductive structures integrated into organic photovoltaic devices
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2013 Nanotechnology 24 484014 (http://iopscience.iop.org/0957-4484/24/48/484014) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 128.248.155.225 This content was downloaded on 05/02/2014 at 15:29
Please note that terms and conditions apply.
IOP PUBLISHING
NANOTECHNOLOGY
Nanotechnology 24 (2013) 484014 (8pp)
doi:10.1088/0957-4484/24/48/484014
Roll-to-roll embedded conductive structures integrated into organic photovoltaic devices H J van de Wiel1,2 , Y Galagan2 , T J van Lammeren2 , J F J de Riet2 , J Gilot2 , M G M Nagelkerke2 , R H C A T Lelieveld2 , S Shanmugam2 , A Pagudala2 , D Hui3 and W A Groen2 1 2 3
TNO, Materials for Integrated Products, De Rondom 1, 5612 AP, Eindhoven, The Netherlands Holst Centre, PO BOX 8550, 5605 KN Eindhoven, The Netherlands DuPont (UK) Limited, Bristol Business Park, Coldharbour Lane, Frenchay, Bristol BS16 1QD, UK
E-mail: [email protected]
Received 3 June 2013, in final form 30 July 2013 Published 6 November 2013 Online at stacks.iop.org/Nano/24/484014 Abstract Highly conductive screen printed metallic (silver) structures (current collecting grids) combined with poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) are a viable replacement for indium tin oxide (ITO) and inkjet printed silver as transparent electrode materials. To provide successful integration into organic photovoltaic (OPV) devices, screen printed silver current collecting grids should be embedded into a substrate to avoid topology issues. In this study micron-thick conductive structures are embedded and integrated into OPV devices. The embedded structures are produced roll-to-roll with optimized process settings and materials. Topology measurements show that the embedded grids are well suited for integration into OPV devices since the surface is almost without spikes and has low surface roughness. JV measurements of OPV devices with embedded structures on a polyethylene terephthalate/silicon nitride (PET/SiN) substrate show an efficiency of 2.15%, which is significantly higher than identical flexible devices with ITO (1.02%) and inkjet printed silver (1.48%). The use of embedded screen printed silver instead of ITO and inkjet printed silver in OPV devices will allow for higher efficiency devices which can be produced with larger design and process freedom. (Some figures may appear in colour only in the online journal)
1. Introduction
the material to be built up consistently and reproducibly. Moreover, ITO offers good electrical conductivity (on glass) while being sufficiently transparent (>80%) at layer thicknesses below 380 nm. However, flexible OPVs require substitution of glass by flexible substrates such as polyethylene naphthalate (PEN) or polyethylene terephthalate (PET) which significantly reduce the electrical conductivity of ITO [1]. The relatively low glass transition temperatures of both PEN (∼120 ◦ C) and PET (∼78 ◦ C) limit the allowable annealing temperature of ITO which is required to improve its conductivity. This results in higher sheet resistance. The sheet resistance of ITO on PEN or PET is between 20 and 60 / depending on the allowable annealing temperature [1]. The
The demand for flexible large area electronics such as organic light-emitting diodes (OLEDs) and organic photovoltaics (OPVs) is growing [1]. These flexible electronics, when produced with roll-to-roll (R2R) [2–7] compatible processes, promise cost reductions with respect to conventional (rigid) electronics [8, 9]. Moreover, the flexibility of these macroelectronics allows for new uses and/or different form-factors. For OPVs one of the electrodes must be transparent. Transparent conducting oxides (TCOs) [10] can meet these requirements. Often for macro-electronic devices the TCO is indium tin oxide (ITO) [10]. High vacuum deposition of ITO, like sputtering, is a mature technology which allows 0957-4484/13/484014+08$33.00
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higher resistance limits the use of ITO to small areas of 1 cm2 on glass and 0.5 cm2 on a flexible substrate [11–13]. On larger areas the Ohmic losses are too high, which will result in lower current transport (OPV). Increasing the ITO thickness will reduce the sheet resistance, however at an unaffordable cost of transparency. Finally, ITO is relatively brittle; relatively low thermo-mechanical loads damage the ITO electrode. The damage will result in degrading performance during its life-time [14, 15]. Possible replacements for ITO are highly conductive printed metallic (silver) structures (current collecting grids) combined with poly(3,4-ethylenedioxythiophene): poly(styrene sulfonate) (PEDOT:PSS). Inkjet printed current collecting grids have sheet resistance in the range of 5–15 / with surface coverage below 10% [16–19]. The sheet resistance of screen printed current collecting grids is in the order of 0.1–1 / [17]. This is significantly lower than the sheet resistance of both ITO and inkjet printed grids, and as a result screen printed silver grids combined with PEDOT:PSS allow for larger area OPVs [20]. Moreover, it is expected that silver is less susceptible to fracture than ITO. However, the grid height of the silver structures must be in the order of several microns to achieve the low sheet resistances. The topology of the screen printed structures often shows high spikes and roughness which prohibits its use in OPVs [21], since this will result in electric short circuits. A possible solution is to embed the high and the rough conductive structures into a substrate or resist deposited on top of a substrate [17, 22, 23]. The embedded micron-thick conductive structures leave a very smooth surface almost without spikes, which may be suited to allowing embedded structures to be integrated into flexible macro-electronics. This paper discusses the integration of R2R produced embedded conductive silver structures into OPV devices. The composite electrode containing embedded current collecting grids in combination with high conducting PEDOT:PSS is a good alternative to ITO electrodes. Flexible OPV devices with embedded current collecting grids have significantly improved efficiencies over large areas compared to ITO-based devices.
Figure 1. Typical topology height profile of a conductive grid design as screen printed.
Figure 2. Schematic overview of the R2R embedding process including lamination, curing and delamination.
The high and rough topology of the silver grid lines as printed does not allow for integration into OPVs. To allow for integration of the silver into OPV devices the peak height should be less than 500 nm, while the RMS roughness and spike height should be less than 50 nm. [21]. A low and smooth topology can be achieved by an R2R embedding process. This comprises three phases, which are lamination, curing and delamination, as is depicted in figure 2. Firstly, prior the embedding process silver structures are screen printed on the so-called donor PEN substrate. The conductive structures can be printed R2R by rotary screen printing. The silver is subsequently sintered in at 150 ◦ C. Then the donor substrate with the sintered screen printed structures is laminated with the so-called acceptor substrate: the silver screen printed structures are submerged into a resist which is deposited on the acceptor PEN substrate. Figure 3(a) depicts the lamination of donor and acceptor substrates. Secondly, the resist is cured by UV light while applying pressure on both donor and acceptor substrates as is depicted in figure 3(b). The UV light illuminates the resist through the acceptor substrate. The curing time depends on the UV curing agent and the resist layer thickness. Thirdly, the donor substrate is delaminated which is presented in figure 3(c). To allow for complete transfer of the silver without inducing any damage to both resist and silver during the delamination, the adhesion of both the silver and resist to the donor substrate should be lower than the adhesion of the silver to the resist and the adhesion of the resist to the acceptor substrate, in order to minimize the energy required to release the donor substrate. Moreover, the cohesion of both
2. Background of embedded structures Conductive structures screen printed on PEN substrate show high topology with high roughness and spikes. A typical measured topography of a screen printed silver grid line on PEN substrate is presented in figure 1. The peak height of the grid line is ∼5500 nm. The root mean square (RMS) roughness is 500 nm. The spike heights are maximum 2000 nm. Moreover, plastic deformation of the (thermoplastic) PEN substrate is observed as is depicted by the red-dotted line in figure 1. The topography shows a deformation of approximately 300 nm below the grid line. The PEN is plastically deformed during the sintering process of the silver. The deformation of the substrate below the grid line can be approximated by fitting a parabolic function through the measured substrate deformations at the edges of the grid line. 2
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Figure 3. (a) Lamination of the donor substrate on which the conductive structures are printed with the acceptor substrate on which the resist is deposited; (b) curing of the resist using UV light while applying pressure on both donor and acceptor substrates; (c) delamination of the donor substrate leaving the silver embedded into the cured resist.
Agfa-Gevaert) is spin coated on top of the embedded current collecting grids. The devices with ITO electrode are used as a reference. The thickness of PEDOT:PSS, with conductivity of 500 S cm−1 , is 100 nm. It provides sheet resistances of 200 / for PEDOT:PSS layers. Poly(3hexylthiophene) (P3HT) (Plextronics, Plexcore OS 2100) and [6,6]-phenyl-C61-butyric acid methyl ester (PCBM) (99%, Solenne BV) with a concentration of 2 wt% each are dissolved in 1,2-dichlorobenzene. The solution is stirred for 24 h at 80 ◦ C. The photoactive layer is obtained by spin coating of the blend at 1000 rpm for 60 s, which corresponds to a thickness of 220 nm. The experiments are performed in a clean-room environment at ambient atmosphere. The metal cathode (1 nm LiF, 100 nm Al) is thermally evaporated in a vacuum chamber through a shadow mask. A schematic illustration of the devices with current collecting grids is shown in figure 4(a). The geometry of the grids and top evaporated electrode (LiF/Al) is shown in figure 4(b). The finished OPV devices are encapsulated with Holst Centre thin film barrier to allow current–voltage measurements outside the glove box [24]. Current–voltage curves are measured with simulated AM 1.5 global solar irradiation (100 mW cm−2 ), using a xenon-lamp-based solar simulator, an Oriel (LS0104) 150 W. The light source is calibrated with a standard Si photodiode detector.
resist and silver should be high, to minimize the chances for damage at weak spots such as the edges of the silver grid line (limited load-bearing volume). The embedded screen printed conductive silver structures have significantly lower peak height, spikes and surface roughness. The topology of the embedded structures is similar to the donor PEN substrate including the sinter deformation (resulting in the peak height).
3. Experimental approach R2R embedding experiments are performed using different process settings, resists and silver inks in order to optimize both the process and materials for lowest topography and roughness. Firstly, different silver inks are screen printed using the DEK Horizon 03i with Stork Prints PlanoMesh (electroformed nickel) on PEN donor substrate after which these are sintered at a temperature of 150 ◦ C for 30 min. One of the silver inks which is used is specifically designed for embedding by DuPont Limited. After embedding, the substrate with the embedded screen printed conductive silver structures for nine OPV devices is cut to 6 in × 6 in. Subsequently, the printed structures are R2R embedded with different process settings into different resists which are deposited on the acceptor substrate. The embedding is performed with a custom setup which is schematically displayed in figure 2. Two different acceptor substrates are R used: PEN (Teijin DuPont Films, Teonex Q65FA, 125 µm thick) and PET/SiN. The PET/SiN substrate is PET substrate with PCVD deposited silicon nitride (Six Ny ) layer. The SixNy layer has water and oxygen barrier properties which are required to extend the life-time of OPV devices. The embedded structures are characterized for their topology to determine the quality of embedding in terms of the average peak height, valley depth, ratio of embedding, RMS roughness and spike height. The topology of the embedded structures is measured with a Bruker Dektak XT surface profiler. The Dektak measurements are performed with a tip radius of 12.5 µm, a tip load of 3 mg and a scan resolution of 0.071 µm/point. For the preparation of OPV devices with both ITO and embedded grids, highly conductive PEDOT:PSS (OrgaconTM ,
4. Results and discussion The embedding experiments are performed with different process settings and materials. Firstly, a typical height profile of an embedded grid line produced on PEN substrate with non-optimized embedding process settings, resist and silver is presented in figure 5(a). The peak height, which is defined as the maximum height of the embedded structure above the resist, is on average 247 nm with a standard deviation of 104 nm based on 15 measurements at random locations. The embedded area is used to calculate the embedding ratio, which is equal to the cross-sectional area which is not embedded divided by the average area of the grid line as printed. In the case of a fully embedded structure the embedding ratio is equal to 100%. For the structure in figure 5(a) 3
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through the height profile. The line is fitted with a robust weighted quadratic least squares regression method. The valley depth, RMS roughness and spike height of the non-optimized embedded grid line is determined using a filtered height profile which is presented in figure 5(b). The filtered profile is calculated by subtracting the fitted height profile (red-dotted line in figure 5(a)) from the measured height profile. The valley depth is equal to the minimum height. The valley depth is on average 115 nm with a standard deviation of 87 nm. The RMS roughness is equal to the root mean square of the height profile minus the average height of the filtered height profile. The average RMS roughness is 28 nm with a standard deviation of 15 nm. Finally, the spike height is equal to the highest spike in the filtered height profile. The average spike height is measured as 134 nm with a standard deviation of 119 nm. The deep valleys, RMS roughness (including the variation) and high spikes of the embedded grids produced with non-optimized process settings and materials do not allow for integration of the embedded grids into OPV devices. In particular, the high spikes will most likely cause electric short circuits. The process settings and materials are optimized to achieve smooth topology of the embedded grids. The process parameters which are optimized include the lamination methodology, the resist deposition technique, the lamination and delamination pressure and the web speed. The resist is selected for highest adhesion to both the acceptor substrate and the silver. Finally, a silver ink is specifically developed for embedding by DuPont Limited. The cohesion of the silver ink is high while adhesion to the donor substrate is low. A typical height profile of an embedded grid line produced on PEN acceptor substrate with optimized embedding process settings and materials including the DuPont Limited silver ink is presented in figure 6. The height profile and filtered height profile show a smooth topology. The peak height is on average 275 nm with a standard deviation
Figure 4. Schematic illustration of the devices with embedded current collecting grids (a) and geometry of current collecting grids, PEDOT:PSS, top electrode (b).
the embedding ratio is on average 92% with a standard deviation of 1.8%. Moreover, the height profile shows that the embedded structure is damaged at the edges. Pieces of embedded structure have broken loose during delamination of the donor substrate. Finally, a line is fitted (red-dotted line)
Figure 5. (a) The height profile of an embedded structure produced with non-optimized materials and embedding process settings. The height profile shows the peak height, the embedded area and damage at the edges of the grid line. Furthermore, a line is fitted through the height profile (red-dotted line) to allow us to determine valley depth, RMS roughness and spike height. (b) The filtered height profile of the embedded grid line produced with non-optimized process settings and materials. The filtered profile is used to calculate the valley depth, RMS roughness and spike height. 4
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Figure 6. (a) Typical height profile of an embedded grid and (b) the filtered height profile of the embedded grid produced with optimized process settings and materials (DuPont embedding silver ink).
Figure 7. Optical microscope image of the PET/SiN/resist substrate with embedded Ag grids, and SEM image of embedded Ag track.
of 38 nm. The embedding ratio is 97% with a standard deviation of 0.5%. The valley depth is 5 nm with a standard deviation of 2 nm. The RMS surface roughness is 2 nm with a standard deviation of 0.5 nm. Finally, the spike height is on average 8 nm with a standard deviation of 4 nm. The optical microscope image of the PET/SiN/resist substrate with embedded Ag grids, and the SEM image of embedded Ag track, are shown in figure 7. The embedded structures produced with the optimized process settings and materials on PEN acceptor substrate show smooth topology suitable for integration into OPV devices. The peak height is well below 500 nm and the valley depth, RMS roughness and spike height are well below 50 nm. The embedding ratio of 97% is near maximum and is the result of the substrate deformation during the sintering process of the silver. Moreover, the variation within a product and between different products is small. The standard deviation is maximum 38 nm (variation of the peak height). The small variation indicates that the embedding of conductive structures can be performed repeatedly and reproducibly.
Using the optimized process settings and silver ink, embedded grids are produced on PET/SiN. The resist which is used for embedding on PEN substrate is replaced by another resist which better adheres to the PET/SiN substrate. It is anticipated that the produced embedded grids will have similar topology with respect to the embedded grids produced on PEN acceptor substrate. Photographs of the embedded structure on PET/SiN substrate and the complete OPV device are presented in figure 8. OPV devices are produced on both PEN and PET/SiN substrates using embedded grids produced with optimized process settings and materials. The thickness of highly conductive PEDOT:PSS (OrgaconTM , Agfa-Gevaert) of 100 nm, as well as the grid spacing of 2 mm, were optimized to provide for an optimal ratio of conductivity and transparency in order to gain maximum device performance [18, 21]. The optical transmission spectra of the PEN and PET/SIN foils covered with the resist material are shown in figure 9. The average optical transmittance of the PEDOT:PSS layer in the visible range is 93%, as is shown in figure 9. The optical transmission spectrum of 5
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Figure 8. Left side, photograph of embedded structures on PET/SiN. The outer dimensions of the embedded screen printed structures are 2.4 × 2.5 cm2 . The right side shows a detail of the OPV device with embedded structures on PET/SiN.
Figure 9. Optical transmission of the PEN and PET/SiN foils covered with resist, PEDOT:PSS layer and PET/SiN/resist/PEDOT:PSS foil.
Figure 10. JV curves of the OPV device with embedded structure on PET/SiN and the OPV device with ITO electrode.
the PET/SiN/resist foil with the PEDOT:PSS layer gives an average transmittance of 82% in the wavelength range of 450–600 nm (absorption maximum of P3HT) as is shown in figure 9. The area covered with grids remains completely non-transparent in the visible region. The grid coverage in the devices is 4.5%, which reduces the total transparency of the substrate/electrode by 4.5%. The measured JV characteristics of 2 × 2 cm2 ITO-free OPV devices with embedded grids produced on both types of substrate (PEN and PET/SiN) are identical. For comparison, a reference device with the same dimensions is produced on PET/SiN using an ITO electrode. The typical JV curves for both the ITO-based and ITO-free devices with embedded grids are presented in figure 10. The sheet resistance of the bottom electrode and photovoltaic performance parameters (the open circuit voltage (Voc ), the fill factor (FF) and the Power Conversion Efficiency (PCE)) of the respective devices are summarized in table 1. The ITO-based devices with an active area of 2 × 2 cm2 show an efficiency of only 1%. The ITO-free devices with embedded grids have an average efficiency of 2.15%, which is more than twice as high as the efficiency of ITO-based devices with the same active area.
The lower efficiency of the ITO-based devices can be explained by the higher resistance of the ITO electrode. A higher sheet resistance increases the series resistance, which in its turn decreases the fill factor, the Jsc and the efficiency. The strong dependence of the OPV device efficiency on the sheet resistance is depicted in figure 11 using results from previous and present experiments [17, 21]. The figure shows that the efficiency of the 2 × 2 cm2 devices decreases with increasing sheet resistance. The OPV devices of the present paper produced with embedded screen printed current collecting grids combined with PEDOT:PSS have the highest power conversion efficiency of 2.15% and the lowest sheet resistance of 0.21 / (the resistivity of the printed line is 5.12 × 10−8 m) for a grid surface coverage of 4.5%. The second highest efficiency is measured for devices produced with embedded screen printed current collecting grids combined with highly conductive PEDOT from [17]. The devices have an efficiency of 1.92% and a sheet resistance of 1 /. The devices with the inkjet printed current collecting grids have the third highest efficiency of 6
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Table 1. Characteristics of the OPV devices. Transparent electrode
Sheet resistance (/)
Voc (V)
Jsc (mA cm−2 )
FF
PCE (%)
ITO-substrate Embedded screen printed Ag-grid/PEDOT
60 0.21/500
0.49 0.53
6.96 8.00
0.30 0.51
1.02 2.15
well below the tolerable 500 nm and valley depths, RMS roughness and spike heights below a tolerable 50 nm are possible, enabling the successful integration of these foils into OPV devices. JV measurements of OPV devices with embedded structures on PET/SiN substrate show significantly higher PCE than identical flexible devices with ITO (1.02%) and inkjet printed silver (1.48%). This is mainly the result of the much lower sheet resistance of the embedded grid structure. The efficiency of 2 × 2 cm2 devices decreases with increasing sheet resistance. The lower sheet resistance of silver in comparison to inkjet printed silver and ITO (0.21 / versus 4.83 / and 60 / respectively) opens up the potential of producing large area OPV devices with greater process and design freedom. Furthermore, silver is more suited for flexible macroelectronics because of its higher thermo-mechanical robustness in comparison to ITO. The brittle behavior of ITO puts a limit on the amount of thermo-mechanical load it can withstand. Moreover, the brittle ITO does not allow for small bend radii. At relatively low loads ITO will degrade and crack. Silver however is less brittle. For this reason it is expected that silver will be able to withstand higher thermo-mechanical loads.
Figure 11. Power conversion efficiency of 2 × 2 cm2 OPV devices on plastic substrates versus sheet resistance of transparent electrode.
1.48% for a sheet resistance of 4.83 / (the resistivity of the printed lines is 2.4 × 10−7 m) [21]. The devices produced with the ITO transparent electrode of the present paper have an efficiency of 1.02% for a sheet resistance of 60 /. Finally, the devices produced with the PEDOT:PSS transparent electrode have the lowest efficiency of 0.71% and the highest sheet resistance of 200 / [21]. The influence of the sheet resistance on the device efficiency is less pronounced for small devices, however it becomes more pronounced when scaling up the active area of organic solar cells [25]. Increasing the active area is required to allow for reduction of the cost price. However, the allowable cell and module dimensions are restricted by the sheet resistance of the electrode. The low resistivity of the embedded screen printed current collecting grids allows us to scale up the cell dimensions. This is a significant advantage over the ITO electrode for which the cell dimension (maximum 0.5 cm2 on flexible substrate) is strongly limited by the high series resistance due to the higher sheet resistance of the electrode.
Acknowledgments The authors would like to acknowledge and thank the Dutch Ministry of Economic Affairs, NanoNextNL, the financial support of the European Community’s Seventh Framework Programme (FP7/2007–2013) under Grant No. 287818 of the X10D project and DuPont (UK) Limited gratefully.
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5. Conclusions R2R embedding of screen printed metal structures is a technology which allows the production of functional foils combining low sheet resistances and high optical transparencies with minimal surface topologies. After optimization of the process settings and materials, embedding ratios of up to 97% can be achieved with high reproducibility on both PEN and PET/SiN acceptor substrates. Peak heights 7
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