Letter pubs.acs.org/NanoLett
Quantum Dot Made in Metal Oxide Silicon-Nanowire Field Effect Transistor Working at Room Temperature. Romain Lavieville,†,‡ François Triozon,†,‡ Sylvain Barraud,†,‡ Andrea Corna,§,∥ Xavier Jehl,§,∥ Marc Sanquer,*,§,∥ Jing Li,⊥,# Antoine Abisset,⊥,# Ivan Duchemin,⊥,# and Yann-Michel Niquet⊥,# †
Université Grenoble Alpes, F-38000 Grenoble, France CEA, LETI MINATEC campus, F-38054 Grenoble, France § Université Grenoble Alpes, INAC-SPSMS, F-38000 Grenoble, France ∥ CEA, INAC-SPSMS, F-38054 Grenoble, France ⊥ Université Grenoble Alpes, INAC-SPMM, F-38000 Grenoble, France # CEA, INAC-SPMM, F-38054 Grenoble, France ‡
S Supporting Information *
ABSTRACT: We report the observation of an atomic like behavior from T = 4.2 K up to room temperature in n- and p-type Ω-gate silicon nanowire (NW) transistors. For that purpose, we modified the design of a NW transistor and introduced long spacers between the source/drain and the channel in order to separate the channel from the electrodes. The channel was made extremely small (3.4 nm in diameter with 10 nm gate length) with a thick gate oxide (7 nm) in order to enhance the Coulomb repulsion between carriers, which can be as large as 200 meV when surface roughness promotes charge confinement. Parasitic stochastic Coulomb blockade effect can be eliminated in our devices by choosing proper control voltages. Moreover, the quantum dot can be tuned so that the resonant current at T = 4.2 K exceeds that at room temperature.
KEYWORDS: Silicon nanowire, silicon single electron transistor, quantum dot, artificial atom
T
shall display the excellent features inherited from the CMOS fabrication: established technology with no use of an expensive electron beam lithography, standardization and mass production, steady improvement in materials and processes, etc. Here we present such an artificial atom transistor, tunable with a combination of top gate and backgate voltages, for which the atomic-like features can be tracked continuously from low to room temperature. This CMOS artificial atom exists in both n- and p-type transistors. The design combines small diameter channel (3.4 nm) and long (25 nm) spacers separating the gate (G) from the heavily doped source (S) and drain (D) electrodes, in order to enhance confinement and Coulomb interactions. Despite the very small size of these artificial atoms (a few nanometers), the fabrication is massively parallel. Although the process variability is large at this scale, several working samples have been already produced. We first discuss the design of the NW transistors. Top-down silicon NWs8 as well as chemical vapor deposition (CVD) grown silicon nanowires9,10 have both reached the 2−8 nm diameter range. These devices show strong transverse confine-
he quest for electronic circuits using single atoms and molecules took off with the rise of nanosciences. Atom switch,1 single atom contact,2 and single atom transistor3−7 are various examples of nanodevices where the electric current is driven through the atomic orbitals of a weak link in an elementary circuit. Despite proof of concept demonstrations, these objects still suffer from many drawbacks: they are very fragile and their interfacing to the macroscopic world is extremely challenging. Most of them can hardly be integrated into standard, scalable semiconductor processes and reveal their atomic properties only at low temperature. On the other hand, reliable silicon CMOS transistors become smaller and smaller. The most advanced design to date is the nanowire (NW) CMOS transistor that consists of an etched quasi-one-dimensional undoped silicon channel covered by a gate and connected to the heavily doped source and drain contacts. Nanowire transistors have better immunity to shortchannel effects than Fin-FET and planar transistors thanks to the very good electrostatic control of the channel by the gate. Because this NW transistor benefits from the maturity of silicon processing and technology, it is attractive to use it as a platform for a room temperature single artificial atom (AA) transistor, that is, a tiny channel where carriers are strongly confined in all 3 dimensions and controlled one-by-one by gates. Such AA © 2015 American Chemical Society
Received: December 15, 2014 Revised: April 17, 2015 Published: April 29, 2015 2958
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insulator (SOI) wafers with 145 nm thick buried oxide and 12 nm thick Si layer.18 The [110] oriented nanowires (NWs) are patterned on the silicon layer by a mesa isolation technique. They are defined by 193 nm deep-UV (DUV) lithography followed by a resist trimming process in order to reduce the NW width down to 10 nm. A 7 nm thick oxidation further reduces their diameter down to ∼3.4 nm and protects the wires for the rest of the fabrication. Then 1.9 nm HfSiON capped by 5 nm atomic layer deposition TiN and 50 nm poly-Si are deposited to form high-κ/metal gates. As for the active patterning, the same photoresist trimming was used to achieve gate lengths down to ∼10 nm. After gate etching, a SiN layer (thickness 25 nm) is deposited and etched to form a first offset spacer on the sidewalls of the gate. Eighteen nanometers thick Si raised source/drain (S/D) are then selectively grown at 750 °C, 20 Torr prior to a first S/D extension implantation (around 8 × 1025 m−3 dopants) and activation annealing. Then a second offset consisting of a tetraethyl orthosilicate (TEOS) liner and nitride layer is fabricated before a second S/D implantation (around 3× 1026 m−3 dopants), activation spike anneal, and silicidation (NiPtSi silicide) in order to achieve low contact resistances. Finally, tungsten contacts and standard Cu backend-of-the-line process are used. This integration scheme based on a CMOS process allows for an easier implementation of contacts, spacers, top and bottom gates, which are all crucial building blocks of a reliable artificial atom. Although room-temperature single electron transistors have already been reported in small silicon structures19−22 and have been constantly improved up to date,8,23 none of the previous demonstrations used standard CMOS integration and with the exception of ref 24 all of them were fabricated with e-beam lithography. Figure 1a shows a TEM image of the cross-section of a device while Figure 1b−ds shows structural models used for electrical simulations. The line-edge roughness of the patterns is critical at this scale and directly results from the initial roughness of the resist (see Figure S1 in the Supporting Information). Figure 1b-d shows therefore possible scenarios for the experimental data discussed below: a moderate surface roughness disorder (b) and a strong surface roughness defining a quantum dot either below the gate (c) or below the spacers (d). The potential landscape in these devices has been computed with a non-equilibrium Green’s functions (NEGF) solver in the nonparabolic two bands k·p (electrons) and three bands k·p (holes) approximations.29,30 Atomistic pointlike dopants have been added into the bulk source and drain extensions in order to achieve a realistic description of the contact to channel interface. Exchange-correlation effects are described with a local density approximation supplemented with a semiclassical model for the image charges self-energy corrections.31,32 Electron− phonon interactions and surface roughness (SR) disorder are taken into account. Although NEGF does not account for Coulomb blockade in the current, it gives a realistic description of the potential landscape in the device when there is an integer number of carriers in the channel. The charging energies can therefore be computed from the eigenstates of the channel in the NEGF potential. Details about the methodology can be found in the Supporting Information. First, samples with drain current Ids > 10−7 A at drain voltage Vd = 40 mV and gate voltage |Vg| = 1 V above the threshold show monotonic Ids−Vg characteristics at room temperature, while most of them behave as robust single electron or hole
ment thanks to the small cross-section of the NW. Isolation from the S-D contacts by longitudinal confinement is then the key to reach the AA regime where the interplay between Coulomb blockade and quantum confinement regulates the addition spectrum. For CVD grown silicon NWs, the S-D contacts are usually Schottky barriers between metallic electrodes and the nanowire.10,11 Here instead of Schottky contacts we used highly doped silicon contacts (source and drain) and decoupled them from the channel by introducing 25 nm long intrinsic silicon nanowire spacers (nonoverlapped S-G geometry). These spacers play the role of long linker molecules in single atom transistors.3 The transmission through the spacers can also be controlled by the substrate bias. A quantum dot is formed below the gate by the electric field, and it accumulates electrons (or holes).12,13 Overall, these spacers present several advantages. First, they preserve the electrostatic control over the channel, and therefore the AA tunability, even at short gate lengths (10 nm). Second, they limit the screening of the electron interactions by the S-D electrodes. Third, they prevent the lateral diffusion of source and drain dopants in the channel. Fourth, it has been shown that long and thin resistors are more efficient than thin tunnel barriers to prevent parasitic cotunneling in metallic single electron transistors.14 This is reminiscent of using quantum point contacts15 or resistive circuits16 in order to observe charging effects and Coulomb blockade.17 Specifically, our AAs are made in thin (∼3.4 nm diameter) etched nanowires (see Figure 1). An omega-shaped gate (Ωgate) sets the transverse electric field locally. These very small Ω-gate nanowire transistors are fabricated at very large scale via a CMOS route developed on conventional (100) silicon-on-
Figure 1. Geometry and simulations. (a) TEM image showing the cross section of the 3.4 nm diameter silicon nanowire, the 7 nm thick SiO2 gate oxide, the 1.9 nm HfSiON, and the 5 nm ALD TiN/ polysilicon gate. (b-d) Models used for the simulations. (b) An n-type device with moderate surface roughness (wire diameter 3.4 nm; surface roughness rms Δ = 0.25 nm). Silicon is in red, SiO2 in green, HfO2 (HfSiON) in blue, TiN gate in gray, and Si3N4 otherwise. The silicon substrate is not represented. The white dots are arsenic donors in the source and drain. This device has a charging energy around 90 meV. (c) An n-type device with strong surface roughness secluding a 4 nm long dot under the gate. (d) A p-type device with strong surface roughness secluding a 7 nm long dot under the source spacer, and a very long, ∼30 nm long dot under the gate and drain spacer. 2959
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coupling between the dot and the top Ω-gate. One of the dots has a charging energy U ≃ 60 meV and a lever arm parameter αg ≃ 0.47. This dot is presumably located near the top gate.12,13 The other dot, the AA, has a larger charging energy U ≃ 140 meV and a smaller αg,AA ≃ 0.34. It is likely located under a spacer and is induced by enhanced surface roughness. In order to validate this scenario, we have calculated the charging energies and lever arm parameters of quantum dots with different sizes and positions along the nanowire. Figure 3d shows the LDoS computed in the device of Figure 1d, which is the only geometry found that reproduces the overall experimental picture. In this device, we have introduced two constrictions under the source spacer that delimit a 4 nm diameter and 7 nm long dot (the AA), while a much longer dot extends from the gate to the drain spacer. The position and size of this 7 nm dot have been chosen to match the experimental charging energy and lever arm parameter of the AA. The other long dot results from random, Gaussian surface roughness with rms Δ = 0.25 nm. Its charging energy is U ≃ 45 meV, and its lever arm parameter is greater than 0.6, which suggests that the experimental accumulation dot is a little shorter on the gate side. There is one well-defined resonance in the AA (the excited state being almost 50 meV below), and a few broader resonances in the long dot. The long dot would typically contain around 4−5 holes (injected from the drain) when the ground state energy level in the AA comes in resonance with the source. We now turn to a n-MOS device with the same nominal geometry but a different, single dot behavior. The linear S-D conductance of this device is plotted in Figure 4a at various temperatures between 4.2 and 300 K. Here five resonances can be identified at Vg,i ≈ 0.7, 1.0, 1.2, 1.37, and 1.45 V (i = 1−5). The effect of the back gate (see Figure 4b) is qualitatively different from that in the p-type sample: the resonances are simply shifted in gate voltage as the substrate bias is varied but they are not suppressed. A modulation of the amplitude of Ids is also observed, which can be due to the ionization of a coupled impurity.25 Yet, lines of finite conductance in the Ids versus (Vg, Vb) plot are characteristic of the transport through a single AA, and not of two dots in series (which would lead to discrete triple points as in Figure 3b). Furthermore, the AA resonances in the n-type sample have a large αg = 0.75 (determined from the Ids(Vg, Vd) plot in Figure 4c). Therefore, we conclude that this AA is below or very near the top gate, as in Figure 1c. The first resonance at Vg,1 = 0.7 V carries a small resonant current at 300 K and no more detectable current below T = 200 K. Thus, this first electron state is weakly tunnel coupled to the source and to the drain. At room temperature, thermal activation of carriers increases the transmission through the nanowire under the spacers, which remains compatible with Coulomb blockade as shown in ref 26. The resonances at larger Vg become increasingly sharper as the temperature decreases. The peaks at Vg = 1.0, 1.2, and 1.37 V have similar width at different temperatures but the value of the conductance Gres i at resonance as well as its temperature dependence varies from peak to peak. Below T = 30 K, Gres i is given by
transistors at lower temperatures. This level of current is consistent with the simulations: with no or weak SR (rms Δ = 0.25 nm), the calculated current at room temperature exceeds 10−7 A for Vd = 40 mV and |Vg| = 1 V above the threshold in both n- and p-type devices (see Figure 2). As a matter of fact,
Figure 2. Calculated room-temperature I(V) characteristics of the rough n-type device of Figure 1b (surface roughness rms Δ = 0.25 nm), and of the n-type device with a dot of Figure 1c, at back gate voltage Vb = 0 V. The larger symbols are the points (Vg,1, Ids,1) where there is on average one electron in the channel. The calculated currents are compared with experimental data on two typical devices not showing Coulomb blockade at T = 300 K (dash-dotted blue lines) and with the I(V) characteristics of the device of Figure 4 (dotted red line). Although NEGF does not reproduce the Coulomb blockade peaks measured in that device, it is expected to give the correct order of magnitude of the current near the threshold Vg,1.
the charging energies computed in those devices range from 50 to about 100 meV, not large enough to observe strong modulations of the current up to room temperature. The calculated current can, however, decrease by orders of magnitude when strong surface roughness leads to the formation of narrow constrictions along the NW (as in Figure 1c,d). As an experimental evidence, we show in Figure 3a the linear Ids−Vg characteristics measured at various temperatures in a p-MOS device with a smaller drain current. A broad resonance can be resolved at 300 K and splits in two sharp resonances at T = 4.2 K. In Figure 3a, the back gate voltage Vb has been adjusted in order to recover a high resonant current at low temperature; otherwise, the current decreases by orders of magnitude between T = 77 K and T = 4.2 K. Such a decrease of the current is also visible in refs 8 and 22 where no back gate bias was applied. The splitting of the resonance and decrease of the current suggest the presence of two dots in series. The detuning (level misalignment) between the two dots results in a suppression of current at low temperature, unless the levels are properly realigned by the back gate electric field. This hypothesis is confirmed by the Ids(Vg, Vb) plot on Figure 3b, where the current appears in a sequence of coupled triple points. The charging energy U of these dots and lever arm parameter to the gate αg = [(δΦ)/(δ Vg)] (Φ being the potential in the dot) can be determined from the Ids(Vg, Vd) plots (see Figure 3c and Figures S2 and S3 in the Supporting Information). The larger is αg, the stronger is the electrostatic
Gres(Vg) ≈
ΓΓ e2 s d 4kBT Γs + Γd
(1)
where Γs(d) is the tunneling rate to the source (drain), and the full width at half-maximum of the resonance is given by 3.52 [(kBT)/(eαg)] (thermally broadened resonant tunneling 2960
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Figure 3. Ids(Vg) characteristics and Coulomb oscillations for a p-type sample. (a) Temperature dependence of Ids(Vg) (Vd = 1 mV). The resonance near Vg = −1.3 V at T = 300 K splits in two resonances at T = 4.2 K. The back gate voltage Vb = −30 V is adjusted in order to recover a high resonant current level at T = 4.2 K. (b) Ids(Vg, Vb) at T = 4.2 K and Vd = 0.15 mV around the split resonance. The current appears at a series of coupled triple points that characterize double dots in series. One dot with a charging energy ≃60 meV is accumulated below the gate and modulates the current through the artificial atom (AA) under the spacers with a charging energy of ≃140 meV. At T = 300 K the accumulation dot does not block the current and a single resonance due to the AA is observed (see text). (c) G(Vg, Vd) at T = 4.2 K along the dashed line of panel b. A charging energy of 60 meV can be deduced for the accumulation dot. The sawtooth pattern is due to the addition of one hole in the AA.25,28 (d) Simulation of the confinement potential and local density of states (LDoS) in a p-type sample with an ∼7 nm long dot under the source spacer (the AA), and an ∼30 nm long dot under the gate and drain spacer. The red line is the potential landscape in the channel, while the horizontal, black dashed lines are the Fermi levels in the source (μs) and drain (μd). The resonances in the channel give the energy and spatial extension of the quasiparticle states. There is one well-defined quasiparticle state in the AA.
five) electrons in the channel is 230 (respectively 150, 130, 60) meV taking into account the lever arm parameter αg = 0.75. Simulations confirm this scenario. Figure 4d shows the LDoS computed in the n-type device of Figure 1c, near the gate voltage where the first electron tunnels into the dot. The calculation was performed for T = 150 K because at lower temperatures some of the resonances become too narrow to be accurately resolved by the NEGF solver. There is only one 4 nm long dot located near the center of the channel. The dot is isolated from the bulk source and drain by lateral confinement within the spacers and by the dielectric mismatch between the nanowire and the embedding oxides (image charge self-energy corrections). Indeed, both raise the conduction band of the wire well above the Fermi level of the contacts (the barrier is up to 300 meV high). Three well-resolved energy levels can be
regime, see Figure S4 in the Supporting Information for the detailed analysis near Vg = 1.0 V). For i ≥ 3 the temperature dependence of G ires is nonmonotonic between T = 4.2 K and T = 30 K, pointing out the contribution of a nearby, thermally accessible excited state to the resonant conductance, or to the temperature dependence of the tunneling rates. At higher temperature (200−300 K) a quasi continuum of states becomes accessible and contributes to the drain current at large Vg. Equivalently the tunnel rates strongly increase with temperature. This is not the case for the resonances near Vg,2 = 1.0 V and Vg,3 = 1.2 V, so that the conductance is larger by several orders of magnitude at 4.2 K than at 300 K for these peaks. The addition energy of the one-to-two (respectively two-to-three, three-to-four, four-to2961
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Figure 4. Conductance characteristics and Coulomb oscillations for a n-type sample. (a) Temperature dependence of G(Vg) = [(δIds)/(δVd)] at Vb = 40 V. A first resonance appears at 300 K near Vg = 0.7 V. Only four resonances are identified at T = 4.2 K in this Vg range. (b) Ids(Vg, Vb) at T = 4.2 K around the second resonance. No triple point, as in Figure 3, but a single line appears in the Ids(Vg, Vb) plot, which is indicative of a single dot. (c) Ids(Vg, Vd) at T = 4.2 K around the second resonance. The first excited state (dashed-dotted line) appears 5 meV above the ground state for the resonance near Vg = 1 V. The lever arm parameter is αg = 0.75. The large αg confirms that the AA is centered under the top gate. (d) Simulation of the confinement potential and LDoS in a n-type sample with a ∼4 nm long dot (the AA) under the gate. The red line is the potential landscape in the channel, while the horizontal, black dashed lines are the Fermi levels in the source (μs) and drain (μd). Three quasiparticle states can be resolved in the dot under the gate.
voltages, in agreement with experiment. Increasing the gate voltage lowers the height and decreases the thickness of the barrier under the spacers. This results in a strong enhancement of the current and reduction of the charging energy, as observed experimentally. The orbital excitations in the channel always lie more than 15 meV above the ground state even in the absence of SR. Yet transport spectroscopy at finite Vd reveals a single excited state at Vd ≃ 5 meV as a plateau of current for both polarities (see Figure 4c). The separation between the ground and the first excited state (5 meV) is therefore much smaller than the calculated splitting between the orbital excitations. Consequently, the first excited state observed in Figure 4c is most likely the valley orbit splitted ground orbital level in the AA. Indeed, the calculated valley-orbit splitting of the ground state
identified inside the dot. The calculated addition energy for the second electron is U = 196 meV. The dot is well coupled to the gate, the lever arm parameter αg = 0.83 being close to the experimental one (0.75). The calculated room-temperature characteristics of this device is plotted in Figure 2. The threshold voltage Vg,1 (defined here as the gate voltage where there is one electron in the channel), and the room-temperature current Ids,1=Ids(Vg,1, Vd = 40 mV) at that voltage are also reported on this figure with a larger symbol. Although NEGF does not reproduce Coulomb blockade in the current, Ids,1 ∝ ΓsΓd/(Γs + Γd) shall be representative of the tunneling rates Γs and Γd with the source and drain. With respect to the weakly disordered device of Figure 1b, the calculated current decreases by orders of magnitude due to the large tunnel barriers raised by the constrictions. Also, the threshold Vg,1 is shifted to larger gate 2962
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TOLOP No 318397 and SiSPIN No 323841. The NEGF calculations were run at the TGCC/Curie machine using allocations from PRACE and GENCI.
resonance is strongly dependent on the shape of the dot and can range from a few to a few tens of meV. Experimental data for other n- and p- type devices are given in the Supporting Information (Figure S5). In our samples, a very good transmission through the 25 nm long spacers can be achieved for any temperature by adjusting the back gate voltage. The fact that the resonant current at T = 4.2 K is comparable to the current measured at 300 K proves that any parasitic stochastic Coulomb blockade effect can be eliminated in our devices by a proper choice of the control voltages. In contrast to our results for the n-type sample, Shin et al.27 have observed current resonances at room temperature that, however, split into multiple peaks at low temperature. Furthermore, the current at the resonances decreases as the temperature is reduced. The regular pattern of split peaks and their drain voltage dependence can be attributed (a) to the effect of valley splitting of orbital levels,8 (b) to a possible parasitic effect due to granularity in the gate stack,28 or (c) to the appearance of multiple dots in series (as in the p-type sample case). In summary, we have fabricated 3.4 nm diameter nanowire Ω-gate MOSFETs with deliberately long offset spacers (25 nm) and short gate length (10 nm) using DUV lithography and standard 300 mm CMOS process. Such a design isolates the channel from the source and the drain and enhances Coulomb interactions within the channel. As a result, these devices show robust addition spectra characteristic of artificial atoms. The shape and location of these artificial atoms depend on line edge roughness along the nanowire but the most prominent source of disorder, that is, the presence of few cavities in series can be managed thanks to the control by both front and back gate voltages. The addition energy can reach up to 230 meV depending on the surface roughness. The orbital excited state is several 10 meV above the ground state and the measured valley orbit splitting is around 5 meV in n-type devices, a large value for a quantum dot.33 These devices bridge conventional MOSFETS with SETs, and show that Coulomb interactions within the channel are bound to play an increasingly important role in the physics and design of the next generations of silicon devices. Finally, the on-chip integration of these artificial atoms with CMOS peripheral modules controlling their operation is very easy, because large size transistors are made with the very same CMOS technology.23
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ASSOCIATED CONTENT
S Supporting Information *
Additional experimental data (surface roughness, double dot stability diagram, temperature dependence, and Coulomb diamonds at room temperature) and modeling details (methodology and additional results). The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/nl504806s.
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REFERENCES
AUTHOR INFORMATION
Corresponding Author
*E-mail: [email protected]. Phone: +33(0)4 38 78 43 67. Fax: +33(0)4 38 78 50 96. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors acknowledge A. Orlov for a careful reading of the manuscript and financial support from the EU under Projects 2963
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Quantum Dot Made in Metal Oxide Silicon-Nanowire Field Effect Transistor Working at Room Temperature. Romain Lavieville,†,‡ François Triozon,†,‡ Sylvain Barraud,†,‡ Andrea Corna,§,∥ Xavier Jehl,§,∥ Marc Sanquer,*,§,∥ Jing Li,⊥,# Antoine Abisset,⊥,# Ivan Duchemin,⊥,# and Yann-Michel Niquet⊥,# †
Université Grenoble Alpes, F-38000 Grenoble, France CEA, LETI MINATEC campus, F-38054 Grenoble, France § Université Grenoble Alpes, INAC-SPSMS, F-38000 Grenoble, France ∥ CEA, INAC-SPSMS, F-38054 Grenoble, France ⊥ Université Grenoble Alpes, INAC-SPMM, F-38000 Grenoble, France # CEA, INAC-SPMM, F-38054 Grenoble, France ‡
S Supporting Information *
ABSTRACT: We report the observation of an atomic like behavior from T = 4.2 K up to room temperature in n- and p-type Ω-gate silicon nanowire (NW) transistors. For that purpose, we modified the design of a NW transistor and introduced long spacers between the source/drain and the channel in order to separate the channel from the electrodes. The channel was made extremely small (3.4 nm in diameter with 10 nm gate length) with a thick gate oxide (7 nm) in order to enhance the Coulomb repulsion between carriers, which can be as large as 200 meV when surface roughness promotes charge confinement. Parasitic stochastic Coulomb blockade effect can be eliminated in our devices by choosing proper control voltages. Moreover, the quantum dot can be tuned so that the resonant current at T = 4.2 K exceeds that at room temperature.
KEYWORDS: Silicon nanowire, silicon single electron transistor, quantum dot, artificial atom
T
shall display the excellent features inherited from the CMOS fabrication: established technology with no use of an expensive electron beam lithography, standardization and mass production, steady improvement in materials and processes, etc. Here we present such an artificial atom transistor, tunable with a combination of top gate and backgate voltages, for which the atomic-like features can be tracked continuously from low to room temperature. This CMOS artificial atom exists in both n- and p-type transistors. The design combines small diameter channel (3.4 nm) and long (25 nm) spacers separating the gate (G) from the heavily doped source (S) and drain (D) electrodes, in order to enhance confinement and Coulomb interactions. Despite the very small size of these artificial atoms (a few nanometers), the fabrication is massively parallel. Although the process variability is large at this scale, several working samples have been already produced. We first discuss the design of the NW transistors. Top-down silicon NWs8 as well as chemical vapor deposition (CVD) grown silicon nanowires9,10 have both reached the 2−8 nm diameter range. These devices show strong transverse confine-
he quest for electronic circuits using single atoms and molecules took off with the rise of nanosciences. Atom switch,1 single atom contact,2 and single atom transistor3−7 are various examples of nanodevices where the electric current is driven through the atomic orbitals of a weak link in an elementary circuit. Despite proof of concept demonstrations, these objects still suffer from many drawbacks: they are very fragile and their interfacing to the macroscopic world is extremely challenging. Most of them can hardly be integrated into standard, scalable semiconductor processes and reveal their atomic properties only at low temperature. On the other hand, reliable silicon CMOS transistors become smaller and smaller. The most advanced design to date is the nanowire (NW) CMOS transistor that consists of an etched quasi-one-dimensional undoped silicon channel covered by a gate and connected to the heavily doped source and drain contacts. Nanowire transistors have better immunity to shortchannel effects than Fin-FET and planar transistors thanks to the very good electrostatic control of the channel by the gate. Because this NW transistor benefits from the maturity of silicon processing and technology, it is attractive to use it as a platform for a room temperature single artificial atom (AA) transistor, that is, a tiny channel where carriers are strongly confined in all 3 dimensions and controlled one-by-one by gates. Such AA © 2015 American Chemical Society
Received: December 15, 2014 Revised: April 17, 2015 Published: April 29, 2015 2958
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insulator (SOI) wafers with 145 nm thick buried oxide and 12 nm thick Si layer.18 The [110] oriented nanowires (NWs) are patterned on the silicon layer by a mesa isolation technique. They are defined by 193 nm deep-UV (DUV) lithography followed by a resist trimming process in order to reduce the NW width down to 10 nm. A 7 nm thick oxidation further reduces their diameter down to ∼3.4 nm and protects the wires for the rest of the fabrication. Then 1.9 nm HfSiON capped by 5 nm atomic layer deposition TiN and 50 nm poly-Si are deposited to form high-κ/metal gates. As for the active patterning, the same photoresist trimming was used to achieve gate lengths down to ∼10 nm. After gate etching, a SiN layer (thickness 25 nm) is deposited and etched to form a first offset spacer on the sidewalls of the gate. Eighteen nanometers thick Si raised source/drain (S/D) are then selectively grown at 750 °C, 20 Torr prior to a first S/D extension implantation (around 8 × 1025 m−3 dopants) and activation annealing. Then a second offset consisting of a tetraethyl orthosilicate (TEOS) liner and nitride layer is fabricated before a second S/D implantation (around 3× 1026 m−3 dopants), activation spike anneal, and silicidation (NiPtSi silicide) in order to achieve low contact resistances. Finally, tungsten contacts and standard Cu backend-of-the-line process are used. This integration scheme based on a CMOS process allows for an easier implementation of contacts, spacers, top and bottom gates, which are all crucial building blocks of a reliable artificial atom. Although room-temperature single electron transistors have already been reported in small silicon structures19−22 and have been constantly improved up to date,8,23 none of the previous demonstrations used standard CMOS integration and with the exception of ref 24 all of them were fabricated with e-beam lithography. Figure 1a shows a TEM image of the cross-section of a device while Figure 1b−ds shows structural models used for electrical simulations. The line-edge roughness of the patterns is critical at this scale and directly results from the initial roughness of the resist (see Figure S1 in the Supporting Information). Figure 1b-d shows therefore possible scenarios for the experimental data discussed below: a moderate surface roughness disorder (b) and a strong surface roughness defining a quantum dot either below the gate (c) or below the spacers (d). The potential landscape in these devices has been computed with a non-equilibrium Green’s functions (NEGF) solver in the nonparabolic two bands k·p (electrons) and three bands k·p (holes) approximations.29,30 Atomistic pointlike dopants have been added into the bulk source and drain extensions in order to achieve a realistic description of the contact to channel interface. Exchange-correlation effects are described with a local density approximation supplemented with a semiclassical model for the image charges self-energy corrections.31,32 Electron− phonon interactions and surface roughness (SR) disorder are taken into account. Although NEGF does not account for Coulomb blockade in the current, it gives a realistic description of the potential landscape in the device when there is an integer number of carriers in the channel. The charging energies can therefore be computed from the eigenstates of the channel in the NEGF potential. Details about the methodology can be found in the Supporting Information. First, samples with drain current Ids > 10−7 A at drain voltage Vd = 40 mV and gate voltage |Vg| = 1 V above the threshold show monotonic Ids−Vg characteristics at room temperature, while most of them behave as robust single electron or hole
ment thanks to the small cross-section of the NW. Isolation from the S-D contacts by longitudinal confinement is then the key to reach the AA regime where the interplay between Coulomb blockade and quantum confinement regulates the addition spectrum. For CVD grown silicon NWs, the S-D contacts are usually Schottky barriers between metallic electrodes and the nanowire.10,11 Here instead of Schottky contacts we used highly doped silicon contacts (source and drain) and decoupled them from the channel by introducing 25 nm long intrinsic silicon nanowire spacers (nonoverlapped S-G geometry). These spacers play the role of long linker molecules in single atom transistors.3 The transmission through the spacers can also be controlled by the substrate bias. A quantum dot is formed below the gate by the electric field, and it accumulates electrons (or holes).12,13 Overall, these spacers present several advantages. First, they preserve the electrostatic control over the channel, and therefore the AA tunability, even at short gate lengths (10 nm). Second, they limit the screening of the electron interactions by the S-D electrodes. Third, they prevent the lateral diffusion of source and drain dopants in the channel. Fourth, it has been shown that long and thin resistors are more efficient than thin tunnel barriers to prevent parasitic cotunneling in metallic single electron transistors.14 This is reminiscent of using quantum point contacts15 or resistive circuits16 in order to observe charging effects and Coulomb blockade.17 Specifically, our AAs are made in thin (∼3.4 nm diameter) etched nanowires (see Figure 1). An omega-shaped gate (Ωgate) sets the transverse electric field locally. These very small Ω-gate nanowire transistors are fabricated at very large scale via a CMOS route developed on conventional (100) silicon-on-
Figure 1. Geometry and simulations. (a) TEM image showing the cross section of the 3.4 nm diameter silicon nanowire, the 7 nm thick SiO2 gate oxide, the 1.9 nm HfSiON, and the 5 nm ALD TiN/ polysilicon gate. (b-d) Models used for the simulations. (b) An n-type device with moderate surface roughness (wire diameter 3.4 nm; surface roughness rms Δ = 0.25 nm). Silicon is in red, SiO2 in green, HfO2 (HfSiON) in blue, TiN gate in gray, and Si3N4 otherwise. The silicon substrate is not represented. The white dots are arsenic donors in the source and drain. This device has a charging energy around 90 meV. (c) An n-type device with strong surface roughness secluding a 4 nm long dot under the gate. (d) A p-type device with strong surface roughness secluding a 7 nm long dot under the source spacer, and a very long, ∼30 nm long dot under the gate and drain spacer. 2959
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coupling between the dot and the top Ω-gate. One of the dots has a charging energy U ≃ 60 meV and a lever arm parameter αg ≃ 0.47. This dot is presumably located near the top gate.12,13 The other dot, the AA, has a larger charging energy U ≃ 140 meV and a smaller αg,AA ≃ 0.34. It is likely located under a spacer and is induced by enhanced surface roughness. In order to validate this scenario, we have calculated the charging energies and lever arm parameters of quantum dots with different sizes and positions along the nanowire. Figure 3d shows the LDoS computed in the device of Figure 1d, which is the only geometry found that reproduces the overall experimental picture. In this device, we have introduced two constrictions under the source spacer that delimit a 4 nm diameter and 7 nm long dot (the AA), while a much longer dot extends from the gate to the drain spacer. The position and size of this 7 nm dot have been chosen to match the experimental charging energy and lever arm parameter of the AA. The other long dot results from random, Gaussian surface roughness with rms Δ = 0.25 nm. Its charging energy is U ≃ 45 meV, and its lever arm parameter is greater than 0.6, which suggests that the experimental accumulation dot is a little shorter on the gate side. There is one well-defined resonance in the AA (the excited state being almost 50 meV below), and a few broader resonances in the long dot. The long dot would typically contain around 4−5 holes (injected from the drain) when the ground state energy level in the AA comes in resonance with the source. We now turn to a n-MOS device with the same nominal geometry but a different, single dot behavior. The linear S-D conductance of this device is plotted in Figure 4a at various temperatures between 4.2 and 300 K. Here five resonances can be identified at Vg,i ≈ 0.7, 1.0, 1.2, 1.37, and 1.45 V (i = 1−5). The effect of the back gate (see Figure 4b) is qualitatively different from that in the p-type sample: the resonances are simply shifted in gate voltage as the substrate bias is varied but they are not suppressed. A modulation of the amplitude of Ids is also observed, which can be due to the ionization of a coupled impurity.25 Yet, lines of finite conductance in the Ids versus (Vg, Vb) plot are characteristic of the transport through a single AA, and not of two dots in series (which would lead to discrete triple points as in Figure 3b). Furthermore, the AA resonances in the n-type sample have a large αg = 0.75 (determined from the Ids(Vg, Vd) plot in Figure 4c). Therefore, we conclude that this AA is below or very near the top gate, as in Figure 1c. The first resonance at Vg,1 = 0.7 V carries a small resonant current at 300 K and no more detectable current below T = 200 K. Thus, this first electron state is weakly tunnel coupled to the source and to the drain. At room temperature, thermal activation of carriers increases the transmission through the nanowire under the spacers, which remains compatible with Coulomb blockade as shown in ref 26. The resonances at larger Vg become increasingly sharper as the temperature decreases. The peaks at Vg = 1.0, 1.2, and 1.37 V have similar width at different temperatures but the value of the conductance Gres i at resonance as well as its temperature dependence varies from peak to peak. Below T = 30 K, Gres i is given by
transistors at lower temperatures. This level of current is consistent with the simulations: with no or weak SR (rms Δ = 0.25 nm), the calculated current at room temperature exceeds 10−7 A for Vd = 40 mV and |Vg| = 1 V above the threshold in both n- and p-type devices (see Figure 2). As a matter of fact,
Figure 2. Calculated room-temperature I(V) characteristics of the rough n-type device of Figure 1b (surface roughness rms Δ = 0.25 nm), and of the n-type device with a dot of Figure 1c, at back gate voltage Vb = 0 V. The larger symbols are the points (Vg,1, Ids,1) where there is on average one electron in the channel. The calculated currents are compared with experimental data on two typical devices not showing Coulomb blockade at T = 300 K (dash-dotted blue lines) and with the I(V) characteristics of the device of Figure 4 (dotted red line). Although NEGF does not reproduce the Coulomb blockade peaks measured in that device, it is expected to give the correct order of magnitude of the current near the threshold Vg,1.
the charging energies computed in those devices range from 50 to about 100 meV, not large enough to observe strong modulations of the current up to room temperature. The calculated current can, however, decrease by orders of magnitude when strong surface roughness leads to the formation of narrow constrictions along the NW (as in Figure 1c,d). As an experimental evidence, we show in Figure 3a the linear Ids−Vg characteristics measured at various temperatures in a p-MOS device with a smaller drain current. A broad resonance can be resolved at 300 K and splits in two sharp resonances at T = 4.2 K. In Figure 3a, the back gate voltage Vb has been adjusted in order to recover a high resonant current at low temperature; otherwise, the current decreases by orders of magnitude between T = 77 K and T = 4.2 K. Such a decrease of the current is also visible in refs 8 and 22 where no back gate bias was applied. The splitting of the resonance and decrease of the current suggest the presence of two dots in series. The detuning (level misalignment) between the two dots results in a suppression of current at low temperature, unless the levels are properly realigned by the back gate electric field. This hypothesis is confirmed by the Ids(Vg, Vb) plot on Figure 3b, where the current appears in a sequence of coupled triple points. The charging energy U of these dots and lever arm parameter to the gate αg = [(δΦ)/(δ Vg)] (Φ being the potential in the dot) can be determined from the Ids(Vg, Vd) plots (see Figure 3c and Figures S2 and S3 in the Supporting Information). The larger is αg, the stronger is the electrostatic
Gres(Vg) ≈
ΓΓ e2 s d 4kBT Γs + Γd
(1)
where Γs(d) is the tunneling rate to the source (drain), and the full width at half-maximum of the resonance is given by 3.52 [(kBT)/(eαg)] (thermally broadened resonant tunneling 2960
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Figure 3. Ids(Vg) characteristics and Coulomb oscillations for a p-type sample. (a) Temperature dependence of Ids(Vg) (Vd = 1 mV). The resonance near Vg = −1.3 V at T = 300 K splits in two resonances at T = 4.2 K. The back gate voltage Vb = −30 V is adjusted in order to recover a high resonant current level at T = 4.2 K. (b) Ids(Vg, Vb) at T = 4.2 K and Vd = 0.15 mV around the split resonance. The current appears at a series of coupled triple points that characterize double dots in series. One dot with a charging energy ≃60 meV is accumulated below the gate and modulates the current through the artificial atom (AA) under the spacers with a charging energy of ≃140 meV. At T = 300 K the accumulation dot does not block the current and a single resonance due to the AA is observed (see text). (c) G(Vg, Vd) at T = 4.2 K along the dashed line of panel b. A charging energy of 60 meV can be deduced for the accumulation dot. The sawtooth pattern is due to the addition of one hole in the AA.25,28 (d) Simulation of the confinement potential and local density of states (LDoS) in a p-type sample with an ∼7 nm long dot under the source spacer (the AA), and an ∼30 nm long dot under the gate and drain spacer. The red line is the potential landscape in the channel, while the horizontal, black dashed lines are the Fermi levels in the source (μs) and drain (μd). The resonances in the channel give the energy and spatial extension of the quasiparticle states. There is one well-defined quasiparticle state in the AA.
five) electrons in the channel is 230 (respectively 150, 130, 60) meV taking into account the lever arm parameter αg = 0.75. Simulations confirm this scenario. Figure 4d shows the LDoS computed in the n-type device of Figure 1c, near the gate voltage where the first electron tunnels into the dot. The calculation was performed for T = 150 K because at lower temperatures some of the resonances become too narrow to be accurately resolved by the NEGF solver. There is only one 4 nm long dot located near the center of the channel. The dot is isolated from the bulk source and drain by lateral confinement within the spacers and by the dielectric mismatch between the nanowire and the embedding oxides (image charge self-energy corrections). Indeed, both raise the conduction band of the wire well above the Fermi level of the contacts (the barrier is up to 300 meV high). Three well-resolved energy levels can be
regime, see Figure S4 in the Supporting Information for the detailed analysis near Vg = 1.0 V). For i ≥ 3 the temperature dependence of G ires is nonmonotonic between T = 4.2 K and T = 30 K, pointing out the contribution of a nearby, thermally accessible excited state to the resonant conductance, or to the temperature dependence of the tunneling rates. At higher temperature (200−300 K) a quasi continuum of states becomes accessible and contributes to the drain current at large Vg. Equivalently the tunnel rates strongly increase with temperature. This is not the case for the resonances near Vg,2 = 1.0 V and Vg,3 = 1.2 V, so that the conductance is larger by several orders of magnitude at 4.2 K than at 300 K for these peaks. The addition energy of the one-to-two (respectively two-to-three, three-to-four, four-to2961
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Figure 4. Conductance characteristics and Coulomb oscillations for a n-type sample. (a) Temperature dependence of G(Vg) = [(δIds)/(δVd)] at Vb = 40 V. A first resonance appears at 300 K near Vg = 0.7 V. Only four resonances are identified at T = 4.2 K in this Vg range. (b) Ids(Vg, Vb) at T = 4.2 K around the second resonance. No triple point, as in Figure 3, but a single line appears in the Ids(Vg, Vb) plot, which is indicative of a single dot. (c) Ids(Vg, Vd) at T = 4.2 K around the second resonance. The first excited state (dashed-dotted line) appears 5 meV above the ground state for the resonance near Vg = 1 V. The lever arm parameter is αg = 0.75. The large αg confirms that the AA is centered under the top gate. (d) Simulation of the confinement potential and LDoS in a n-type sample with a ∼4 nm long dot (the AA) under the gate. The red line is the potential landscape in the channel, while the horizontal, black dashed lines are the Fermi levels in the source (μs) and drain (μd). Three quasiparticle states can be resolved in the dot under the gate.
voltages, in agreement with experiment. Increasing the gate voltage lowers the height and decreases the thickness of the barrier under the spacers. This results in a strong enhancement of the current and reduction of the charging energy, as observed experimentally. The orbital excitations in the channel always lie more than 15 meV above the ground state even in the absence of SR. Yet transport spectroscopy at finite Vd reveals a single excited state at Vd ≃ 5 meV as a plateau of current for both polarities (see Figure 4c). The separation between the ground and the first excited state (5 meV) is therefore much smaller than the calculated splitting between the orbital excitations. Consequently, the first excited state observed in Figure 4c is most likely the valley orbit splitted ground orbital level in the AA. Indeed, the calculated valley-orbit splitting of the ground state
identified inside the dot. The calculated addition energy for the second electron is U = 196 meV. The dot is well coupled to the gate, the lever arm parameter αg = 0.83 being close to the experimental one (0.75). The calculated room-temperature characteristics of this device is plotted in Figure 2. The threshold voltage Vg,1 (defined here as the gate voltage where there is one electron in the channel), and the room-temperature current Ids,1=Ids(Vg,1, Vd = 40 mV) at that voltage are also reported on this figure with a larger symbol. Although NEGF does not reproduce Coulomb blockade in the current, Ids,1 ∝ ΓsΓd/(Γs + Γd) shall be representative of the tunneling rates Γs and Γd with the source and drain. With respect to the weakly disordered device of Figure 1b, the calculated current decreases by orders of magnitude due to the large tunnel barriers raised by the constrictions. Also, the threshold Vg,1 is shifted to larger gate 2962
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TOLOP No 318397 and SiSPIN No 323841. The NEGF calculations were run at the TGCC/Curie machine using allocations from PRACE and GENCI.
resonance is strongly dependent on the shape of the dot and can range from a few to a few tens of meV. Experimental data for other n- and p- type devices are given in the Supporting Information (Figure S5). In our samples, a very good transmission through the 25 nm long spacers can be achieved for any temperature by adjusting the back gate voltage. The fact that the resonant current at T = 4.2 K is comparable to the current measured at 300 K proves that any parasitic stochastic Coulomb blockade effect can be eliminated in our devices by a proper choice of the control voltages. In contrast to our results for the n-type sample, Shin et al.27 have observed current resonances at room temperature that, however, split into multiple peaks at low temperature. Furthermore, the current at the resonances decreases as the temperature is reduced. The regular pattern of split peaks and their drain voltage dependence can be attributed (a) to the effect of valley splitting of orbital levels,8 (b) to a possible parasitic effect due to granularity in the gate stack,28 or (c) to the appearance of multiple dots in series (as in the p-type sample case). In summary, we have fabricated 3.4 nm diameter nanowire Ω-gate MOSFETs with deliberately long offset spacers (25 nm) and short gate length (10 nm) using DUV lithography and standard 300 mm CMOS process. Such a design isolates the channel from the source and the drain and enhances Coulomb interactions within the channel. As a result, these devices show robust addition spectra characteristic of artificial atoms. The shape and location of these artificial atoms depend on line edge roughness along the nanowire but the most prominent source of disorder, that is, the presence of few cavities in series can be managed thanks to the control by both front and back gate voltages. The addition energy can reach up to 230 meV depending on the surface roughness. The orbital excited state is several 10 meV above the ground state and the measured valley orbit splitting is around 5 meV in n-type devices, a large value for a quantum dot.33 These devices bridge conventional MOSFETS with SETs, and show that Coulomb interactions within the channel are bound to play an increasingly important role in the physics and design of the next generations of silicon devices. Finally, the on-chip integration of these artificial atoms with CMOS peripheral modules controlling their operation is very easy, because large size transistors are made with the very same CMOS technology.23
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ASSOCIATED CONTENT
S Supporting Information *
Additional experimental data (surface roughness, double dot stability diagram, temperature dependence, and Coulomb diamonds at room temperature) and modeling details (methodology and additional results). The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/nl504806s.
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REFERENCES
AUTHOR INFORMATION
Corresponding Author
*E-mail: [email protected]. Phone: +33(0)4 38 78 43 67. Fax: +33(0)4 38 78 50 96. Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS The authors acknowledge A. Orlov for a careful reading of the manuscript and financial support from the EU under Projects 2963
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