Letter pubs.acs.org/NanoLett
Lithography-Free Fabrication of Core−Shell GaAs Nanowire Tunnel Diodes A. Darbandi, K. L. Kavanagh, and S. P. Watkins* Department of Physics, Simon Fraser University, Burnaby, BC V5A-1S6, Canada S Supporting Information *
ABSTRACT: GaAs core−shell p−n junction tunnel diodes were demonstrated by combining vapor−liquid−solid growth with gallium oxide deposition by atomic layer deposition for electrical isolation. The characterization of an ensemble of core−shell structures was enabled by the use of a tungsten probe in a scanning electron microscope without the need for lithographic processing. Radial tunneling transport was observed, exhibiting negative differential resistance behavior with peak-to-valley current ratios of up to 3.1. Peak current densities of up to 2.1 kA/cm2 point the way to applications in core−shell photovoltaics and tunnel field effect transistors. KEYWORDS: GaAs, nanowire, core−shell, tunnel diodes, metalorganic vapor phase epitaxy
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terized in place without removal from the substrate using a tungsten nanoprobe in a scanning electron microscope. This avoids potentially damaging lithographic processing steps and enables the rapid evaluation of an ensemble of single NW devices.11,12 The overall fabrication steps are summarized in Figure 1. An n-type GaAs (111)B substrate serves as the bottom contact. Short n-type GaAs cores are grown by the vapor−liquid−solid (VLS) mechanism from Au nanoparticles in a metalorganic vaporphase epitaxy (MOVPE) reactor, and the entire wafer is then coated in Ga2O3 by atomic layer
emiconducting core−shell nanowire (NW) structures have been proposed for several applications, including photovoltaics (PV)1 and field effect transistors (FETs).2 Tunnel diode behavior in nanowire structures is of recent interest for use in FET applications in order to reduce the drive power in highly scaled devices.3 Tunneling behavior in axial p−n homo and heterojunctions has been reported in NWs by a few groups.4−6 Moselund et al. demonstrated vertical tunnel FETs using axial InAs/silicon tunnel junctions.7 The growth of III−V structures on Si is attractive due to cost and processing considerations and becomes increasingly feasible for NW structures due to the reduced contact area between the mismatched materials. The use of a core−shell geometry can potentially improve the on-state current by increasing the surface area.8,9 The electrical properties of core−shell p−n tunnel junctions have been reported for lithographically patterned Si−Ge NW structures2 and more recently in lithographically patterned InP/InGaAs core−shell devices.9 Tunnel FETs based on radial InAs/GaSb core−shell heterojunctions were recently reported and shown to result in higher on-state currents compared with axial tunnel junctions.8 In addition to tunnel FETs, radial tunnel junctions could find applications in future NW PV devices as contacts between multiple radial p−n junctions, similar to the approach used in advanced planar PV multijunction devices.10 Most research into the electrical properties of core−shell NWs has relied on the use of challenging lithographic processes. Typically, NWs are removed from a substrate and patterned using costly lithographic techniques which can introduce extensive surface modification. In this work we present the realization of core−shell n−p junction NW tunnel diodes fabricated without lithographic processing and charac© XXXX American Chemical Society
Figure 1. (a) GaAs NW “footings” coated with ALD-deposited Ga2O3, (b) regrown GaAs NWs formed by decomposing Ga2O3 above the Au/Ga eutectic temperature, and (c) intended final structure of the core−shell tunnel diodes investigated in this work. Received: May 7, 2015 Revised: July 3, 2015
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DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters
abrupt interface with the Au-NP. Energy dispersive X-ray spectroscopy (EDS) was taken from the Au-NP down to the tip of the GaAs NW. The corresponding drift-corrected spectra are shown in Figure 2b. The EDS spectra are normalized to the Au peak. The Ga profile inside the Au-NP shows a slightly higher intensity which is likely an artifact due to matrix effects due to reabsorption. Similarly, the nonzero levels of As are likely due to reabsorption artifacts. The oxygen trace further confirms the existence of the Ga2O3 layer. The oxide-coated NW footings were then reloaded into the MOVPE reactor for VLS regrowth of the n-type core. The wires were first heated to 400 °C under TBAs for 60 s. At this temperature, which is above the eutectic point of the Au/Ga alloy, the Ga2O3 decomposes at the NP surface, releasing O2, and fresh supersaturated Au/Ga alloy is exposed. Upon introducing the TMGa, TBAs, and DETe precursors (also at 400 °C), NW growth continues, while growth on the oxidecoated regions is suppressed (see Supporting Information). A representative SEM image of n-type GaAs(Te) NWs with a diameter of ∼100 nm is shown in Figure 3a. The image
deposition (ALD) (Figure 1a). The ALD Ga2O3 is used to provide isolation from any two-dimensional layer that would otherwise form on the substrate surface and act as a parasitic junction. The Ga2O3 film forms a stable oxide layer at typical MOVPE growth temperatures but can be decomposed in the vicinity of the Au NP, providing a fresh surface for continued VLS growth (Figure 1b). Figure 1c shows the final intended structure. A nominally undoped axial spacer segment (“i”) prevents the formation of a parasitic axial p−n tunnel junction. A p-type shell is formed by using a Ga precursor which favors conventional vapor solid (VS) growth at these temperatures. This also results in a residual p-type axial segment which reduces the contact resistance of the gold to the p-type shell (Figure 1c). The growth is entirely self-aligned requiring no lithographic processing steps. The resulting GaAs core−shell n−p junction tunnel diodes have high peak current densities and peak-to-valley current ratios (PVCR) up to 3.1. The fabrication process begins with the formation of Au nanoparticles (NP) by deposition of a 3 nm gold layer on a (111)B Si-doped (3 × 1018 cm−3) GaAs wafer using vacuum evaporation followed by annealing at 475 °C for 1 min under H2 and tertiary butylarsine (TBAs) overpressure in the MOVPE reactor. The short GaAs footings (Figure 1a) were grown using trimethylgallium (TMGa) and TBAs at flow rates of 17 and 160 μ mol/s, respectively, at 400 °C. Te-doping was carried out by introducing H2-diluted diethyltellurium (DETe) with a molar flow of 0.05 μmol/min. N-type GaAs NWs were grown with an average length of 500 nm. The wafer was then loaded inside an ALD reactor, where trimethylgallium (TMGa), and O2 were used as precursors and Ar was employed as the carrier gas. The oxide was grown at 375 °C at a chamber pressure of 3 × 10−3 Torr. The Ga2O3 growth rate was ∼0.05 nm/cycle. A representative BF-TEM image of the oxide-coated GaAs NW is shown in Figure 2a which shows a 10 nm thick
Figure 3. (a) SEM image of n-type GaAs(Te) NWs on NW-footings. (b) BF-TEM image of a GaAs(Te) NW in which the lower segment corresponds to the GaAs/Ga2O3 core−shell. (c) Selected area electron diffraction pattern from the middle of the GaAs(Te) NW.
contrast at the base of the NWs, as well as at the substrate surface, clearly indicates the presence of the oxide layer. Further investigation was performed to verify the quality of the regrown NWs. Figure 3b shows a BF-TEM image of the latter sample. The oxide-coated regions are labeled green in the figure. The boundary was confirmed by EDS observation of oxide in those regions. In addition, the oxide-coated regions have an observable thickness increase compared with the uncoated regions. No trace of oxygen was found by EDS on the surface of the regrown GaAs(Te) NWs. There is a defective GaAs region at the regrowth junction which coincides with the interruption of the vapor−liquid−solid (VLS) growth. Straight defects are visible starting in the regrown nanowire, slanted toward the sidewall. The angle with respect to the growth direction (30°) is consistent with commonly observed {111} stacking faults. The selected area electron diffraction pattern in Figure 3c indicates the NW was zincblende phase, growth direction [111] with the electron beam oriented close to a (112) NW direction.
Figure 2. (a) Representative BF-TEM image, (b) energy dispersive Xray spectroscopy linescan, and (c) HR-TEM image of a GaAs(Te)/ Ga2O3 NW.
Ga2O3 layer cladding the NW and NP. The image contrast at the NW edges is due to facets. A similar oxide layer was also formed on the substrate. It should be pointed out that the growth of the footing segments was found to be necessary to localize the Au NPs following MOVPE regrowth. If oxide was deposited directly on the NPs, a significant fraction of the NWs were observed to grow along the substrate surface. The protective oxide layer is amorphous as seen from the HR-TEM image of a 50 nm thick GaAs NW shown in Figure 2c. GaAs lattice fringes confirm single crystal structure with an B
DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters
Prior to proceeding with fabrication of the intended tunnel diode structure indicated in Figure 1c, two challenges should be resolved: (1) Ohmic contact formation to the p-type shell layer, and (2) suppression of the electrical conduction from the axial p−n junction at the tip of the NWs. As indicated in Figure 1c, our contact scheme relies on an Ohmic contact formed between the Au NP and the degenerately p-doped GaAs shell. In order to assess the electrical properties of the p-type shell contact scheme the structure in the inset of Figure 5a was
The electrical properties of the n-type NWs following the regrowth procedure were measured by contacting the Au NP at the tip of each free-standing NW with a tungsten nanoprobe. The procedure, shown as an inset in Figure 4, was carried out
Figure 4. Upper curves show representative I−V properties of three regrown GaAs(Te) NWs. The lower curve shows the result of contacting the oxide-coated substrate directly with the nanoprobe.
inside a scanning electron microscope. An average of 20 NWs with various diameters were tested from across the wafer. Figure 4 shows representative I−V curves for GaAs(Te) NWs with an average length of 6.5 μm. The curves indicated in the legend were obtained by placing the nanoprobe tip on the Au nanoparticle using the substrate as the ground electrode. For these n-type NWs, the measured current rectification is due to the Schottky contact at the NP/NW interface.12 The I−V characteristics of the metal−semiconductor diode, including the NW resistance R are given by I = I0[eq(V−IRNW/(nkBT)) − 1], based on thermionic emission theory. The experimental data was fitted using the latter equation with less than 5% error. The ideality factor extracted from this fit was in the range n = 1.1− 1.4. Assuming a cylindrical geometry for the NWs the average apparent resistivity [ρ* = R(πr2NW/l)] was estimated to be between 0.006 and 0.009 Ω cm. These results are comparable to those obtained without the regrowth procedure confirming that there was no appreciable penalty to the electrical performance. This effective resistivity value corresponds to an average estimated n-type dopant concentration of ∼5 × 1017 cm−3 assuming negligible acceptor compensation. Careful analysis of these data show that the current density at high bias (normalized to a constant NW length) increases approximately as the inverse of the NW diameter, indicating the presence of enhanced doping at the surface, consistent with some lateral growth. The effect of contacting the tip directly to the Ga2O3-coated GaAs substrate is shown in the lower curve in Figure 4. The current is greatly reduced, but nonzero, suggesting either some residual leakage through the oxide, or possible partial penetration of the probe to the underlying substrate. I−V measurements obtained using metal contacts to a Ga2O3 coated GaAs substrate indicate a resistivity of at least 105 Ohm·cm, which is more than adequate to ensure isolation of the individual NWs (see Supporting Information).
Figure 5. (a) I−V characteristics of a Au nanoparticle contacted to a ptype shell. (b) Upper curve shows residual conduction through nominally undoped “i” segment due to memory effect from previous ndoped axial segment. The lower curve shows suppression of the ndopant memory effect by TBAs purge of NP following growth of ndoped segment.
grown. A nominally undoped GaAs NW core was grown on a p-type GaAs(Zn) (111)B substrate with the growth conditions stated earlier. A 70 nm thick GaAs(Zn) shell was grown subsequently using diethylzinc (DEZn) and triethylgallium (TEGa) with a molar flow of 0.4 μmol/min and 1.78 μmol/ min, respectively. TEGa promotes lateral growth with an average growth rate of 0.25 nm/s at 400 °C. The measured current densities for the p-shell NW test structures are shown in Figure 5a for several NWs with various overall diameters. Approximately ohmic I−V characteristics were observed for all measured devices. The apparent resistivity of the corresponding p-type shell was evaluated using the effective cross-sectional area and was estimated to be 0.007 Ω cm. The resistance of the C
DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters residual p-doped neck region, which serves as the contact between the shell and the NP (see Figure 1c), was neglected since its length with respect to the full device length is relatively small, and the cross sectional area is much larger than that of the shell region. The estimated shell resistivity corresponds to a degenerate hole concentration of ∼3 × 1019 cm−3 assuming negligible electron compensation. We confirmed that this high doping resulted from the Zn precursor, since a doubling of the DEZn flow yielded a similar increase in the conductivity of the shell. This suggests that residual carbon incorporation from the TEGa precursor was negligible by comparison. The second challenge relevant to achieving the intended radial tunnel diode structure is to prevent unwanted conduction through the axial p−n channel at the tip of the NWs. An axial p−n junction at the top end of the NWs could be created during the p-type shell growth since the TEGa source still results in a limited axial VLS growth rate of ∼4 nm/s. To suppress this axial path, a resistive undoped GaAs segment was placed in between the n-type and p-type core region (Figure 1c). The solubility of Te in Au NPs is rather high13 which can lead to unwanted memory effects for axial junctions. To ensure complete purging of the NP before growth of the undoped segment, a growth interrupt under TBAs was used to purge Te dopant from the NP. This procedure relies on the high vapor pressure of Te (86 Pa at 400 °C14) which ensures reevaporation of Te from the NP upon reduction of the Te input flux to zero. To test this procedure we grew two structures consisting of an n-type core followed by a nominally undoped segment as shown in the inset in Figure 5b. In one case the structure was grown with no NP purging, while in the second case the NP was purged under TBAs for 200 s. Figure 5b shows the I−V characteristics of a representative NW where a 350 nm thick undoped GaAs axial segment was grown after the n-type core NW (upper curve). The I−V curve shows current rectification with a diode ideality factor of 1.1. Several devices with various diameters within the range of 250−600 nm were examined, and the resistivity of the undoped neck was estimated to be 0.025 Ω·cm. This rather low resistivity indicates the contribution of residual tellurium from the Au NP from the previous growth step. This is due to the rather high solubility of Te in the NP.13 The lower curve in Figure 5b shows the same structure but with a 200 s TBAs anneal at 400 °C after the growth of the n-type segment, followed by growth of the undoped core. This technique takes advantage of the high vapor pressure of Te (86 Pa at 400 °C14) to drive off the residual Te atoms dissolved in the Au-NPs during the TBAs interrupt. A highly insulating GaAs neck with a resistance of ∼250 GΩ was obtained, confirming the effectiveness of the undoped blocking segment. Radial NW tunnel diode devices using the full structure indicated schematically in Figure 1c were fabricated. No evidence of GaAs growth on the oxide coated regions was observed in TEM measurements (see Supporting Information). A BF-TEM image of a single NW tunnel diode device is shown in Figure 6a. The image contrast at the edges is due to the NW facets. The observed tapering at the tip of the device is the result of residual VLS growth during the shell growth. Individual NW tunnel diodes were examined electrically using the nanoprobe technique at room temperature. Five devices with various overall diameters in the range of 275−420 nm were studied. The mean length of the measured devices was 3.0 ± 0.2 μm.
Figure 6. (a) Bright field TEM image of final device structure. Representative forward (b) and reverse (c) I−V properties of core− shell GaAs n−p junction devices with various diameters. (d) indicates typical Fermi level positions at equilibrium assuming NA = 3 × 1019 cm−3 and ND = 3 × 1019 cm−3 (not to scale).
A plot of measured total device current versus forward bias is shown in Figure 6b. Clear tunnel diode behavior with a characteristic negative differential resistance region was observed for all measured devices. Three components contribute to current flow in heavily doped p−n tunnel diodes. At small applied bias electrons tunnel directly from the conduction band of the n-type material to the unoccupied energy states at the valence band of the p-type material. The tunneling current reaches a maximum value Ip above which fewer energy levels are available upon further increase of the applied voltage. The current decreases until the bands are uncrossed leading to a negative differential resistance characterized by the valley voltage. The present devices showed peak voltages in the range of 0.20−0.22 V. Based on the approximate area of the core−shell p−n junctions the peak current densities were in the range of 0.9−2.3 kA/cm2. The pn junction area was calculated from the estimated surface area of the regrown n-type core based on its nominal length and radius. These numbers are very high compared with typical planar diode GaAs tunnel junctions.10,15 Our values also compare favorably with those of Si−Ge core−shell tunnel junctions of around 2.5 kA/cm2.2 In general, for a multijunction photovoltaic device the peak tunneling current density should be much higher than the short circuit current density,10 therefore the observation of high peak current densities in these structures is promising. The negative differential resistance can be characterized by the peak-to-valley current ratio (PVCR) Ip/Iv, measured in the range 2.5−3.1 for the fabricated devices. These values are similar to those of planar GaAs tunnel diodes.15 Higher PVCR values can be achieved by bandgap engineering through the use of heterostructures. A room temperature PVCR of about 8 has been reported for axial InP/GaAs NWs16 and radial InP/ InGaAs core−shell NWs.9 The total tunneling diode current can be written as the sum of three terms: D
DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters Itot = IT + I x + Ipn
values obtained from Figure 6d agree well with finite element simulations based on the expected calibrated resistivity of the core and shell regions. It is worth pointing out that the resistance values extracted from linear fits to Figure 6d agree with the values obtained from the diode equation for forward bias in the thermal diffusion limit. In both cases the I−V properties are determined by the Ohmic losses in the neutral regions of the device. The preceding results show that core−shell tunnelling diodes can be fabricated using a hybrid MOVPE/ALD method employing the use of precursor chemistry to control the axial versus lateral growth. A novel self-aligned fabrication method employing catalyst nanoparticles and ALD gallium oxide was shown to result in electrically isolated devices that can be probed by a single tungsten nanoprobe without the use of lithographic processing steps. This technique points the way to rapid characterization of core−shell NW structures for application in FETs and PV devices.
(1)
where the tunneling current IT, excess current Ix, and thermal diffusion current are given by17 ⎛ IP V⎞ V exp⎜1 − ⎟ VP VP ⎠ ⎝
(2)
I x = IV exp(A[V − Vv])
(3)
⎛ ⎛ qV − IRNW ⎞ ⎞ ⎟ − 1⎟ Ipn = Is⎜exp⎜ ⎝ ⎠ ⎝ ⎠ nkT
(4)
IT =
where VP and VV are the peak and valley voltages, respectively, IS is the saturation current, and A is an empirical coefficient. Ip, IV, Vp, VV, and n were determined from fits to the data shown in Figure 6. For larger diameter devices, the curves are fitted quite well including only the tunneling and diffusion current terms. For the smaller devices, an excess current contribution was also needed to achieve acceptable fits.The primary fitting parameters are summarized in Table 1 An average diode ideality factor of n
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S Supporting Information *
Additional information verifying the selectivity of the gallium oxide shell, as well as details concerning estimates of the gallium oxide resistivity, is given. The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b01795.
Table 1. Tunneling Transport Parameters 2
19
−3
nanowire diameter
JP (kA/cm )
VP (V)
ND (10 cm )
275 300 320 360 420
0.97 1.75 2.18 2.14 2.10
0.16 0.18 0.23 0.26 0.21
1.8 2.1 2.8 3.3 2.5
ASSOCIATED CONTENT
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AUTHOR INFORMATION
Corresponding Author
*E-mail: [email protected].
= 2.5 ± 0.1 was obtained with a saturation current Is = 1.4 ± 0.9 × 10−11 A. The rather high value of the ideality factor may result from compensating defects due to the high doping levels employed. The peak voltage can be estimated from the p- and n-doping concentrations.18 We assume an acceptor concentration of the p-doped shell of NA = 3 × 1019 cm−3 based on nanoprobe measurements of undoped-core/p-doped shell doping calibrations discussed earlier. The effective doping of the n-type core is nominally 5 × 1017 cm−3 based on nanoprobe measurements; however, this is not enough to account for the observed peak voltage values. We attribute the discrepancy to the formation of a thin, very highly doped shell due to residual lateral growth during core growth. The values of ND in Table 1 reproduce the observed peak voltages and indicate n-doping of the thin shell in the range 1.8−3.3 × 1019 cm−3. This is consistent with previous measurements of shell doping using DETe under similar growth conditions;13 however, the assumption of parabolic conduction band dispersion in reference 19 means that these are very rough estimates. Typical estimated values of the equilibrium Fermi levels for the n-type and p-type materials are shown in the inset of Figure 6. For the smaller diameter devices, fit quality was greatly improved by adding the excess current term eq 3. Excess current is the result of electrons tunneling to midgap states. It has been shown that for InAs/Si tunnel diode NWs the excess current resulting from defects result in a low PVCR.19 This term has a negligible contribution in our devices except for the smaller diameter devices, indicating possibly the increased effect of surface states. The reverse I−V characteristics are shown in Figure 6d plotted on a linear scale. These data are dominated by the effective resistance of the core−shell nanowire. The resistance
Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS We thank the staff at 4DLABS for assistance with ALD and electron microscopy. The authors gratefully acknowledge funding from the Natural Sciences and Engineering Research Council of Canada.
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REFERENCES
(1) Dong, Y.; Tian, B.; Kempa, T. J.; Lieber, C. M. Nano Lett. 2009, 9, 2183−2187. (2) Fung, W. Y.; Chen, L.; Lu, W. Appl. Phys. Lett. 2011, 99, 092108−3. (3) Choi, W. Y.; Park, B.-G.; Lee, J. D.; Liu, T.-J. K. IEEE Electron Device Lett. 2007, 28, 743−745. (4) Chen, L.; Fung, W. Y.; Lu, W. Nano Lett. 2013, 13, 5521−5527. (5) Zhang, P.; Le, S. T.; Hou, X.; Zaslavsky, A.; Perea, D. E.; Dayeh, S. A.; Picraux, S. T. Appl. Phys. Lett. 2014, 105, 062106−4. (6) Schmid, H.; Bessire, C.; Björk, M. T.; Schenk, A.; Riel, H. Nano Lett. 2012, 12, 699−703. (7) Moselund, K. E.; Schmid, H.; Bessire, C.; Bjork, M. T.; Ghoneim, H.; Riel, H. IEEE Electron Device Lett. 2012, 33, 1453−1455. (8) Dey, A. W.; Svensson, J.; Ek, M.; Lind, E.; Thelander, C.; Wernersson, L.-E. Nano Lett. 2013, 13, 5919−5924. (9) Ganjipour, B.; Tizno, O.; Heurlin, M.; Borgstrom, M. Device Research Conference (DRC), 72nd Annual, Santa Barbara, CA, 2014; pp 123−124. (10) Sugiura, H.; Amano, C.; Yamamoto, A.; Yamaguchi, M. Jpn. J. Appl. Phys. 1988, 27, 269−272. (11) Talin, A. A.; Léonard, F.; Swartzentruber, B. S.; Wang, X.; Hersee, S. D. Phys. Rev. Lett. 2008, 101, 076802−4. (12) Salehzadeh, O.; Chen, M. X.; Kavanagh, K. L.; Watkins, S. P. Appl. Phys. Lett. 2011, 99, 182102−3.
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Nano Letters (13) Salehzadeh, O.; Kavanagh, K. L.; Watkins, S. P. J. Appl. Phys. 2012, 112, 054324. (14) Machol, R. E.; Westrum, E. F. J. Am. Chem. Soc. 1958, 80, 2950−2952. (15) Hermle, M.; Letay, G.; Philipps, S. P.; Bett, A. W. Prog. Photovoltaics 2008, 16, 409−418. (16) Wallentin, J.; Persson, J. M.; Wagner, J. B.; Samuelson, L.; Deppert, K.; Borgström, M. T. Nano Lett. 2010, 10, 974−979. (17) Sze, S. M.; Ng, K. K. Physics of Semiconductor Devices; John Wiley & Sons: New York, 2006; p 7. (18) Demassa, T.; Knott, D. Solid-State Electron. 1970, 13, 131. (19) Bessire, C. D.; Bjork, M. T.; Schmid, H.; Schenk, A.; Reuter, K. B.; Riel, H. Nano Lett. 2011, 11, 4195−4199.
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Lithography-Free Fabrication of Core−Shell GaAs Nanowire Tunnel Diodes A. Darbandi, K. L. Kavanagh, and S. P. Watkins* Department of Physics, Simon Fraser University, Burnaby, BC V5A-1S6, Canada S Supporting Information *
ABSTRACT: GaAs core−shell p−n junction tunnel diodes were demonstrated by combining vapor−liquid−solid growth with gallium oxide deposition by atomic layer deposition for electrical isolation. The characterization of an ensemble of core−shell structures was enabled by the use of a tungsten probe in a scanning electron microscope without the need for lithographic processing. Radial tunneling transport was observed, exhibiting negative differential resistance behavior with peak-to-valley current ratios of up to 3.1. Peak current densities of up to 2.1 kA/cm2 point the way to applications in core−shell photovoltaics and tunnel field effect transistors. KEYWORDS: GaAs, nanowire, core−shell, tunnel diodes, metalorganic vapor phase epitaxy
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terized in place without removal from the substrate using a tungsten nanoprobe in a scanning electron microscope. This avoids potentially damaging lithographic processing steps and enables the rapid evaluation of an ensemble of single NW devices.11,12 The overall fabrication steps are summarized in Figure 1. An n-type GaAs (111)B substrate serves as the bottom contact. Short n-type GaAs cores are grown by the vapor−liquid−solid (VLS) mechanism from Au nanoparticles in a metalorganic vaporphase epitaxy (MOVPE) reactor, and the entire wafer is then coated in Ga2O3 by atomic layer
emiconducting core−shell nanowire (NW) structures have been proposed for several applications, including photovoltaics (PV)1 and field effect transistors (FETs).2 Tunnel diode behavior in nanowire structures is of recent interest for use in FET applications in order to reduce the drive power in highly scaled devices.3 Tunneling behavior in axial p−n homo and heterojunctions has been reported in NWs by a few groups.4−6 Moselund et al. demonstrated vertical tunnel FETs using axial InAs/silicon tunnel junctions.7 The growth of III−V structures on Si is attractive due to cost and processing considerations and becomes increasingly feasible for NW structures due to the reduced contact area between the mismatched materials. The use of a core−shell geometry can potentially improve the on-state current by increasing the surface area.8,9 The electrical properties of core−shell p−n tunnel junctions have been reported for lithographically patterned Si−Ge NW structures2 and more recently in lithographically patterned InP/InGaAs core−shell devices.9 Tunnel FETs based on radial InAs/GaSb core−shell heterojunctions were recently reported and shown to result in higher on-state currents compared with axial tunnel junctions.8 In addition to tunnel FETs, radial tunnel junctions could find applications in future NW PV devices as contacts between multiple radial p−n junctions, similar to the approach used in advanced planar PV multijunction devices.10 Most research into the electrical properties of core−shell NWs has relied on the use of challenging lithographic processes. Typically, NWs are removed from a substrate and patterned using costly lithographic techniques which can introduce extensive surface modification. In this work we present the realization of core−shell n−p junction NW tunnel diodes fabricated without lithographic processing and charac© XXXX American Chemical Society
Figure 1. (a) GaAs NW “footings” coated with ALD-deposited Ga2O3, (b) regrown GaAs NWs formed by decomposing Ga2O3 above the Au/Ga eutectic temperature, and (c) intended final structure of the core−shell tunnel diodes investigated in this work. Received: May 7, 2015 Revised: July 3, 2015
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DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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abrupt interface with the Au-NP. Energy dispersive X-ray spectroscopy (EDS) was taken from the Au-NP down to the tip of the GaAs NW. The corresponding drift-corrected spectra are shown in Figure 2b. The EDS spectra are normalized to the Au peak. The Ga profile inside the Au-NP shows a slightly higher intensity which is likely an artifact due to matrix effects due to reabsorption. Similarly, the nonzero levels of As are likely due to reabsorption artifacts. The oxygen trace further confirms the existence of the Ga2O3 layer. The oxide-coated NW footings were then reloaded into the MOVPE reactor for VLS regrowth of the n-type core. The wires were first heated to 400 °C under TBAs for 60 s. At this temperature, which is above the eutectic point of the Au/Ga alloy, the Ga2O3 decomposes at the NP surface, releasing O2, and fresh supersaturated Au/Ga alloy is exposed. Upon introducing the TMGa, TBAs, and DETe precursors (also at 400 °C), NW growth continues, while growth on the oxidecoated regions is suppressed (see Supporting Information). A representative SEM image of n-type GaAs(Te) NWs with a diameter of ∼100 nm is shown in Figure 3a. The image
deposition (ALD) (Figure 1a). The ALD Ga2O3 is used to provide isolation from any two-dimensional layer that would otherwise form on the substrate surface and act as a parasitic junction. The Ga2O3 film forms a stable oxide layer at typical MOVPE growth temperatures but can be decomposed in the vicinity of the Au NP, providing a fresh surface for continued VLS growth (Figure 1b). Figure 1c shows the final intended structure. A nominally undoped axial spacer segment (“i”) prevents the formation of a parasitic axial p−n tunnel junction. A p-type shell is formed by using a Ga precursor which favors conventional vapor solid (VS) growth at these temperatures. This also results in a residual p-type axial segment which reduces the contact resistance of the gold to the p-type shell (Figure 1c). The growth is entirely self-aligned requiring no lithographic processing steps. The resulting GaAs core−shell n−p junction tunnel diodes have high peak current densities and peak-to-valley current ratios (PVCR) up to 3.1. The fabrication process begins with the formation of Au nanoparticles (NP) by deposition of a 3 nm gold layer on a (111)B Si-doped (3 × 1018 cm−3) GaAs wafer using vacuum evaporation followed by annealing at 475 °C for 1 min under H2 and tertiary butylarsine (TBAs) overpressure in the MOVPE reactor. The short GaAs footings (Figure 1a) were grown using trimethylgallium (TMGa) and TBAs at flow rates of 17 and 160 μ mol/s, respectively, at 400 °C. Te-doping was carried out by introducing H2-diluted diethyltellurium (DETe) with a molar flow of 0.05 μmol/min. N-type GaAs NWs were grown with an average length of 500 nm. The wafer was then loaded inside an ALD reactor, where trimethylgallium (TMGa), and O2 were used as precursors and Ar was employed as the carrier gas. The oxide was grown at 375 °C at a chamber pressure of 3 × 10−3 Torr. The Ga2O3 growth rate was ∼0.05 nm/cycle. A representative BF-TEM image of the oxide-coated GaAs NW is shown in Figure 2a which shows a 10 nm thick
Figure 3. (a) SEM image of n-type GaAs(Te) NWs on NW-footings. (b) BF-TEM image of a GaAs(Te) NW in which the lower segment corresponds to the GaAs/Ga2O3 core−shell. (c) Selected area electron diffraction pattern from the middle of the GaAs(Te) NW.
contrast at the base of the NWs, as well as at the substrate surface, clearly indicates the presence of the oxide layer. Further investigation was performed to verify the quality of the regrown NWs. Figure 3b shows a BF-TEM image of the latter sample. The oxide-coated regions are labeled green in the figure. The boundary was confirmed by EDS observation of oxide in those regions. In addition, the oxide-coated regions have an observable thickness increase compared with the uncoated regions. No trace of oxygen was found by EDS on the surface of the regrown GaAs(Te) NWs. There is a defective GaAs region at the regrowth junction which coincides with the interruption of the vapor−liquid−solid (VLS) growth. Straight defects are visible starting in the regrown nanowire, slanted toward the sidewall. The angle with respect to the growth direction (30°) is consistent with commonly observed {111} stacking faults. The selected area electron diffraction pattern in Figure 3c indicates the NW was zincblende phase, growth direction [111] with the electron beam oriented close to a (112) NW direction.
Figure 2. (a) Representative BF-TEM image, (b) energy dispersive Xray spectroscopy linescan, and (c) HR-TEM image of a GaAs(Te)/ Ga2O3 NW.
Ga2O3 layer cladding the NW and NP. The image contrast at the NW edges is due to facets. A similar oxide layer was also formed on the substrate. It should be pointed out that the growth of the footing segments was found to be necessary to localize the Au NPs following MOVPE regrowth. If oxide was deposited directly on the NPs, a significant fraction of the NWs were observed to grow along the substrate surface. The protective oxide layer is amorphous as seen from the HR-TEM image of a 50 nm thick GaAs NW shown in Figure 2c. GaAs lattice fringes confirm single crystal structure with an B
DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters
Prior to proceeding with fabrication of the intended tunnel diode structure indicated in Figure 1c, two challenges should be resolved: (1) Ohmic contact formation to the p-type shell layer, and (2) suppression of the electrical conduction from the axial p−n junction at the tip of the NWs. As indicated in Figure 1c, our contact scheme relies on an Ohmic contact formed between the Au NP and the degenerately p-doped GaAs shell. In order to assess the electrical properties of the p-type shell contact scheme the structure in the inset of Figure 5a was
The electrical properties of the n-type NWs following the regrowth procedure were measured by contacting the Au NP at the tip of each free-standing NW with a tungsten nanoprobe. The procedure, shown as an inset in Figure 4, was carried out
Figure 4. Upper curves show representative I−V properties of three regrown GaAs(Te) NWs. The lower curve shows the result of contacting the oxide-coated substrate directly with the nanoprobe.
inside a scanning electron microscope. An average of 20 NWs with various diameters were tested from across the wafer. Figure 4 shows representative I−V curves for GaAs(Te) NWs with an average length of 6.5 μm. The curves indicated in the legend were obtained by placing the nanoprobe tip on the Au nanoparticle using the substrate as the ground electrode. For these n-type NWs, the measured current rectification is due to the Schottky contact at the NP/NW interface.12 The I−V characteristics of the metal−semiconductor diode, including the NW resistance R are given by I = I0[eq(V−IRNW/(nkBT)) − 1], based on thermionic emission theory. The experimental data was fitted using the latter equation with less than 5% error. The ideality factor extracted from this fit was in the range n = 1.1− 1.4. Assuming a cylindrical geometry for the NWs the average apparent resistivity [ρ* = R(πr2NW/l)] was estimated to be between 0.006 and 0.009 Ω cm. These results are comparable to those obtained without the regrowth procedure confirming that there was no appreciable penalty to the electrical performance. This effective resistivity value corresponds to an average estimated n-type dopant concentration of ∼5 × 1017 cm−3 assuming negligible acceptor compensation. Careful analysis of these data show that the current density at high bias (normalized to a constant NW length) increases approximately as the inverse of the NW diameter, indicating the presence of enhanced doping at the surface, consistent with some lateral growth. The effect of contacting the tip directly to the Ga2O3-coated GaAs substrate is shown in the lower curve in Figure 4. The current is greatly reduced, but nonzero, suggesting either some residual leakage through the oxide, or possible partial penetration of the probe to the underlying substrate. I−V measurements obtained using metal contacts to a Ga2O3 coated GaAs substrate indicate a resistivity of at least 105 Ohm·cm, which is more than adequate to ensure isolation of the individual NWs (see Supporting Information).
Figure 5. (a) I−V characteristics of a Au nanoparticle contacted to a ptype shell. (b) Upper curve shows residual conduction through nominally undoped “i” segment due to memory effect from previous ndoped axial segment. The lower curve shows suppression of the ndopant memory effect by TBAs purge of NP following growth of ndoped segment.
grown. A nominally undoped GaAs NW core was grown on a p-type GaAs(Zn) (111)B substrate with the growth conditions stated earlier. A 70 nm thick GaAs(Zn) shell was grown subsequently using diethylzinc (DEZn) and triethylgallium (TEGa) with a molar flow of 0.4 μmol/min and 1.78 μmol/ min, respectively. TEGa promotes lateral growth with an average growth rate of 0.25 nm/s at 400 °C. The measured current densities for the p-shell NW test structures are shown in Figure 5a for several NWs with various overall diameters. Approximately ohmic I−V characteristics were observed for all measured devices. The apparent resistivity of the corresponding p-type shell was evaluated using the effective cross-sectional area and was estimated to be 0.007 Ω cm. The resistance of the C
DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters residual p-doped neck region, which serves as the contact between the shell and the NP (see Figure 1c), was neglected since its length with respect to the full device length is relatively small, and the cross sectional area is much larger than that of the shell region. The estimated shell resistivity corresponds to a degenerate hole concentration of ∼3 × 1019 cm−3 assuming negligible electron compensation. We confirmed that this high doping resulted from the Zn precursor, since a doubling of the DEZn flow yielded a similar increase in the conductivity of the shell. This suggests that residual carbon incorporation from the TEGa precursor was negligible by comparison. The second challenge relevant to achieving the intended radial tunnel diode structure is to prevent unwanted conduction through the axial p−n channel at the tip of the NWs. An axial p−n junction at the top end of the NWs could be created during the p-type shell growth since the TEGa source still results in a limited axial VLS growth rate of ∼4 nm/s. To suppress this axial path, a resistive undoped GaAs segment was placed in between the n-type and p-type core region (Figure 1c). The solubility of Te in Au NPs is rather high13 which can lead to unwanted memory effects for axial junctions. To ensure complete purging of the NP before growth of the undoped segment, a growth interrupt under TBAs was used to purge Te dopant from the NP. This procedure relies on the high vapor pressure of Te (86 Pa at 400 °C14) which ensures reevaporation of Te from the NP upon reduction of the Te input flux to zero. To test this procedure we grew two structures consisting of an n-type core followed by a nominally undoped segment as shown in the inset in Figure 5b. In one case the structure was grown with no NP purging, while in the second case the NP was purged under TBAs for 200 s. Figure 5b shows the I−V characteristics of a representative NW where a 350 nm thick undoped GaAs axial segment was grown after the n-type core NW (upper curve). The I−V curve shows current rectification with a diode ideality factor of 1.1. Several devices with various diameters within the range of 250−600 nm were examined, and the resistivity of the undoped neck was estimated to be 0.025 Ω·cm. This rather low resistivity indicates the contribution of residual tellurium from the Au NP from the previous growth step. This is due to the rather high solubility of Te in the NP.13 The lower curve in Figure 5b shows the same structure but with a 200 s TBAs anneal at 400 °C after the growth of the n-type segment, followed by growth of the undoped core. This technique takes advantage of the high vapor pressure of Te (86 Pa at 400 °C14) to drive off the residual Te atoms dissolved in the Au-NPs during the TBAs interrupt. A highly insulating GaAs neck with a resistance of ∼250 GΩ was obtained, confirming the effectiveness of the undoped blocking segment. Radial NW tunnel diode devices using the full structure indicated schematically in Figure 1c were fabricated. No evidence of GaAs growth on the oxide coated regions was observed in TEM measurements (see Supporting Information). A BF-TEM image of a single NW tunnel diode device is shown in Figure 6a. The image contrast at the edges is due to the NW facets. The observed tapering at the tip of the device is the result of residual VLS growth during the shell growth. Individual NW tunnel diodes were examined electrically using the nanoprobe technique at room temperature. Five devices with various overall diameters in the range of 275−420 nm were studied. The mean length of the measured devices was 3.0 ± 0.2 μm.
Figure 6. (a) Bright field TEM image of final device structure. Representative forward (b) and reverse (c) I−V properties of core− shell GaAs n−p junction devices with various diameters. (d) indicates typical Fermi level positions at equilibrium assuming NA = 3 × 1019 cm−3 and ND = 3 × 1019 cm−3 (not to scale).
A plot of measured total device current versus forward bias is shown in Figure 6b. Clear tunnel diode behavior with a characteristic negative differential resistance region was observed for all measured devices. Three components contribute to current flow in heavily doped p−n tunnel diodes. At small applied bias electrons tunnel directly from the conduction band of the n-type material to the unoccupied energy states at the valence band of the p-type material. The tunneling current reaches a maximum value Ip above which fewer energy levels are available upon further increase of the applied voltage. The current decreases until the bands are uncrossed leading to a negative differential resistance characterized by the valley voltage. The present devices showed peak voltages in the range of 0.20−0.22 V. Based on the approximate area of the core−shell p−n junctions the peak current densities were in the range of 0.9−2.3 kA/cm2. The pn junction area was calculated from the estimated surface area of the regrown n-type core based on its nominal length and radius. These numbers are very high compared with typical planar diode GaAs tunnel junctions.10,15 Our values also compare favorably with those of Si−Ge core−shell tunnel junctions of around 2.5 kA/cm2.2 In general, for a multijunction photovoltaic device the peak tunneling current density should be much higher than the short circuit current density,10 therefore the observation of high peak current densities in these structures is promising. The negative differential resistance can be characterized by the peak-to-valley current ratio (PVCR) Ip/Iv, measured in the range 2.5−3.1 for the fabricated devices. These values are similar to those of planar GaAs tunnel diodes.15 Higher PVCR values can be achieved by bandgap engineering through the use of heterostructures. A room temperature PVCR of about 8 has been reported for axial InP/GaAs NWs16 and radial InP/ InGaAs core−shell NWs.9 The total tunneling diode current can be written as the sum of three terms: D
DOI: 10.1021/acs.nanolett.5b01795 Nano Lett. XXXX, XXX, XXX−XXX
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Nano Letters Itot = IT + I x + Ipn
values obtained from Figure 6d agree well with finite element simulations based on the expected calibrated resistivity of the core and shell regions. It is worth pointing out that the resistance values extracted from linear fits to Figure 6d agree with the values obtained from the diode equation for forward bias in the thermal diffusion limit. In both cases the I−V properties are determined by the Ohmic losses in the neutral regions of the device. The preceding results show that core−shell tunnelling diodes can be fabricated using a hybrid MOVPE/ALD method employing the use of precursor chemistry to control the axial versus lateral growth. A novel self-aligned fabrication method employing catalyst nanoparticles and ALD gallium oxide was shown to result in electrically isolated devices that can be probed by a single tungsten nanoprobe without the use of lithographic processing steps. This technique points the way to rapid characterization of core−shell NW structures for application in FETs and PV devices.
(1)
where the tunneling current IT, excess current Ix, and thermal diffusion current are given by17 ⎛ IP V⎞ V exp⎜1 − ⎟ VP VP ⎠ ⎝
(2)
I x = IV exp(A[V − Vv])
(3)
⎛ ⎛ qV − IRNW ⎞ ⎞ ⎟ − 1⎟ Ipn = Is⎜exp⎜ ⎝ ⎠ ⎝ ⎠ nkT
(4)
IT =
where VP and VV are the peak and valley voltages, respectively, IS is the saturation current, and A is an empirical coefficient. Ip, IV, Vp, VV, and n were determined from fits to the data shown in Figure 6. For larger diameter devices, the curves are fitted quite well including only the tunneling and diffusion current terms. For the smaller devices, an excess current contribution was also needed to achieve acceptable fits.The primary fitting parameters are summarized in Table 1 An average diode ideality factor of n
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S Supporting Information *
Additional information verifying the selectivity of the gallium oxide shell, as well as details concerning estimates of the gallium oxide resistivity, is given. The Supporting Information is available free of charge on the ACS Publications website at DOI: 10.1021/acs.nanolett.5b01795.
Table 1. Tunneling Transport Parameters 2
19
−3
nanowire diameter
JP (kA/cm )
VP (V)
ND (10 cm )
275 300 320 360 420
0.97 1.75 2.18 2.14 2.10
0.16 0.18 0.23 0.26 0.21
1.8 2.1 2.8 3.3 2.5
ASSOCIATED CONTENT
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AUTHOR INFORMATION
Corresponding Author
*E-mail: [email protected].
= 2.5 ± 0.1 was obtained with a saturation current Is = 1.4 ± 0.9 × 10−11 A. The rather high value of the ideality factor may result from compensating defects due to the high doping levels employed. The peak voltage can be estimated from the p- and n-doping concentrations.18 We assume an acceptor concentration of the p-doped shell of NA = 3 × 1019 cm−3 based on nanoprobe measurements of undoped-core/p-doped shell doping calibrations discussed earlier. The effective doping of the n-type core is nominally 5 × 1017 cm−3 based on nanoprobe measurements; however, this is not enough to account for the observed peak voltage values. We attribute the discrepancy to the formation of a thin, very highly doped shell due to residual lateral growth during core growth. The values of ND in Table 1 reproduce the observed peak voltages and indicate n-doping of the thin shell in the range 1.8−3.3 × 1019 cm−3. This is consistent with previous measurements of shell doping using DETe under similar growth conditions;13 however, the assumption of parabolic conduction band dispersion in reference 19 means that these are very rough estimates. Typical estimated values of the equilibrium Fermi levels for the n-type and p-type materials are shown in the inset of Figure 6. For the smaller diameter devices, fit quality was greatly improved by adding the excess current term eq 3. Excess current is the result of electrons tunneling to midgap states. It has been shown that for InAs/Si tunnel diode NWs the excess current resulting from defects result in a low PVCR.19 This term has a negligible contribution in our devices except for the smaller diameter devices, indicating possibly the increased effect of surface states. The reverse I−V characteristics are shown in Figure 6d plotted on a linear scale. These data are dominated by the effective resistance of the core−shell nanowire. The resistance
Notes
The authors declare no competing financial interest.
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ACKNOWLEDGMENTS We thank the staff at 4DLABS for assistance with ALD and electron microscopy. The authors gratefully acknowledge funding from the Natural Sciences and Engineering Research Council of Canada.
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REFERENCES
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