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Highly Stable Carbon Nanotube Top-Gate Transistors with Tunable Threshold Voltage Huiliang Wang, Brian Cobb,* Albert van Breemen, Gerwin Gelinck, and Zhenan Bao* Single-walled carbon nanotubes (SWNTs) possess ideal properties for thin film transistors (TFTs) such as high charge carrier mobility,[1] solution processability[2,3] and excellent mechanical flexibility.[4] One of the major issues preventing the practical use of SWNTs in electronics is that as-synthesized SWNTs are a mixture of semiconducting and metallic SWNTs. Metallic SWNTs must be removed from these mixtures in order to fabricate high performance TFTs. Recently, a variety of sorting techniques such as density gradient centrifugation,[5] gel chromatography,[6,7] and conjugated polymers sorting[3,8] have been successfully used to separate semiconducting SWNTs from their metallic counterparts. While the TFTs fabricated by these sorted carbon nanotubes demonstrate high mobility and on/ off ratios,[3,7,9,10] challenges still remain for their practical use, including: i) reduction of the operational large hysteresis,[11,12] primarily caused by charge traps at the surface and bulk of gate transistor dielectrics;[13] ii) environmental stability, SWNT TFTs are generally unipolar in air and ambipolar in inert atmosphere,[10] while consistent device characteristics are desired independent of environment; iii) reduction and control of the threshold voltage (Vth) of SWNT TFTs[3,14] preventing the fabrication of robust and low-power circuits. Previously, a few strategies have been attempted to reduce the hysteresis of SWNT transistors such as annealing the device in vacuum,[11] surface treatment of dielectric before deposition,[15] encapsulation of the SWNTs with PMMA,[11] HMDS,[16] spin-on glass,[13] ferroelectric polymer[17] or extra sorting polymers.[12] While these methods can reduce hysteresis to some extent, the long-term bias-stress stability of SWNT TFTs has not been reported. In addition, the control of polarity and the continuous turning of threshold voltage in SWNT TFTs have not been achieved under ambient conditions. In response to the ongoing challenges for SWNT-based TFTs, we fabricated double gate polythiophene-sorted SWNT TFTs by utilizing the Poly(trifluoroethylene) (PTrFE and high-k Poly(vinylidene-trifluoroethylene-chlorotrifluoroethylene), P(VDF-TrFE-CTFE) (Scheme S1), as our top gate dielectrics.
H. Wang, Prof. Z. Bao Department of Materials Science & Engineering Department of Chemical Engineering Stanford University Stanford, CA 94305 E-mail: [email protected] Dr. B. Cobb, Dr. A. van Breemen, Dr. G. Gelinck Holst Centre/TNO High Tech Campus 31, Eindhoven, 5656 AE, Netherlands E-mail: [email protected]
DOI: 10.1002/adma.201400540
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These polymer dielectrics are chosen for three reasons: i) they exhibit high dielectric constants of ∼10 and ∼25 respectively, ii) fluorinated polymers are resistant to moisture,[18] one of the primary causes of hysteresis,[11] and iii) they both have nearly no polarization-field hysteresis[19] (Figure S1 for PTrFE), and therefore do not induce intrinsic hysteresis. By utilizing PTrFE as the top gate dielectric, we fabricated hysteresis-free TFTs with a threshold voltage around 0 V in ambient conditions. The devices exhibit hysteresis-free operation at different sweep rates at a gate field of 0.5 MV/cm with unipolar device characteristics under both ambient and nitrogen atmospheres. Under a vigorous electrical bias stress test lasting 10000 s, the threshold voltage shifts of our SWNT TFTs are comparable to the recently reported stable organic[20,21] or metal oxide[22,23] TFTs. Interestingly, when high-k P(VDF-TrFE-CTFE) was utilized as the top gate dielectric, we also observed a clear ambipolar transistor behavior, even under ambient conditions. Finally, we demonstrate the capability to tune the threshold voltage of both unipolar SWNT TFTs with PTrFE dielectrics and ambipolar SWNT TFTs with P(VDF-TrFE-CTFE) dielectrics by the application of a second gate bias. The ability to tune the threshold voltage of SWNT TFTs in double-gate structures is important for realizing reliable SWNT logic circuits at large scales.[24] We first explored SWNT top gate TFTs with PTrFE dielectrics. The fabrication process is provided in the Experimental Section (a schematic is shown in Figure 1a). The density of spin coated semiconducting SWNT films sorted by Poly (3-dodecylthiophene-2,5-diyl) (P3DDT) in the device is shown in Figure S2. A typical transfer curve is shown in Figure 1b, where the hysteresis is absent. The gate-induced field is around 0.5 MV/cm for a dielectric thickness of 200 nm. An output curve of the device is shown in Figure 1c, indicating no obvious contact barrier. It was reported that the degree of hysteresis is also dependent on the sweep rate since the charge capture and emission times are different for defect traps at the SWNT-dielectric interface and in the bulk.[13] In our devices, no hysteresis was observed at sweep rates ranging from 0.5 V/s to 10 V/s (Figure 1d), indicating minimal trap sites in this device configuration. A transistor with a more typical SWNT bottom gate device structure without a top gate dielectric was also analyzed under the same voltage for comparison. Examples of the device’s transfer and output curves are shown in Figure 1e and S3, where a relatively large hysteresis is seen. Also notable, the bottom gate device has a lower off-current than the top gate device since there is much less gate leakage current through the thermal SiO2 dielectric. Overall, 24 double gate devices were fabricated and characterized in ambient conditions and the statistics of hysteresis are shown in Figure 1f. Hysteresis is defined as the difference between gate voltages needed to induce an average sourcedrain current, i.e., (ISD,max + ISD,min)/2, between the forward and
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COMMUNICATION Figure 1. Hysteresis of SWNT TFTs with PTrFE top gate dielectric at VSD = −5 V. (a) Schematic device structure of SWNT double gate TFTs (devices shown in this figure have PTrFE as top gate dielectric except for the one Figure 1e) (b) Top gate transfer characteristics of a hysteresis-free double gate SWNT TFT. (c) Top gate output characteristics of a SWNT TFT. (d) Sweep rate dependent top gate transfer characteristics of a SWNT TFT. (e) Transfer characteristics of a bottom gate SWNT TFT without top gate dielectric as a control sample. (f) Histogram of the hysteresis of the 24 devices with PTrFE top gate dielectric.
reverse sweeps.[13] Among the 24 devices, 12 devices were fabricated under a nitrogen atmosphere and another 12 were fabricated in ambient conditions. The devices fabricated in ambient condition showed a more positive, near-zero threshold voltage of −0.14 ± 0.38 V in comparison to the devices fabricated under nitrogen with a threshold voltage of −2.18 ± 0.40 V (Figure S4). Previous work has shown that the Vth shift in SWNT TFTs is mainly influenced by the ambient used for characterization rather than that for fabrication.[10] The more positive threshold voltage for devices fabricated in air is likely due to oxygen doping of the SWNTs or oxygen dipole formation between SWNTs and metal contacts,[25] both of which may promote hole transport at more positive gate voltages. The average hysteresis for devices fabricated in air and nitrogen are similar in our case, being 0.40 ± 0.27 V and 0.35 ± 0.21 V, respectively. This shows that fabrication of devices in air does not introduce additional traps in comparison to the devices fabricated under nitrogen. We attribute the observed small hysteresis for some devices to inhomogeneous defects traps at the dielectric. The charge
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carrier mobility of the devices shown in Figure 1 is around 1 cm2/V s, similar to the mobility of conventional bottom gate devices using the same spin-coated SWNTs and measurement conditions. The mobility of the device might be improved further by rinsing or soaking SWNTs films in toluene to remove the insulating P3DDT. However, this might also remove some SWNTs in the channel. The measurement of hysteresis in our SWNT TFTs serves as a useful starting point to examine their stability. Since TFTs used for driving displays, analog circuitry and power electronics need to be kept “on” or “off” for long periods of time, large bias-stress induced threshold voltage shifts should be investigated. Here, we tested the effects of bias voltage on the threshold voltage of SWNT-PTrFE top gate TFTs up to 10000 s. We applied a gate voltage of ±10 V (0.5 MV/cm) with both source and drain grounded. The application of a source-drain voltage has been reported to reduce the effects of threshold voltage shifts for organic semiconductors since it would generate an electrical field that opposes the gate bias.[26] The bias
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of polycrystalline Si TFTs and organic TFTs.[26,27] These authors attributed this change in threshold voltage to ions drifting near the interface of between the semiconductor and dielectric.[26,27] Overall, both the positive and negative bias-induced threshold voltage shifts observed during SWNT TFT device performance are among the smallest in comparison to other recently reported organic[20,21] or oxide TFTs.[22,23] In addition, the mobilities of the devices remain almost constant as evidenced by the similar slopes of the linear-scale transfer curves (Figure 2a and b) at different biases, indicating that the bias does not induce extra defects or impede charge transport in the SWNTs. Therefore, these results demonstrate that the double gate SWNT TFT structures used here are very promising for the long-term operation of TFTs. The high-k dielectric P(VDF-TrFE-CTFE) was also explored as an alternative to PTrFE for top gate dielectrics. Surprisingly, these devices demonstrated excellent ambipolarity (Figure 3a and b) even when measured in ambient conditions. This in contrast to the unipolar p-type behavior observed in our PTrFE based TFTs. Generally, ambipolarity is observed when SWNT transistors are characterized in an inert atmosphere. They normally exhibit unipolar p-type characteristics in ambient atmosphere, even when coated with dielectrics such as PMMA,[11] spin-on-glass,[13] HMDS,[16] or Al2O3.[25,28] The only
Figure 2. Bias-stress testing of SWNT TFTs with PTrFE top gate dielectric at VSD = −5V. (a) Top gate transfer characteristics of a double gate SWNT TFT under gate bias of +10 V, (b) Top gate transfer characteristics of a double gate SWNT TFT under gate bias of −10 V, (c) Threshold voltage shifts as a function of bias time.
stress results are shown in Figure 2. With the application of a gate bias of +10 V, the threshold voltage increases slightly up to 1 V at 10000 s (Figure 2a,c), as a result of trapping of charges similar as those reported for organic and oxide semiconductor previously.[20,22,26] With a bias gate voltage of −10 V, however, the gate threshold voltage first unexpectedly increased for up to 1 V and then decreased back to almost the original threshold voltage value at around 10000s (Figure 2b,c). The unexpected increase in threshold voltage on applying a negative gate voltage has also been observed previously in the case
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Figure 3. Ambipolar SWNT TFT device characteristics with P(VDF-TrFECTFE) top gate dielectric. (a) Top gate transfer characteristics of an ambipolar SWNT TFT (b) Top gate output characteristics of an ambipolar SWNT TFT.
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Δ th,top = −
C bottom Δ bottom C top
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be observed for both PTrFE and P(VDFTrFE-CTFE) top gate dielectric devices. The shifts are caused by the applied bottom gate bias (Vbottom), which modifies the charge distribution in the channel and shifts the threshold voltage of top gate transistor (Vth, top) by[30]
where Ctop and Cbottom are the top and bottom gate capacitance per unit area respectively. The transfer curve for a TFT with a PTrFE dielectric (Figure 4a) shifts in a manner similar to that of self-assembled monolayer layer double-gate transistors, since there is only one channel formed in the thin SWNT network.[31] It was observed that two channels can form for thicker layer polymer double Figure 4. Tuning the threshold voltage of a SWNT TFT with bottom gate bias at VSD = −5 V. gate devices, which causes a shoulder to (a) Top gate transfer characteristics of a unipolar SWNT TFT using PTrFE as the top gate dielec- appear in the transfer curve.[32] By applying tric at different bottom gate bias (VBG). (b) Top gate threshold voltage shifts as a function of a bias from +30 to −30 V, we can tune the bottom gate bias. (c) Top gate transfer characteristics of an ambipolar SWNT TFT using P(VDF- threshold voltage from −4.3 to +9.3 V conTrFE-CTFE) as the top gate dielectric at different bottom gate bias (VBG). (d) Top gate threshold tinuously (Figure 4b). This wide range of voltage shifts as a function of bottom gate bias for both hole current (p-type threshold) and threshold tuning can be used to achieve high electron current (n-type threshold). noise margin large-scale organic circuits as demonstrated by Myny et al.[33] For the double gate device having P(VDF-TrFE-CTFE) as the top gate exception occurs when HfO2 is used as the top gate dielectric, dielectric, both n-type threshold voltage and p-type threshold in which case they exhibit n-type characteristics.[25,28] This voltage tuning is shown in Figures 4c and d. The Vth can be n-type behavior was attributed to the positive fixed charges introduced during HfO2 deposition, reducing the injection tuned from −1.5 to +2 V for hole current and from 9 to 8.2 V for electron current. This degree of tuning is much smaller barrier for electrons.[25] The reason for not observing n-type compared to our SWNT-PTrFE TFTs as the P(VDF-TrFE-CTFE) behavior in Al2O3-based TFTs was proposed by Franklin dielectric results in a larger top-gate capacitive coupling to the et al. as the more electropositive Al attracts more electrons channel. This work also represents the first demonstration in the oxygen ions.[28] Here, both the amounts of C-F dipoles of Vth tuning using a double gate structure in an ambipolar and the dielectric constant are higher in P(VDF-TrFE-CTFE) in comparison to PTrFE. As a result, this has allowed greater transistor. accumulated electron carrier density at the same gate voltage, In conclusion, we demonstrate a double gate configuration with which might result in the ambipolarity of the SWNT – P(VDFfluorinated top gate dielectrics to obtain desirable device characterTrFE-CTFE) TFTs within the measured voltage range. It is also istics in SWNT TFTs. Hysteresis-free SWNT TFTs were obtained noted that a clear hysteresis is observed especially n-channel under ambient conditions using solution processed PTrFE as a regions, likely due to the extra trapped charges during the top gate dielectric, regardless of sweep rate. We found that the switching of electron/hole conduction and the worse quality devices fabricated in inert nitrogen gas had lower threshold voltof P(VDF-TrFE-CTFE) encapsulation. However, using soluages than devices fabricated in air, while the hysteresis of devices tion-processed high-k P(VDF-TrFE-CTFE) dielectric to achieve fabricated in both environments was small when using PTrFE as ambipolar SWNT TFT operation in ambient atmosphere may the top gate dielectric. Bias stress tests demonstrate that the top prove important for the fabrication of low cost all-printed gate transistors exhibit excellent electrical stability. Additionally, we SWNT CMOS-like logic circuits with ambipolar SWNT observed ambipolar behavior when P(VDF-TrFE-CTFE) was used TFTs.[29] as the top gate dielectric, even in ambient conditions. By applying a bottom gate bias, we were able to tune the threshold voltage of Controlling transistor threshold voltage (Vth) is also very both unipolar and ambipolar transistors, which is highly desirable important for realizing high noise-margin, robust circuits, for transistor operation in robust circuits. that is, a circuit having a high immunity towards the electrical noise that is always present in a system. However, the precise control of Vth remains challenging. Here we Experimental Section show for the first time that we can continuously tune Vth in SWNT top gate TFTs by application of a bottom gate bias in Preparation of SWNTs solution: 5 mg HiPco SWNTs from Unidym were a double gate configuration. In Figure 4, clear Vth shifts can mixed with 5 mg rr-P3DDT in 25 mL toluene and sonicated (Cole Parmer
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www.MaterialsViews.com ultrasonic processor 750 W) for 30 min at an amplitude level of 70%. The solution was then centrifuged (Sorvall RC5C-plus) at 17000 rpm for 1 h at 16 °C. Supernatant was collected for use in fabricating the devices. Preparation of solutions for top gate dielectrics: Both PTrFE and P(VDFTrFE-CTFE) were dissolved in cyclopentanone at a concentration of 50 mg/mL. To ensure good dissolution, PTrFE solution was stirred overnight at 70 °C while P(VDF-TrFE-CTFE) solution was stirred overnight without heating. Fabrication of devices: Heavily doped Si substrates were used for the bottom gate electrodes on top of which 200 nm SiO2 bottom gate insulator with a capacitance of 17 nF/cm2 was thermally grown. Sourcedrain electrodes consisted of a 5 nm titanium adhesion layer followed by 30 nm of gold and were patterned using standard photolithography techniques. 15 drops of SWNT solution was spin coated on the substrates at 2000 rpm for 60 s. The substrates were then annealed at 150 °C for 1 h. Top gate dielectrics were spin coated on top of SWNT films at 500 rpm for 5 s and 2000 rpm for 1 min to obtain films of ∼200 nm thickness. The PTrFE dielectric was then annealed for 30 min at 135 °C and the P(VDF-TrFE-CTFE) dielectric was annealed at 80 °C for 10 min. Finally, 30 nm thick gold top gate electrodes were evaporated through a shadow mask. The schematic of the device structure is shown in Figure 1a.
Supporting Information Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements The authors would like to thank Alessio Marrani from Solvay Specialty Polymers, Italy for providing the PTrFE and P(VDF-TrFE-CTFE) materials. We also thank Dr. Hylke B. Akkerman, Mr. Francisco Gonzales Rodriguez, Mr. Francesco Pedroli, Mr. Mina M.A. Abdelmalek and Dr. Jeremy Feldblyum for helpful discussion. This work was funded by National Science Foundation (Award Number: 1059020 and 1335645) and the Air Force office of Scientific Research (FA9550–12–1–0190). H. W. acknowledges financial support from Link foundation Energy fellowship. Received: February 3, 2014 Revised: March 2, 2014 Published online: May 2, 2014
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Highly Stable Carbon Nanotube Top-Gate Transistors with Tunable Threshold Voltage Huiliang Wang, Brian Cobb,* Albert van Breemen, Gerwin Gelinck, and Zhenan Bao* Single-walled carbon nanotubes (SWNTs) possess ideal properties for thin film transistors (TFTs) such as high charge carrier mobility,[1] solution processability[2,3] and excellent mechanical flexibility.[4] One of the major issues preventing the practical use of SWNTs in electronics is that as-synthesized SWNTs are a mixture of semiconducting and metallic SWNTs. Metallic SWNTs must be removed from these mixtures in order to fabricate high performance TFTs. Recently, a variety of sorting techniques such as density gradient centrifugation,[5] gel chromatography,[6,7] and conjugated polymers sorting[3,8] have been successfully used to separate semiconducting SWNTs from their metallic counterparts. While the TFTs fabricated by these sorted carbon nanotubes demonstrate high mobility and on/ off ratios,[3,7,9,10] challenges still remain for their practical use, including: i) reduction of the operational large hysteresis,[11,12] primarily caused by charge traps at the surface and bulk of gate transistor dielectrics;[13] ii) environmental stability, SWNT TFTs are generally unipolar in air and ambipolar in inert atmosphere,[10] while consistent device characteristics are desired independent of environment; iii) reduction and control of the threshold voltage (Vth) of SWNT TFTs[3,14] preventing the fabrication of robust and low-power circuits. Previously, a few strategies have been attempted to reduce the hysteresis of SWNT transistors such as annealing the device in vacuum,[11] surface treatment of dielectric before deposition,[15] encapsulation of the SWNTs with PMMA,[11] HMDS,[16] spin-on glass,[13] ferroelectric polymer[17] or extra sorting polymers.[12] While these methods can reduce hysteresis to some extent, the long-term bias-stress stability of SWNT TFTs has not been reported. In addition, the control of polarity and the continuous turning of threshold voltage in SWNT TFTs have not been achieved under ambient conditions. In response to the ongoing challenges for SWNT-based TFTs, we fabricated double gate polythiophene-sorted SWNT TFTs by utilizing the Poly(trifluoroethylene) (PTrFE and high-k Poly(vinylidene-trifluoroethylene-chlorotrifluoroethylene), P(VDF-TrFE-CTFE) (Scheme S1), as our top gate dielectrics.
H. Wang, Prof. Z. Bao Department of Materials Science & Engineering Department of Chemical Engineering Stanford University Stanford, CA 94305 E-mail: [email protected] Dr. B. Cobb, Dr. A. van Breemen, Dr. G. Gelinck Holst Centre/TNO High Tech Campus 31, Eindhoven, 5656 AE, Netherlands E-mail: [email protected]
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These polymer dielectrics are chosen for three reasons: i) they exhibit high dielectric constants of ∼10 and ∼25 respectively, ii) fluorinated polymers are resistant to moisture,[18] one of the primary causes of hysteresis,[11] and iii) they both have nearly no polarization-field hysteresis[19] (Figure S1 for PTrFE), and therefore do not induce intrinsic hysteresis. By utilizing PTrFE as the top gate dielectric, we fabricated hysteresis-free TFTs with a threshold voltage around 0 V in ambient conditions. The devices exhibit hysteresis-free operation at different sweep rates at a gate field of 0.5 MV/cm with unipolar device characteristics under both ambient and nitrogen atmospheres. Under a vigorous electrical bias stress test lasting 10000 s, the threshold voltage shifts of our SWNT TFTs are comparable to the recently reported stable organic[20,21] or metal oxide[22,23] TFTs. Interestingly, when high-k P(VDF-TrFE-CTFE) was utilized as the top gate dielectric, we also observed a clear ambipolar transistor behavior, even under ambient conditions. Finally, we demonstrate the capability to tune the threshold voltage of both unipolar SWNT TFTs with PTrFE dielectrics and ambipolar SWNT TFTs with P(VDF-TrFE-CTFE) dielectrics by the application of a second gate bias. The ability to tune the threshold voltage of SWNT TFTs in double-gate structures is important for realizing reliable SWNT logic circuits at large scales.[24] We first explored SWNT top gate TFTs with PTrFE dielectrics. The fabrication process is provided in the Experimental Section (a schematic is shown in Figure 1a). The density of spin coated semiconducting SWNT films sorted by Poly (3-dodecylthiophene-2,5-diyl) (P3DDT) in the device is shown in Figure S2. A typical transfer curve is shown in Figure 1b, where the hysteresis is absent. The gate-induced field is around 0.5 MV/cm for a dielectric thickness of 200 nm. An output curve of the device is shown in Figure 1c, indicating no obvious contact barrier. It was reported that the degree of hysteresis is also dependent on the sweep rate since the charge capture and emission times are different for defect traps at the SWNT-dielectric interface and in the bulk.[13] In our devices, no hysteresis was observed at sweep rates ranging from 0.5 V/s to 10 V/s (Figure 1d), indicating minimal trap sites in this device configuration. A transistor with a more typical SWNT bottom gate device structure without a top gate dielectric was also analyzed under the same voltage for comparison. Examples of the device’s transfer and output curves are shown in Figure 1e and S3, where a relatively large hysteresis is seen. Also notable, the bottom gate device has a lower off-current than the top gate device since there is much less gate leakage current through the thermal SiO2 dielectric. Overall, 24 double gate devices were fabricated and characterized in ambient conditions and the statistics of hysteresis are shown in Figure 1f. Hysteresis is defined as the difference between gate voltages needed to induce an average sourcedrain current, i.e., (ISD,max + ISD,min)/2, between the forward and
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COMMUNICATION Figure 1. Hysteresis of SWNT TFTs with PTrFE top gate dielectric at VSD = −5 V. (a) Schematic device structure of SWNT double gate TFTs (devices shown in this figure have PTrFE as top gate dielectric except for the one Figure 1e) (b) Top gate transfer characteristics of a hysteresis-free double gate SWNT TFT. (c) Top gate output characteristics of a SWNT TFT. (d) Sweep rate dependent top gate transfer characteristics of a SWNT TFT. (e) Transfer characteristics of a bottom gate SWNT TFT without top gate dielectric as a control sample. (f) Histogram of the hysteresis of the 24 devices with PTrFE top gate dielectric.
reverse sweeps.[13] Among the 24 devices, 12 devices were fabricated under a nitrogen atmosphere and another 12 were fabricated in ambient conditions. The devices fabricated in ambient condition showed a more positive, near-zero threshold voltage of −0.14 ± 0.38 V in comparison to the devices fabricated under nitrogen with a threshold voltage of −2.18 ± 0.40 V (Figure S4). Previous work has shown that the Vth shift in SWNT TFTs is mainly influenced by the ambient used for characterization rather than that for fabrication.[10] The more positive threshold voltage for devices fabricated in air is likely due to oxygen doping of the SWNTs or oxygen dipole formation between SWNTs and metal contacts,[25] both of which may promote hole transport at more positive gate voltages. The average hysteresis for devices fabricated in air and nitrogen are similar in our case, being 0.40 ± 0.27 V and 0.35 ± 0.21 V, respectively. This shows that fabrication of devices in air does not introduce additional traps in comparison to the devices fabricated under nitrogen. We attribute the observed small hysteresis for some devices to inhomogeneous defects traps at the dielectric. The charge
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carrier mobility of the devices shown in Figure 1 is around 1 cm2/V s, similar to the mobility of conventional bottom gate devices using the same spin-coated SWNTs and measurement conditions. The mobility of the device might be improved further by rinsing or soaking SWNTs films in toluene to remove the insulating P3DDT. However, this might also remove some SWNTs in the channel. The measurement of hysteresis in our SWNT TFTs serves as a useful starting point to examine their stability. Since TFTs used for driving displays, analog circuitry and power electronics need to be kept “on” or “off” for long periods of time, large bias-stress induced threshold voltage shifts should be investigated. Here, we tested the effects of bias voltage on the threshold voltage of SWNT-PTrFE top gate TFTs up to 10000 s. We applied a gate voltage of ±10 V (0.5 MV/cm) with both source and drain grounded. The application of a source-drain voltage has been reported to reduce the effects of threshold voltage shifts for organic semiconductors since it would generate an electrical field that opposes the gate bias.[26] The bias
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of polycrystalline Si TFTs and organic TFTs.[26,27] These authors attributed this change in threshold voltage to ions drifting near the interface of between the semiconductor and dielectric.[26,27] Overall, both the positive and negative bias-induced threshold voltage shifts observed during SWNT TFT device performance are among the smallest in comparison to other recently reported organic[20,21] or oxide TFTs.[22,23] In addition, the mobilities of the devices remain almost constant as evidenced by the similar slopes of the linear-scale transfer curves (Figure 2a and b) at different biases, indicating that the bias does not induce extra defects or impede charge transport in the SWNTs. Therefore, these results demonstrate that the double gate SWNT TFT structures used here are very promising for the long-term operation of TFTs. The high-k dielectric P(VDF-TrFE-CTFE) was also explored as an alternative to PTrFE for top gate dielectrics. Surprisingly, these devices demonstrated excellent ambipolarity (Figure 3a and b) even when measured in ambient conditions. This in contrast to the unipolar p-type behavior observed in our PTrFE based TFTs. Generally, ambipolarity is observed when SWNT transistors are characterized in an inert atmosphere. They normally exhibit unipolar p-type characteristics in ambient atmosphere, even when coated with dielectrics such as PMMA,[11] spin-on-glass,[13] HMDS,[16] or Al2O3.[25,28] The only
Figure 2. Bias-stress testing of SWNT TFTs with PTrFE top gate dielectric at VSD = −5V. (a) Top gate transfer characteristics of a double gate SWNT TFT under gate bias of +10 V, (b) Top gate transfer characteristics of a double gate SWNT TFT under gate bias of −10 V, (c) Threshold voltage shifts as a function of bias time.
stress results are shown in Figure 2. With the application of a gate bias of +10 V, the threshold voltage increases slightly up to 1 V at 10000 s (Figure 2a,c), as a result of trapping of charges similar as those reported for organic and oxide semiconductor previously.[20,22,26] With a bias gate voltage of −10 V, however, the gate threshold voltage first unexpectedly increased for up to 1 V and then decreased back to almost the original threshold voltage value at around 10000s (Figure 2b,c). The unexpected increase in threshold voltage on applying a negative gate voltage has also been observed previously in the case
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Figure 3. Ambipolar SWNT TFT device characteristics with P(VDF-TrFECTFE) top gate dielectric. (a) Top gate transfer characteristics of an ambipolar SWNT TFT (b) Top gate output characteristics of an ambipolar SWNT TFT.
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Δ th,top = −
C bottom Δ bottom C top
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be observed for both PTrFE and P(VDFTrFE-CTFE) top gate dielectric devices. The shifts are caused by the applied bottom gate bias (Vbottom), which modifies the charge distribution in the channel and shifts the threshold voltage of top gate transistor (Vth, top) by[30]
where Ctop and Cbottom are the top and bottom gate capacitance per unit area respectively. The transfer curve for a TFT with a PTrFE dielectric (Figure 4a) shifts in a manner similar to that of self-assembled monolayer layer double-gate transistors, since there is only one channel formed in the thin SWNT network.[31] It was observed that two channels can form for thicker layer polymer double Figure 4. Tuning the threshold voltage of a SWNT TFT with bottom gate bias at VSD = −5 V. gate devices, which causes a shoulder to (a) Top gate transfer characteristics of a unipolar SWNT TFT using PTrFE as the top gate dielec- appear in the transfer curve.[32] By applying tric at different bottom gate bias (VBG). (b) Top gate threshold voltage shifts as a function of a bias from +30 to −30 V, we can tune the bottom gate bias. (c) Top gate transfer characteristics of an ambipolar SWNT TFT using P(VDF- threshold voltage from −4.3 to +9.3 V conTrFE-CTFE) as the top gate dielectric at different bottom gate bias (VBG). (d) Top gate threshold tinuously (Figure 4b). This wide range of voltage shifts as a function of bottom gate bias for both hole current (p-type threshold) and threshold tuning can be used to achieve high electron current (n-type threshold). noise margin large-scale organic circuits as demonstrated by Myny et al.[33] For the double gate device having P(VDF-TrFE-CTFE) as the top gate exception occurs when HfO2 is used as the top gate dielectric, dielectric, both n-type threshold voltage and p-type threshold in which case they exhibit n-type characteristics.[25,28] This voltage tuning is shown in Figures 4c and d. The Vth can be n-type behavior was attributed to the positive fixed charges introduced during HfO2 deposition, reducing the injection tuned from −1.5 to +2 V for hole current and from 9 to 8.2 V for electron current. This degree of tuning is much smaller barrier for electrons.[25] The reason for not observing n-type compared to our SWNT-PTrFE TFTs as the P(VDF-TrFE-CTFE) behavior in Al2O3-based TFTs was proposed by Franklin dielectric results in a larger top-gate capacitive coupling to the et al. as the more electropositive Al attracts more electrons channel. This work also represents the first demonstration in the oxygen ions.[28] Here, both the amounts of C-F dipoles of Vth tuning using a double gate structure in an ambipolar and the dielectric constant are higher in P(VDF-TrFE-CTFE) in comparison to PTrFE. As a result, this has allowed greater transistor. accumulated electron carrier density at the same gate voltage, In conclusion, we demonstrate a double gate configuration with which might result in the ambipolarity of the SWNT – P(VDFfluorinated top gate dielectrics to obtain desirable device characterTrFE-CTFE) TFTs within the measured voltage range. It is also istics in SWNT TFTs. Hysteresis-free SWNT TFTs were obtained noted that a clear hysteresis is observed especially n-channel under ambient conditions using solution processed PTrFE as a regions, likely due to the extra trapped charges during the top gate dielectric, regardless of sweep rate. We found that the switching of electron/hole conduction and the worse quality devices fabricated in inert nitrogen gas had lower threshold voltof P(VDF-TrFE-CTFE) encapsulation. However, using soluages than devices fabricated in air, while the hysteresis of devices tion-processed high-k P(VDF-TrFE-CTFE) dielectric to achieve fabricated in both environments was small when using PTrFE as ambipolar SWNT TFT operation in ambient atmosphere may the top gate dielectric. Bias stress tests demonstrate that the top prove important for the fabrication of low cost all-printed gate transistors exhibit excellent electrical stability. Additionally, we SWNT CMOS-like logic circuits with ambipolar SWNT observed ambipolar behavior when P(VDF-TrFE-CTFE) was used TFTs.[29] as the top gate dielectric, even in ambient conditions. By applying a bottom gate bias, we were able to tune the threshold voltage of Controlling transistor threshold voltage (Vth) is also very both unipolar and ambipolar transistors, which is highly desirable important for realizing high noise-margin, robust circuits, for transistor operation in robust circuits. that is, a circuit having a high immunity towards the electrical noise that is always present in a system. However, the precise control of Vth remains challenging. Here we Experimental Section show for the first time that we can continuously tune Vth in SWNT top gate TFTs by application of a bottom gate bias in Preparation of SWNTs solution: 5 mg HiPco SWNTs from Unidym were a double gate configuration. In Figure 4, clear Vth shifts can mixed with 5 mg rr-P3DDT in 25 mL toluene and sonicated (Cole Parmer
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www.MaterialsViews.com ultrasonic processor 750 W) for 30 min at an amplitude level of 70%. The solution was then centrifuged (Sorvall RC5C-plus) at 17000 rpm for 1 h at 16 °C. Supernatant was collected for use in fabricating the devices. Preparation of solutions for top gate dielectrics: Both PTrFE and P(VDFTrFE-CTFE) were dissolved in cyclopentanone at a concentration of 50 mg/mL. To ensure good dissolution, PTrFE solution was stirred overnight at 70 °C while P(VDF-TrFE-CTFE) solution was stirred overnight without heating. Fabrication of devices: Heavily doped Si substrates were used for the bottom gate electrodes on top of which 200 nm SiO2 bottom gate insulator with a capacitance of 17 nF/cm2 was thermally grown. Sourcedrain electrodes consisted of a 5 nm titanium adhesion layer followed by 30 nm of gold and were patterned using standard photolithography techniques. 15 drops of SWNT solution was spin coated on the substrates at 2000 rpm for 60 s. The substrates were then annealed at 150 °C for 1 h. Top gate dielectrics were spin coated on top of SWNT films at 500 rpm for 5 s and 2000 rpm for 1 min to obtain films of ∼200 nm thickness. The PTrFE dielectric was then annealed for 30 min at 135 °C and the P(VDF-TrFE-CTFE) dielectric was annealed at 80 °C for 10 min. Finally, 30 nm thick gold top gate electrodes were evaporated through a shadow mask. The schematic of the device structure is shown in Figure 1a.
Supporting Information Supporting Information is available from the Wiley Online Library or from the author.
Acknowledgements The authors would like to thank Alessio Marrani from Solvay Specialty Polymers, Italy for providing the PTrFE and P(VDF-TrFE-CTFE) materials. We also thank Dr. Hylke B. Akkerman, Mr. Francisco Gonzales Rodriguez, Mr. Francesco Pedroli, Mr. Mina M.A. Abdelmalek and Dr. Jeremy Feldblyum for helpful discussion. This work was funded by National Science Foundation (Award Number: 1059020 and 1335645) and the Air Force office of Scientific Research (FA9550–12–1–0190). H. W. acknowledges financial support from Link foundation Energy fellowship. Received: February 3, 2014 Revised: March 2, 2014 Published online: May 2, 2014
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