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Cite this: Phys. Chem. Chem. Phys., 2013, 15, 20611

Fabrication of high performance/highly functional field-effect transistor devices based on [6]phenacene thin films† Ritsuko Eguchi,*a Xuexia He,a Shino Hamao,a Hidenori Goto,a Hideki Okamoto,b Shin Gohda,c Kaori Satoc and Yoshihiro Kubozonoad Field-effect transistors (FETs) based on [6]phenacene thin films were fabricated with SiO2 and parylene gate dielectrics. These FET devices exhibit field-effect mobility in the saturation regime as high as 7.4 cm2 V1 s1, which is one of the highest reported values for organic thin-film FETs. The two- and four-probe mobilities in the linear regime display nearly similar values, suggesting negligible contact resistance at 300 K. FET characteristics were investigated using two-probe and four-probe measurement modes at 50–300 K. The two-probe mobility of the saturation regime can be explained by the multiple shallow trap and release model, while the intrinsic mobility obtained by the four-probe measurement in the linear regime is better explained by the phenomenon of transport with charge carrier scattering

Received 24th August 2013, Accepted 15th October 2013

at low temperatures. The FET device fabricated with a parylene gate dielectric on polyethylene

DOI: 10.1039/c3cp53598c

[6]phenacene FETs in flexible/transparent electronics. N-channel FET characteristics were also achieved

terephthalate possesses both transparency and flexibility, implying feasibility of practical application of in the [6]phenacene thin-film FETs using metals that possess a small work function for use as source/

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drain electrodes.

1. Introduction Field-effect transistors (FETs) based on thin films and single crystals of phenacene molecules—which consist of a W-shaped fused configuration of benzene rings—have attracted much attention owing to their desirable FET characteristics.1–11 The FETs based on thin films and single crystals of picene exhibited field-effect mobilities, or m, as high as 1.4 and 1.3 cm2 V1 s1, respectively.2,6 Characteristics such as O2 sensing and bias-stress in picene thin-film FETs were discovered, and the device performance was improved significantly by controlling the interface between the source/drain electrodes and the picene thin films, as well as between the gate dielectric and the picene thin films.1–7 The characteristics of FET devices based on thin films8,9 and single crystals10 of [7]phenacene were subsequently investigated, in which a

Research Laboratory for Surface Science, Okayama University, Okayama 700-8530, Japan. E-mail: [email protected] b Division of Earth, Life, and Molecular Sciences, Okayama University, Okayama 700-8530, Japan c NARD Institute, Ltd., Amagasaki 660-0805, Japan d Research Center for New Functional Materials for Energy Production, Storage and Transport, Okayama University, Okayama 700-8530, Japan † Electronic supplementary information (ESI) available: The surface morphology and the size of crystallites of [6]phenacene thin films investigated by atomic force microscopy (AFM) and X-ray diffraction (XRD). See DOI: 10.1039/c3cp53598c

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p-channel FET characteristics with m values as high as 0.8 and 3.2 cm2 V1 s1 were reported for thin films and single crystals, respectively.8,10 Recently, we reported excellent p-channel FET characteristics for [6]phenacene thin film FETs, in which the m value is close to 3.7 cm2 V1 s1.11 In this report, the characteristics of a [6]phenacene thinfilm FET were fully investigated. The m value of the saturation regime reaches 7.4 cm2 V1 s1 under a vacuum of 106 Torr. This m value is twice as high as the previous m value of 3.7 cm2 V1 s1 under an Ar atmosphere.11 Thus, the FET performance effectively increased under the vacuum conditions. Temperature dependence of the characteristics of [6]phenacene thin-film FETs is clarified with two-probe and four-probe measurement modes. These results confirm that m of the saturation regime can be explained by the multiple shallow trap and release (MTR) model, while m of the linear regime in four-probe measurement modes follows the power-law in the low temperature region. Furthermore, the [6]phenacene thin-film FET devices are fabricated with a parylene gate dielectric on a polyethylene terephthalate (PET) substrate, and the transparency and flexibility of the FET devices were fully characterized. Finally, n-channel operation of a [6]phenacene thin-film FET has been achieved for the first time using metals with a small work function for the source/drain electrodes.

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2. Experimental

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2.1

Sample preparation

[6]Phenacene was synthesized according to the method described in ref. 12 and 13, and was sublimed to be >99.5% pure under vacuum. SiO2 and parylene were used as the gate dielectrics. The surface of the SiO2 was coated with hexamethyldisilazane (HMDS) to produce a hydrophobic surface, while a 1 mm thick layer of parylene formed on an Au (50 nm or 25 nm)/PET substrate was used as the gate dielectric for flexible devices. [6]Phenacene thin films were 35 nm thick for the SiO2 gate dielectric devices and 60 nm for the flexible devices. The thickness of the Au and Sr source/drain electrodes was 50 and 100 nm, respectively. The Sr source/drain electrodes were also covered with 50 nm of Au. The thickness of the F4TCNQ inserted into the space between the Au electrodes and the thin film was 3 nm. Thin films of [6]phenacene, Au and Sr electrodes, and F4TCNQ were formed by thermal evaporation at 107 Torr. The device structures (top-contact type) are shown in figures. 2.2

was grounded. Negative voltage was applied to VG and VD, except for the measurement in the ambipolar FET device. The two- and four-probe, and the temperature dependent measurements of [6]phenacene thin-film FET with a SiO2 gate dielectric were carried out in the vacuum micro-probe/chamber system with five probes and a liquid He flow cryostat. The FET characteristics were recorded using an Agilent B1500A under vacuum conditions (B106 Torr). For the four-probe measurement, the intermediate voltages between source and drain electrodes, V1 and V2, were simultaneously measured when obtaining the transfer curve (Fig. 1a). The transmission spectrum was recorded using a UV-VIS absorption spectrometer ( JASCO V-670 iRM EX). The surface morphology and the size of crystallites of [6]phenacene thin films were investigated by the atomic force microscope (AFM) and the X-ray diffraction (XRD)

Characterization

The capacitance per area, C0, of SiO2 (400 nm) and parylene (1 mm) was measured using a precision LCR meter (Agilent E4980A), and the C0 values were 8.1 and 3.0 nF cm2, respectively. The C0 that is the capacitance at 0 Hz was estimated by extrapolating the capacitance measured from 20 Hz to 1 MHz. The width W and the length L (L12) for each device are listed in Table 1. The m values were determined from the transfer curves in the saturation and linear regions with the general MOS formula. The FET characteristics of the flexible and ambipolar devices were recorded using a semiconductor parametric analyzer (Agilent B1500A) in an Ar-filled glove box. As seen in the device structures, the drain current ID was measured as a function of the gate voltage VG. The constant drain voltage VD was applied to the drain electrodes, while the source electrode

Fig. 1 (a) Device structure of [6]phenacene thin-film FET with a SiO2 gate dielectric on a Si substrate, and the molecular structure of [6]phenacene. (b) |ID| vs. |VG| curve at VD = 100 V with a logarithm plot as an inset. (c) |ID|1/2 vs. |VG| curve at VD = 100 V and (d) |ID| vs. |VD| curve.

Table 1 Summary of the characteristics of the various types of [6]phenacene thin-film FETs. Superscript notations in the mlin value, 2w and 4w, correspond to the twoprobe and four-probe measurement modes, respectively

Devices

VD (V)

msat (cm2 V1 s1)

mlin (cm2 V1 s1)

[6]Phenacene (35 nm) HMDS coated SiO2 (400 nm)/Si

100

7.4



[6]Phenacene (60 nm) Parylene (1 mm)/Au (50 nm)/black PET [6]Phenacene (60 nm) Parylene (1 mm)/Au (50 nm)/transparent PET [6]Phenacene (60 nm) Parylene (1 mm)/Au (25 nm)/transparent PET [6]Phenacene (60 nm) with Au/F4TCNQ electrodes Parylene (1 mm)/Au (50 nm)/transparent PET [6]Phenacene (35 nm) with Au/Sr electrodes HMDS coated SiO2 (400 nm)/Si p-Channel (negative VG) n-Channel (positive VG)

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|VTH| (V)

W/L (cm cm1) (W/L12 (cm cm1))

off Ion D /ID

69

3.6  107

2w

80

8

3.5  10

80

3.5  108

20



3.9*

20



3.4*4w

140

6.0  101



102

9.9  105

0.102/0.045 (0.102/0.021) 0.102/0.045 (0.102/0.021) 0.102/0.045 (0.102/0.021) 0.050/0.025

140

4.6  101



100

2.3  105

0.050/0.025

120

2

5.7  10



86

6

1.2  10

0.050/0.005

100

2.7



56

2.1  107

0.050/0.005

4

2

80

3.9  10



69

7.2  10

0.050/0.025

80

9.3  103

4.5  103*2W

67

5.8  104

0.050/0.025

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measurements. Details of AFM and XRD results are presented in ESI.†

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3.1

[6]Phenacene thin-film FET with a SiO2 gate dielectric

FET characteristics from the two-probe measurement: the saturation regime mobility. Fig. 1a displays the device structure of the [6]phenacene thin-film FET with a SiO2 gate dielectric. A detailed structural characterization of the [6]phenacene thin film was first presented by Komura et al.11 The absolute drain current, |ID|, curves were plotted as a function of absolute gate voltage, |VG|, as shown in Fig. 1b, where the drain voltage, VD, was fixed at 100 V. From the |ID| vs. |VG| curves obtained at VD = 100 V in the two-probe measurement mode, the |ID|1/2 vs. |VG| curve was plotted in order to evaluate the m value, msat, using the metal-oxide-semiconductor (MOS) FET formula of the saturation regime (Fig. 1c). msat, absolute threshold voltage |VTH|, and the on–off ratio were estimated from the forward |ID|1/2 vs. |VG| curve to be 7.4 cm2 V1 s1, 69 V, and 3.6  107, respectively, which confirms clear p-channel FET characteristics. The m value of 7.4 cm2 V1 s1 for the [6]phenacene thin-film FET is one of the highest for organic thin-film FETs, to the best of our knowledge.14–19 In this study, the FET characteristics were measured under vacuum conditions, in contrast to the previous study that was measured in a Ar-filled glove box.11 The O2 sensing property of the [6]phenacene FET was reported in a previous study.11 Exposing the [6]phenacene thin film FET to O2 led to a drastic increase in |ID| compared with that under vacuum conditions (4.5  102 Torr). This means that the presence of O2 causes the positive contribution to FET performance, while H2O degrades the phenacene FETs.1 Therefore, the FET performance under vacuum of 106 Torr may be improved owing to an elimination of H2O that deteriorates the FET performance. Consequently, it is important to note that the study on O2-exposure or Ar-exposure dependence using the [6]phenacene FET device stored under 106 Torr to eliminate H2O sufficiently is quite interesting, because the higher m may be observed in a dried O2 atmosphere. This study is the next important research subject. The output curves are shown in Fig. 1d. The clear saturation behaviors of |ID| in the high |VD| region, and the linear behaviors in the low |VD| region, were observed, which means that no Schottky-like hole-injection barrier was present between the Au source/drain electrodes and the thin film in the high |VG| region, in addition to the presence of Ohmic contact. The maximum |ID| in the output curves decreases compared with that in the |ID| vs. |VG| curve, this may be because of the bias stress effect induced by a continuous application of VD and VG.11 FET characteristics from two- and four-probe measurements: the linear regime mobility. The |ID| curves plotted as a function of |VG| are displayed in Fig. 2a, where VD is the low energy region and VD = 20 V. The voltages between the two intermediate electrodes and the source electrode, V1 and V2, were recorded in four-probe measurement mode, as shown in

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Fig. 2 (a) |ID| vs. |VG| and |ID|/V12 vs. |VG| curves. (b) V1, V2, and V12 vs. |VG| curves at VD = 20 V, measured using the four-probe measurement mode. (c) Temperature dependence of the four-terminal resistance (R4w) and the two-terminal resistance (R2w). Inset is the plot of Rcontact (which equally R2w  R4w).

the schematic of the device in Fig. 1a. The V1, V2, and V12 (which is equal to V1  V2) at VD = 20 V are plotted in Fig. 2b. The V12 is almost zero at |VG| = 0 V, since VD is primarily applied to the potential barrier between the drain electrode and the channel. The carrier concentration increases as |VG| increases, and the channel resistance is reduced, resulting in an increase and a saturation of the V12 at |VG| > 80 V. The |ID|/ V12 vs. |VG| curve at VD = 20 V is also shown in Fig. 2a. |ID|/V12 refers to the inverse of resistance, 1/R, between the V1 and V2 electrodes, which corresponds to the conductance G. The four-probe mobility in the linear regime, mlin_4w, |VTH|, and the on–off ratio were estimated to be 3.4 cm2 V1 s1, 80 V, and 3.5  108, respectively, from the forward |ID|/V12 curve. The mlin_4w is evaluated with the MOS FET formula in the linear regime, given by:   ID d L12 V12 mlin 4w ¼ ; (1) WCO dVG where C0 is the capacitance per area and L12 is the distance between the voltage probes. The mlin_4w at VD = 20 V is smaller than the msat at VD = 100 V, which generally follows the trend that msat > mlin. In order to compare the four-probe mobility with the two-probe mobility, the two-probe mobility

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in the linear regime, mlin_2w, was evaluated by the following equation:

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mlin

2w

¼

L dID : WCO VD dVG

(2)

The mlin_2w can be as high as 3.9 cm2 V1 s1, which is close to the value of mlin_4w and reflects the intrinsic charge carrier mobility. Since the contact resistance, Rcontact, may affect the difference between mlin_4w and mlin_2w, the two- and four-probe resistances, R2w and R4w, were evaluated at VG = 100 V. The R2w was normalized by a factor of L/L12, in order to compare it to R4w. The temperature dependence of R2w and R4w is shown in Fig. 2c, indicating that the Rcontact (which is equal to R2w  R4w) in this FET device is quite small in the temperature range of 200–300 K, while an increase of the Rcontact is observed in the low temperature region (Fig. 2c, inset). The low Rcontact subsequently reflects a slight difference between mlin_4w and mlin_2w, 3.4 cm2 V1 s1 and 3.9 cm2 V1 s1, respectively, at room temperature. We previously confirmed that the contact resistance of the [7]phenacene thin-film FET is too small8 from the experiment based on the transmission line method, which is consistent with the results arising from the [6]phenacene thin-film FET. Therefore, the most impressive feature of this system is the contact resistance being too small in thin-film FETs based on phenacene-type molecules. Temperature dependence of the mobility. Temperature dependencies of msat and mlin_4w in the [6]phenacene thin-film FET are shown in Fig. 3a. The mlin_4w value was evaluated from the forward transfer curve at VD = 20 V. Additionally, the msat value determined by the forward transfer curve at VD = 100 V was also plotted, which was more than twice as high as mlin_4w at 300 K. These temperature dependencies were analyzed by the MTR model:1,2,20–26 mðTÞ ¼

m0  ; Nt et  ev 1þ exp Nv kB T

(3)

where T, m0, Nt, Nv, and kB are the temperature, intrinsic mobility, the total density of states (DOS) for the shallow trap states, the effective DOS at the valence band edge, and the Boltzmann constant, respectively. The m0 corresponds to m(T) in a trap-free FET device, i.e., intrinsic crystal mobility. The et and ev refer to the energy level of the trap state and the edge energy of the valence band, respectively. Therefore, et  ev corresponds to the trap depth. The values of m0, Nt/Nv, and et  ev were determined to be 18 cm2 V1 s1, 0.42, and 33 meV, respectively, from the temperature dependence of msat; while m0, Nt/Nv and et  ev were 4.6 cm2 V1 s1, 0.24 and 34 meV, respectively, from the temperature dependence of mlin_4w. These m0 values obtained from the temperature dependence of msat are quite high relative to m0 = 4.3  101 cm2 V1 s1 for the picene thinfilm FET, which was evaluated through the temperature dependence of msat in two-probe measurement mode.2 The large m0 values imply the formation of more extended p-conduction network relative to picene. Furthermore, the value of Nt/Nv (0.42) for the two-probe measurement was consistent with the

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Fig. 3 (a) Temperature dependence of msat and mlin_4w in [6]phenacene thin-film FETs. The msat values were evaluated from the transfer curves in the saturation region at VD = 100 V, measured using the two-probe measurement mode; while mlin_4w were evaluated from the transfer curves in the linear region at VD = 20 V, measured using the four-probe measurement mode. The solid lines refer to a fitting line using the MTR model. The inset displays the linear plots of mobility vs. temperature. (b) Logarithm plot of mlin_4w vs. temperature with fitting lines using the MTR model and the power-law.

Nt/Nv value of organic thin-film FETs (101–102),24,25 and was quite different to the Nt/Nv value of single crystal FETs (4  106).26 These results confirm that the channel region of the [6]phenacene thin films contains a relatively large number of trap states. The et  ev, which was 33 meV, for [6]phenacene FETs is smaller by one order of magnitude than the corresponding values for the picene thin-film FET (180 meV)2 and the [7]phenacene thin-film FET (310 meV).8 It is important to note that although the temperature dependence of mlin_4w was analyzed with the MTR model, this model does not completely reproduce the experimental results, especially at low temperatures, as shown in Fig. 3a. In contrast to the MTR model, the function of the power-law, mlin_4w p T a, exhibits a good fit to the data, with a E 1.5 (Fig. 3b, solid line). The doped inorganic materials, with the donor or acceptors forming the discrete energy levels within the band gap, exhibit a decrease in mobility with respect to decreasing temperature following the expression m p T1.5,27 because the scattering of the charge carriers increases as a result of the ionized donor and acceptors. Additionally, for the organic molecular crystals with disorders and defects, the trap states form a continuous distribution, suggesting the presence of a large amount of the active scattering centers, such as ionized defects. The mobile carriers are scattered by charged defects at low temperature,

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resulting in a decrease in mobility as the temperature decreases. Therefore, the mlin_4w values exhibit the intrinsic transport property, in which the transport is fundamentally explained using the MTR model, but the scattering of charge carriers may occur at low temperatures, following the power-law. This behavior is expected since the channel region contains a relatively large number of trap states in the [6]phenacene thin films, which is obtained from the MTR model fitting. We were able to clarify the transport mechanism of the [6]phenacene thin-film FET. The temperature dependence of msat in the [6]phenacene thin-film FET follows the MTR model, which is consistent with the general results of the FET device exhibiting a m value of 1–10 cm2 V1 s1. These results may be well explained by the MTR model,1,2,8 while the temperature dependence of mlin_4w follows the power-law in the low temperature region, in which the scattering of the charge carrier may have occurred because of the traps in the sample. 3.2 Flexible [6]phenacene thin film FETs with a parylene gate dielectric The device structure of the flexible FETs based on [6]phenacene thin films which are made on black (thick) and transparent (thin) PET substrates is shown in Fig. 4a, where the gate dielectric is a 1 mm thick layer of parylene. These FET devices are also flexible, as shown in the bottom left photograph of Fig. 4a. The transfer characteristics of the flexible FET devices on both PETs are shown in Fig. 4b and c, which were measured in the two-probe measurement mode. msat, |VTH|, and the on– off ratio were determined to be 6.0  101 cm2 V1 s1, 102 V and 9.9  105, respectively, for black PETs, as a result of the forward transfer curves in the saturation regime (VD = 140 V). msat, |VTH|, and the on–off ratio were 4.6  101 cm2 V1 s1, 100 V and 2.3  105 for the transparent PET. The msat values,

Fig. 4 (a) Device structure of the [6]phenacene thin-film FET with a parylene gate dielectric on a PET substrate. Photographs of the flexible device are shown in (a). |ID| vs. |VG| curves at VD = 140 V of the [6]phenacene thin-film FET with parylene gate dielectrics on (b) black and (c) transparent PETs with logarithm plots as an inset. (d) |ID| vs. |VD| curve of the [6]phenacene thin-film FET with a parylene gate dielectrics on a transparent PET.

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4.6  101 through 6.0  101 cm2 V1 s1, for the flexible FET devices are still smaller by an order of magnitude than the msat value for the [6]phenacene FET fabricated on SiO2/Si substrates (non-flexible device), which was 7.4 cm2 V1 s1. The hysteresis of the transfer curves is hardly observed, relative to non-flexible devices. In Fig. 4d, the output curves exhibit concave behavior in the low |VD| region, which implies the presence of a carrierinjection barrier between the source/drain electrodes and the thin film. This may originate from the worse contact between the source/drain electrodes and the thin film, because of the rough surface morphology (see ESI†). A clear saturation behavior when |VD| > 20 V is observed. The transmission spectrum of Au (25 nm)/[6]phenacene (50 nm)/parylene (1 mm)/Au (25 nm)/transparent PET substrates is shown in Fig. 5a, in order to investigate the transparency in the portions containing all elements of the FET device. As shown in Fig. 4, the thickness of the Au is reduced from 50 nm to 25 nm. The transmission is reduced to 80% in the range of 350–1000 nm, but it is still recognized as transparent. The transfer characteristics of the [6]phenacene flexible FET with 25 nm thick Au electrodes were measured, as shown in Fig. 5b; and msat, |VTH|, and the on–off ratio were determined to be 5.7  102 cm2 V1 s1, 86 V and 1.2  106, respectively. The msat value is smaller than that of the flexible FET devices with 50 nm thick Au electrodes (4.6  101 cm2 V1 s1) since the contact between the Au electrodes and the gate dielectric was unstable for devices with thinner Au electrodes, and the high |VG| and |VD| could not be applied, resulting in the lower msat. However, the passable mobility and the on–off ratio were maintained as the flexible FET devices became transparent. Fig. 6a displays the schematic of the [6]phenacene thin-film FET with a parylene gate dielectric on transparent PET substrates, with 2,3,5,6-tetrafluoro-7,7,8,8-tetracyanoquinodimethane (F4TCNQ) inserted into the interface between the source/drain electrodes and the thin film. The transfer and output curves are shown in Fig. 6b and c. msat, |VTH| and the on–off ratio were determined to be 2.7 cm2 V1 s1, 56 V and 2.1  107, respectively, as a result of the transfer curves in the saturation region (VD = 100 V). The m value was greater than that of the flexible FET devices that did not include the F4TCNQ insertion (Fig. 4). The F4TCNQ insertion is effective with respect to the output curves in the low |VD| region, i.e., the |ID| linearly increases from |VD| = 0 V, which

Fig. 5 (a) Transmission spectrum of Au (25 nm)/[6]phenacene (50 nm)/parylene (1 mm)/Au (25 nm)/transparent PET substrates. (b) |ID| vs. |VG| curve at VD = 120 V of the flexible FET with Au (25 nm) electrodes. Inset shows a photograph of the flexible device.

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Fig. 6 (a) Device structure of the [6]phenacene thin-film FET with a parylene gate dielectric on a transparent PET substrate into which F4TCNQ is inserted at the interface between the source/drain electrodes and the thin film. A photograph of the device is shown in (a). (b) |ID| vs. |VG| curve with a logarithm plot as an inset and (c) |ID| vs. |VD| curve.

estimated to be 4.5  103 cm2 V1 s1, 67 V, and 5.8  104, respectively, with MOS formula in the linear regime. Alternatively, the transfer characteristics of the p-channel region can be regarded as the normal measurement (application of negative VD and negative VG). Therefore, the p-channel transfer characteristics (left side of Fig. 7b) can be analyzed with the MOS formula in the saturation regime. msat, |VTH|, and the on–off ratio for the p-channel operation were 3.9  102 cm2 V1 s1, 69 V and 7.2  104, respectively. Thus, the p-channel m value is much smaller than the m value for the [6]phenacene thin-film FET with Au electrodes (7.4 cm2 V1 s1), which was caused by the large carrier-injection barrier height (eF = 2.5 eV) between the Sr electrodes, and the energy level of highest occupied molecular orbital (HOMO) (eHOMO = 5.5 eV).11 Nevertheless, the n-channel operation of the [6]phenacene thin-film FET is significant for the future application of [6]phenacene FETs toward complementary MOS (CMOS) logic circuits, in which both p-channel and n-channel FETs are indispensable.

4. Conclusions behaves differently than the output curves of the flexible FET devices that did not include the F4TCNQ insertion (Fig. 4d). 3.3 Ambipolar FET characteristics of the [6]phenacene thin-film FET with a SiO2 gate dielectric Finally, we attempted to fabricate the n-channel [6]phenacene thin-film FET with Sr electrodes, and the device schematic is shown in Fig. 7a. The work function of Sr is 2.5 eV,28 which corresponds to a Fermi energy, eF, of 2.5 eV, which is close to the energy level of lowest unoccupied molecular orbital (LUMO) of [6]phenacene, (eLUMO = 2.4 eV), relative to eF of Au (5.1 eV).11 These values suggest the possibility of n-channel operation in a [6]phenacene FET containing Sr electrodes. The |ID| vs. |VG| curves measured at VD = 80 V are shown in Fig. 7b, in which the p-channel (applying negative VG) and n-channel (applying positive VG) operations are both observed. VGS (which equals VG  VS) and VGD (which equals VG  VD) at VG = 80 V and VD = 80 V correspond to 80 V and 160 V, respectively, which is actually different from VGS (80 V) and VGD (0 V) in the normal n-channel measurement mode at VD = 80 V. Therefore, the n-channel operation shown in Fig. 7b was achieved with a very high VG, where the saturation of ID should not emerge as a result of non-vanishing VGD. The values of mlin_2w, |VTH|, and the on–off ratio for the n-channel operation were

In conclusion, high-performance [6]phenacene thin-film FETs were fabricated and fully characterized. We have summarized the parameters of the [6]phenacene thin-film FETs obtained through this work in Table 1. First, the FET performance of the [6]phenacene thin-film FET was characterized by two-probe and four-probe measurement modes, and an extremely high msat (which was equal to 7.4 cm2 V1 s1) was recorded in the twoprobe measurement mode, which is one of the highest recorded values for organic thin-film FETs, to the best of our knowledge. Second, the temperature dependence of m was investigated through msat and mlin_4w measurements. The msat follows the MTR model and the m0 is quite high, which suggests a high p-conduction network in the [6]phenacene thin films, while the mlin_4w follows the power-law function in the low temperature region as a result of an increase of the charge carrier scattering. Therefore, the intrinsic mobility may be better explained by the phenomenon of transport with charge scattering. Third, flexibility and transparency were added to the [6]phenacene thin-film FETs by using a parylene gate dielectric and a PET substrate. Finally, n-channel operation was observed for the [6]phenacene thin-film FET with Sr source/drain electrodes, implying a drastic reduction of the electron injection barrier as a result of the eF of Sr being close to the LUMO of [6]phenacene. The experimental results obtained from these studies are significant for the production of practical/high-performance FET devices and logic gate circuits based on phenacene-type organic molecules.

Acknowledgements

Fig. 7 (a) Device structure of an n-channel operated [6]phenacene thin-film FET. A photograph of the device is shown in (a). (b) |ID| vs. |VG| curves at VD = 80 V.

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This study is partly supported by Grant-in-aid (23684028, 22244045, 24654105, 24550054) of MEXT, by the program to disseminate tenure tracking system in Japan Science and Technology Agency (JST), by the LEMSUPER project ( JST-EU Superconductor Project) and ACT-C project in JST, by the

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highly functional field-effect transistor devices based on [6]phenacene thin films.

Field-effect transistors (FETs) based on [6]phenacene thin films were fabricated with SiO2 and parylene gate dielectrics. These FET devices exhibit fi...
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