Ultrasonics 59 (2015) 79–85

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Half bridge topology 500 V pulser for ultrasonic transducer excitation Linas Svilainis ⇑, Andrius Chaziachmetovas, Vytautas Dumbrava Department of Electronics Engineering, Kaunas University of Technology, Studentu str. 50, LT-51368 Kaunas, Lithuania

a r t i c l e

i n f o

Article history: Received 10 November 2014 Received in revised form 22 January 2015 Accepted 25 January 2015 Available online 4 February 2015 Keywords: Ultrasonic measurements High voltage pulser Half bridge pulser Transducer excitation

a b s t r a c t Application of half bridge topology for ultrasonic transducer excitation using long pulse trains is presented. The novelty of the approach is the high speed solution for a high side drive. A commercially available high speed digital isolator and a high speed MOSFET driver were combined to give the possibility to deliver fast driving signals to a high side N-channel MOSFET. The experimental investigation indicates that the output amplitude of the fundamental harmonic can reach 624 Vp–p for light loads and 552 Vp–p when driving 50 X loads. The operation frequency at such voltages can reach 10 MHz for unloaded or 50 X load condition and 6 MHz when driving capacitive 3000 pF loads. The output impedance is 13 X for voltages below 500 Vp–p and 16–26 X for voltages 500 Vp–p and above. Ó 2015 Elsevier B.V. All rights reserved.

1. Introduction The design of the high voltage pulser for ultrasonic transducer excitation is a challenging task when high voltage and relatively high frequency range is considered. Piezoelectric transducer is the most common type thanks to its simplicity, sensitivity and price. It exhibits capacitive load. Transducer excitation in ultrasonic imaging is usually performed using high voltage spike or single rectangular pulse [1,2]. The inspection of the composite materials requires high energy signals with frequencies up to 5 MHz [3]. Low frequencies can go down to 1 kHz when testing concrete [4]. Sonoporation [5] involves the usage of ultrasound to deliver therapeutic/genetic compounds into target cells. Such experiments would need long tonebursts. Up to 500 Vp–p output is required in order to reach high acoustic pressures [5]. The frequency used is based on contrast agent resonant frequency and covers a wide range: from 20 kHz up to 5 MHz frequencies [5]. Arbitrary pulse trains are needed in order to study swept frequency and random frequency effects. Then there is a need for 1 kHz to 5 MHz pulser capable to produce rectangular pulse trains or tonebursts up to 500 V into piezoelectric transducer or 50 X load. Plenty of publications exists that are offering topologies for high voltage pulse generation [1,2,6–8]. Unfortunately, these topologies are intended for single pulse production and are not capable of long low frequency pulse trains generation or are not efficient. Capacitance of the transducers can reach 3000 pF which will alter the bandwidth of the pulser. This effect will be severe for the pulsers intended for a single pulse excitation, where only one front is

⇑ Corresponding author. Tel.: +370 37 300532; fax: +370 37 352998. E-mail address: [email protected] (L. Svilainis). http://dx.doi.org/10.1016/j.ultras.2015.01.014 0041-624X/Ó 2015 Elsevier B.V. All rights reserved.

steep. Capacitive load also reduces the efficiency of excitation since the energy that is not consumed by transducer is fed back to the pulser. This is not the issue when short excitation pulses are used since energy per pulse is low. But average power dissipated in pulser circuit can become large when long tonebursts or spread spectrum pulse trains are employed. For this reason, commercial pulsers are usually specified for resistive load, are bulky and expensive [9–11]. Capacitance reduction can be achieved by matching circuits [12] but high impedance of the circuit could remain. Typically, the transducer capacitance does not exceed 500 pF. When driving such light loads intrinsic losses of the pulser dominate. If the energy dissipated in the pulser circuit is minimised, then the size of the pulser can be reduced. Such pulser is reported in [13]. It can operate down to low frequencies, produce up to 1 kV pulses and is able to produce long tonebursts. Nevertheless, its operation frequencies are limited to 1 MHz due to high side driver speed limitations. Another group of topologies [14–19] uses P- and N- channel MOSFETs, can operate up to 60 MHz and produce long pulse trains; it poses low intrinsic losses but is not able to produce high voltage excitation (maximum 240 Vp–p). Transformer push–pull topology offers an efficient MOSFET drive, can achieve high frequencies, offer low intrinsic losses but the lower end of operation frequencies is limited to 0.5 MHz [20,22]. The aim of the presented design was to develop the pulser suitable for up to 500 Vp–p rectangular pulse trains generation into capacitive or resistive load over 1 kHz to 5 MHz bandwidth. Pulser output amplitude must be stable when the load is changed from light load (open or less than 500 pF) to highly capacitive (3000 pF) or 50 X [23]. It must ensure minimal losses when running under light loads.

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2. Pulser design A conventional pulser (Fig. 1) contains one switch to produce the leading edge and resistor pull-up to produce the trailing edge [1,2]. The circuit is extremely simple: leading edge of the pulse is steep and produces wideband response. Therefore, such excitation circuit became a standard in ultrasonic equipment. This topology is not suitable for pulse trains generation: pull-up resistor value has to be decreased in order to get fast response for trailing edge. Then it will consume large power when the switch is on. Such losses can be tolerated when the pulse duration is short. As it was mentioned above, the pulser is aimed for high voltage excitation from 5 MHz down to 1 kHz. Consequently, topology with two active elements is needed. One element is responsible for pulling up (positive pulse) and another element should pull down [13].

2.1. Topology selection Driving of the low side MOSFET is easy: a variety of suitable Nchannel MOSFETs and the corresponding drivers exists. The problem lies in driving the high side switch. Transformer push–pull topology is a suitable solution since both MOSFETs are N-channel and are referenced to ground [20,22]. Unfortunately, the transformer size can become large here if operating frequencies below 1 MHz are required. The most attractive solution for a high side drive is to use Pchannel MOSFET. The main advantage of P-channel MOSFET is the simplified gate drive topology for high-side switch. The main disadvantage of this device is a high drain–source resistance Rds(on) in comparison with the N-channel device. Also, the device switching speed is low due to increased gate charge. Circuits for coded excitation using P- and N-channel MOSFETs have been suggested [14,15] for small transducers (i.e. phased array) and voltages below 100 V. Yet, higher voltages and longer pulse trains with high current output are needed for the tasks discussed above. Half bridge (totem-pole) topology using two N-channel MOSFETs was suggested in [13] for frequencies below 1 MHz. This design uses a floating high-side driver IC which is commercially available. Unfortunately, commercial high side coupling circuits are slow: the propagation delay is more than 100 ns [13]. Though suitable for low frequency ultrasound [21], upper operation frequency of such circuitry is limited to a few MHz. Better results are obtained when transformer gate drive is used in half bridge topology [24]. However, transformer magnetising inductance limits the lower frequencies. Increasing the magnetising inductance is not the solution since this would increase the leakage inductance hence the upper achievable frequencies. The circuit suggested in [25] allows for higher pulse durations using diode and additional transistor. Unfortunately, such circuit would increase the available gate pull-down impedance hence the dV/dt immunity of the output MOSFET [26]. The half bridge pulser presented in [27] was able to achieve 2.7 MHz operation. Again, limitation is the speed of the high side MOSFET driver. Nevertheless, half bridge topology seems the suitable topology if frequencies below 1 MHz are considered. High voltage supply R2

Input

C1 Output M1

D1

But existing commercial high side drivers are slow and do not offer significant gate drive current to achieve dV/dt immunity [26] and high speed switching.

2.2. Circuit design Half bridge topology was proposed for the pulser (Fig. 2). It must be noted that driving of the high side switch is complicated: source of the N-cannel MOSFET floats at a high slew rate. A special high speed driver and floating +12 V power supply have to be derived. The novelty of the approach is that a high-speed digital isolator ISO721 (50 V/ns maximum slew rate) was used to deliver the logic signal into the floating high side driver. Another improvement is that the bootstrapped [13] power supply was replaced by an isolated DC/DC converter LME1212SC to ensure down to DC operation of the pulser. Two IXFH10N80Q N-channel 800 V power MOSFETs were used as low and high side switches. This MOSFET has 30 A peak drain current IDpeak and 1.1 X RDS. Such current according to [13] is sufficient to ensure 11 MHz maximum operating frequency for 3000 pF load. The resistance in the switch path can be up to 6 X because it is the current that mostly defines the ramping speed. Resistors R2 and R1 were added to further decrease the di/dt stress on MOSFETs and reduce the output ringing. The actual operating frequency will be lower due to the limitations in the driving circuitry and MOSFET interaction. A high-speed MOSFET driver EL7155CS was used. This type of driver has separate sourcing and sinking outputs which are essential to keep the MOSFET dV/dt immunity and switching speed. Half bridge is well known in motor drive and switched mode power supply applications where the load is inductive. The dead time between the turn on and turn off is inserted in order to reduce the cross-conduction losses here. This mode is addressed as zero voltage switching [28]. Application of the half bridge in the ultrasonic pulser is different since the load is usually capacitive. Output voltage remains on drain–source clamps due to the capacitive load. In case of the inductive load the inductor current is responsible for the removal of the remaining carriers from the drain–source channel of the MOSFET which is being turned off. In analysed case, this charge remains even under light load or open condition and has to be consumed by complementary MOSFET which is being turned on. Unintentional dV/dt turn-on of the not conducting MOSFET can occur if ramping is too fast. The sink output of the driver was directly connected to the gate to ensure the dV/dt immunity. The sourcing output was connected through resistor R3, R4 in order to limit the slew rate of the MOSFET to the specified dV/dt. Additional dead time was envisaged for high side and low side MOSFET drive in order to ensure that MOSFET gate is biased to switch off before the turn-on of the opposing switch. Driving signals were derived in CPLD (Complex programmable logic device) M4A3. Dead time between gate driving pulses [20] was introduced using internal gate delay. The approximate cost of the components (printed circuit board and enclosure box excluded) is 47 EUR which is significantly less than the cost of the commercial pulsers. The size of the printed circuit board is 100  65 mm.

3. Experimental investigation RL

Fig. 1. Conventional pulser topology with one active element.

The pulser was manufactured according to Fig. 2 and an investigation of the performance was carried out. The experimental investigation included PSPICE simulation (OrCAD PSpice A/D 9.1).

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+12V

U1 LME1212SC Vin+ Vout+

U2 ISO721M

In

Gnd1 V1

High Side Driv e

Floating +12V R2

Vout-

Gnd2 V2

Vin-

HV

H

R3

Out L U3 EL7155CS

M2 IXFH10N80Q Y1 Transducer

GenOut +12V OutH Input

In

Low Side Driv e

OutL

U4 M4A564/32

H

R1 R4

L U5 EL7155CS

M1 IXFH10N80Q

Fig. 2. Proposed pulser circuit is using half bridge topology.

3.1. Experimental setup The structure of the instrumentation used in the experiments is presented in Fig. 3. The whole system is synchronised from single 100 MHz frequency reference frequency source. A high-speed USB bridge CY68013A was used to control the data acquisition process. Pulser code SRAM was uploaded with ones and zeros sequences representing a toneburst with duration of 10 periods of fundamental frequency. Low level output from pulser SRAM was fed to pulser input. Pulser output was loaded by 50 X, 470 pF or 3000 pF load or left open. The length of the coaxial connections was kept short (direct ‘‘T’’ or ‘‘I’’ type BNC adapters). Load signal was routed into a high input impedance 100:1 divider. The divider was manufactured using 5 kX to 50 X matching pad design. High pulse load resistors (CMB 0207 from Vishay) were used in the divider. The divider was carefully calibrated by taking AC response using a sinusoidal continuous wave signal source Rohde&Schwarz SMC100A signal generator and Yokogawa DLM 2054 mixed signal oscilloscope. RMS value reported by oscilloscope and AD converter were noted and the ratio of the two was taken as a transmission coefficient of the divider at the considered frequency. 10 kHz to 30 MHz frequency range was measured. Measured AC response of the divider is presented in Fig. 4. This measured response was used to compensate the measured AC pulser of the pulser. It can be seen that AC response is stable within 0.5 dB in frequency range 10 kHz to 30 MHz. The purpose of the divider is to register the pulser output signals with minimal

load of the pulser output. The divider was succeeded by programmable attenuator containing discrete 3 dB, 6 dB, 10 dB and 20 dB attenuation stages. High pulse load resistors of the same type (CMB 0207 from Vishay) were used to construct ‘‘P’’ type attenuator stages. Switching between stages is performed using G6S-2F signal relay. Measured AC response (using Rohde&Schwarz FSH8 network analyser) of the attenuator was flat to 0.1 dB in frequency range 10 kHz to 30 MHz. Output of the programmable attenuator is supplied to analog-to-digit (AD) converter via antialiasing filter (third order Butterworth LP filter with 33 MHz cut-off frequency). AD converter includes a 10 bit AD9214 which is streaming its output to IS61LV25616 SRAM (Static random access memory) controlled by M4A3128/64 CPLD. Readout is via same CY68013A USB bridge. Both pulser SRAM and AD SRAM use the same 100 MHz reference clock 501JCA100M000DAF (20 ppm stability, 25 ps jitter). High voltage power source is based on a high voltage power module HVP0.5P which is controlled via USB using FT232RL and MSP430F1612. 3.2. Intrinsic losses optimisation The circuit was simulated in order to optimise the gate resistor. The model for IXFH10N80Q was produced by modifying

-46

Pulser code SRAM

Divider 100:1 5kΩ->50Ω

Pulser Load

Sync. State machine

Reference clock, 100MHz

AD converter w buffer SRAM

High voltage power source

High speed USB bridge

Programm. attenuator

Transmission (dB)

Transmission: ADC+antialiasing filter+100:1 divider -47

-48

USB Host PC

USB Fig. 3. Instrumentation used for pulser performance investigation.

-49 0.05

0.1

1

10

Frequency (MHz) Fig. 4. Measured AC response of the 100:1 divider.

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D DGD DG RGS 6

RDS 1

M1 NMOS1

M2 NMOS2

G DSD DRV CG 2050pF

RS 0.0001 ETH 0.9Vdc LS 10nH

S Fig. 5. MOSFET model circuit used in simulation.

180

Gate drive resistor: 0 1 2 3 4 5 6

0.1

160 140

1 120

2

EPP ( J)

IXFA4N60P3 device model. See Fig. 5 for MOSFET model used in simulation. Intrinsic MOSFETs used classical NMOS LEVEL 1 model with L = 0.5e6W = 11e6 for M2 and L = 0.5e6, W = 7e6 for M1. The rest of parameters were the same: IS = 1e32, VTO = 4.65, LAMBDA = 5.0e03, GAMMA = 10, KP = 0.55. Diode DGD model was using CJO = 400.0e12, M = 0.6871, VJ = .9905, N = 8. Diode DSD had following parameters: IS = 337.88e9, N = 1.9146, RS = 5.6080e3, IKF = 1.8749, CJO = 3.0749e9, M = 0.7801, VJ = 0.3905, ISR = 5.4280e9, BV = 800, IBV = 25.879e3, TT = 40.78e9. Open circuit load condition was used in simulations. The current flowing to MOSFET M2 drain ID was measured together with VHV, high voltage power supply in point HV. Instant power PHV consumed from a high voltage power source was obtained by multiplying them. Energy consumption was obtained by integrating instant power over time. There is no energy consumption from high voltage source when MOSFET M1 is conducting. This repeats every period of the toneburst. Energy difference at these points over one period represents the energy per pulse consumption (EPP, at HV set to 500 V, Fig. 6). It was found that 5 X resistor is optimal for ringing suppression. It produces 14 V/ns pulser output slew rate which is close to maximum specified dV/dt for IXFH10N80Q (20 V/ns). Another purpose of this resistor is to introduce the dead time between the high and low transitions of the output. Charging of the gate is slowed down due to resistor R3, R4. Gate discharge is fast thanks to the low impedance of the pull-down circuit. Therefore, MOSFET is turned off before the opposing MOSFET turns on. Fig. 6 might be misleading, causing assumption that further increase of the dead time or increase of gate drive resistance can reduce the switching losses. Explanation of what is happening with gate drive resistance increase can be found in Fig. 7. Increase of the gate drive resistance slows down the gate drive and the output signal slew rate. Output pulse duration and swing amplitude are decreasing. Therefore output is not at full swing. MOSFETs parasitic output capacitance COSS is nonlinear: it is more than 3000 pF at VDS 0 V and mere 172 pF at VDS 25 V. For M1 COSS is in direct proportion to output voltage, for M1 this relation is opposite. This means that if output is not reaching 0 or VHV, then equivalent MOSFET capacitance (parallel connection of COSS for M1 and M2) is reduced. So is the EPP, but at the expense of reduced output. In order to keep output at maximum available slew rate must be

100

3

4

80 60 40

5

20

6

0 0

10

20

30

40

50

60

70

80

Dead time (ns) Fig. 6. Energy per pulse consumption vs. dead time of the gate driving pulse (for 100 ns output pulse duration, correspond to 50% duty cycle of 5 MHz toneburst signal) obtained by simulation.

265

@ 3000pF load

Fundamental harmonic (V)

82

260

255

250

245

240 0

2

4

6

8

Gate resistance R3 R4 ( ) Fig. 7. Output fundamental magnitude drop due to increased gate drive resistance.

high. Yet, this causes the switching losses (EPP) increase. Dead time and asymmetry in gate drive resistances are dedicated to keep the EPP and output swing optimal. The final optimisation (Fig. 8, HV set to 500 V) was done using an assembled device, altering the amount of internal gates in delay chain. Energy per pulse consumption was evaluated by measuring the power PHV consumed at node HV (refer Fig. 2) and average number of pulses using technique presented in [13]. Energy per pulse (EPP) was calculated by measuring the average power consumption PHV from high voltage power source and dividing it by pulse repetition frequency PRF and number of periods in toneburst N:

Epp ¼

PHV ; PRF  N

ð1Þ

Adverse effect of the dV/dt turn on can be seen at small dead time values: power consumption rises rapidly. Both the dead time duration and the gate resistor value were optimised. It can be seen that 4–5 X gate resistor and 85 ns driving pulse duration (15 ns dead time) are optimal to reduce the switching losses in unloaded condition. Such dead time value was stored permanently in CPLD. 4.7 X gate resistor is optimal: dV/dt turn-on is reliably managed and output swing drop is still acceptable.

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Fig. 8. Experimentally obtained energy per pulse amount vs. dead time of gate pulse.

Fig. 9. Pulser output signals at 50 X load.

3.3. Voltage measurement technique Pulser output signals were recorded using toneburst mode with burst frequency fb varying from 0.1 MHz to 10 MHz in order to investigate the frequency response. Sine and cosine function was fit to the signal y1 . . . ym, sampled at time instances t1 . . . tm using fs = 100 MHz to extract the fundamental harmonic of this toneburst:

PM PM m¼1 ½cosð2pf b t m Þ  ym  m¼1 ½sinð2pf b t m Þ  ym  Vc ¼ P ; V ¼ : s PM 2 2 M ½cosð2 p f t Þ b m m¼1 m¼1 ½sinð2pf b t m Þ

ð2Þ

Then the magnitude of the fundamental harmonic fb was obtained as:

Vc ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V 2c þ V 2s :

ð3Þ Fig. 10. Pulser output signals at capacitive load.

3.4. Output impedance measurement technique Pulser output impedance was measured using the modified procedure described in standard EN 12668-1 [23]. The impedance was obtained by taking two output voltages measured at 50 X (V50) and 75 X (V75) load:

Zo ¼

50  75  ðV 75  V 50 Þ : 75  V 50  50  V 75

ð4Þ

Voltage values V50 and V75 were obtained by using the SWC, Eqs. (2) and (3). 3.5. Performance investigation results Examples of the pulser output signal when the high voltage power supply is 500 V and toneburst frequency is 5 MHz are presented in Figs. 9 and 10. The analysis of the Fig. 9 reveals that the rise and fall times are sufficient to ensure 16 MHz frequency at 50 X load and Fig. 10 indicates that 6 MHz can be attained at capacitive, 3000 pF load conditions:

f max ¼

1

p  tr

;

ð5Þ

where tr is the rise/fall front duration and fmax is the maximum achievable frequency.

With the high voltage power supply set to 500 V, the output swing is 440 Vp–p on 50 X load and 500 Vp–p on capacitive, 3000 pF load. Slight oscillations can be noted after leading and trailing edges which do not affect the final performance. It must be noted that 470 pF load is a good approximation of the 5 MHz transducer (C543-SM, Olympus) load (refer Fig. 11). AC response of the magnitude of the fundamental harmonic obtained using Eqs. (2) and (3) for 50 X, open and 3000 pF load conditions is presented in Fig. 12. With high voltage set to VHV it could be expected that the peakto-peak amplitude of the fundamental harmonic will be VHV p–p. For instance, when VHV is 500 V, the output swings from 0 to 500 V (refer Figs. 9–11). On the other hand, the amplitude of fundamental harmonic is higher for rectangular toneburst. Therefore, the amplitude obtained when VHV is 500 V according Fig. 12 is not 250 V (half of VHV) but 312 V (or 624 Vp–p). Output is stable over frequency range in unloaded condition. The output voltage is the same 312 V up to 1 MHz for highly capacitive load (3000 pF), then it starts to drop and at 6 MHz is equal to 240 V (480 Vp–p). Fundamental harmonic is 276 V (552 Vp–p) for 50 X load when high voltage power supply is 500 V. This is explained by voltage drop on intrinsic output impedance of the pulser. AC response obtained was normalised in order to compare the performance under various high voltage settings and loads. The

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Fig. 11. Pulser output signals comparison when loaded by ultrasonic transducer, 50 X resistance and 470 pF capacitance.

Fig. 12. Pulser output AC response for 50 X, open and capacitive loads at various output voltage setting.

Fig. 13. Normalised pulser output AC response vs. load and high voltage settings.

Fig. 14. AC response of the output impedance under several output levels.

4. Conclusions results are presented in Fig. 13 (50 X, 3000 pF load and unloaded comparison). The bandwidth for the highest output voltage is up to 10 MHz under 50 X load. For unloaded condition or lower voltages the upper frequency is even higher. The pulser is capable to drive 3000 pF loads up to 6 MHz. Output is stable within 3 dB up to 6 MHz for all types of loads. Slight reduction of the output at low frequencies, when driving 50 X load, can be explained by larger power consumption. In this case, the high voltage buffer capacitor is not capable to deliver sufficient energy and the output amplitude drops down by 0.2 dB. It can be concluded that the output AC response is smooth for all types of loads. High voltage setting does not affect the relative output amplitude and bandwidth. The results of output resistance AC response for several output voltage settings are presented in Fig. 14. It can be seen that the output resistance for voltages below 500 V is 13 X and stable up to 10 MHz. For 500 V resistance varies from 16 X to 26 X in 8 MHz range and varies significantly beyond 9 MHz. The output reactance is created by a parallel connection of the MOSFET output capacitance (approximately 400 pF). The output reactance varies with the output voltage swing because this capacitance is nonlinear.

High voltage and high current pulser for ultrasonic transducer excitation has been presented. Half bridge topology was used which requires a floating and fast high side driver. The problem was solved using a combination of the fast digital isolator and the high speed MOSFET driver. The pulser has 10 MHz upper frequency range when loaded by 50 X or light loads. The upper frequency range is 6 MHz when loaded by 3000 pF. Lower operation frequencies are not limited because the bootstrapped high side power supply was replaced by an isolated DC/DC converter. Output amplitude of the fundamental harmonic can reach 624 Vp–p for light loads and 552 Vp–p when driving 50 X loads. Acknowledgement This research was funded by a Grant (No. MIP-058/2012) from the Research Council of Lithuania. References [1] J.A. Brown, G.R. Lockwood, A low-cost, high-performance pulse generator for ultrasound imaging, IEEE Trans. Ultrason., Ferroelectr., Freq. Control 49 (6) (2002) 848–851, http://dx.doi.org/10.1109/TUFFC.2002.1009345.

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