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A Low-Phase-Noise Ka-Band Push-Push Voltage-Controlled Oscillator Using CMOS/ Glass-Integrated Passive Device Technologies Sen Wang, Member, IEEE Abstract—In this paper, a Ka-band CMOS push-push voltage-controlled oscillator (VCO) integrated into a glass-integrated passive device (GIPD) process is presented. The transformer, λ/4 transmission line, and inductors of the VCO are realized in the GIPD process, achieving superior performances, and therefore improve the phase noise of the VCO. Moreover, the transformer-based VCO is a differential Hartley topology to further reduce the phase noise and chip area. Operating at 1.8 V supply voltage, the VCO core consumes merely 3.8 mW of dc power. The measured phase noise is −109.18 dBc/Hz at 1 MHz offset from the 30.84 GHz oscillation frequency. The push-push VCO also demonstrates a 24.5 dB fundamental rejection, and exhibits an 8.4% tuning range. Compared with recently published CMOS-based VCOs, it is observed that the proposed VCO exhibits excellent performance under low power consumption.
I. Introduction
D
emands on wireless communications have motivated the development of RF front-end circuits toward tens of gigahertz to achieve high-data-rate transmission. Scalable and advanced CMOS technologies demonstrate low cost, high integration, and good reliability potentials which make digital, analog, and RF circuitry in a single chip realistic [1]. A voltage-controlled oscillator (VCO) is one of the key components to provide stable carrier frequencies in transceivers. However, the inherent lossy silicon substrate and low maximum oscillation frequency ( fmax) of active devices degrade the phase noise and limit the operating frequency of CMOS VCOs, respectively. Therefore, integrated VCOs are generally realized by III–V compound devices or SiGe HBTs at microwave and millimeter-wave frequencies [2]–[4]. These GaAs/InP/ SiGe-based VCOs have advantages in terms of good phase noise, high operating frequency, and output power, but a great deal of dc power is also required. Typically, a push-push VCO in a standard CMOS process is an attractive approach which achieves an output frequency twice the fundamental frequency and features a good fundamental rejection and wide tuning range [5], [6]. The output frequency, namely the second harmonic, is Manuscript received April 18, 2013; accepted June 6, 2014. The work was supported by the National Science Council of Taiwan under Grant NSC 101-2221-E-027-104. The author is with the Graduate Institute of Computer and Communication Engineering, Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan, R.O.C. (e-mail: wangsen @ntut.edu.tw). DOI http://dx.doi.org/10.1109/TUFFC.2014.3059 0885–3010
even able to work above the device fmax. Although demonstrating high oscillating frequency and acceptable output power, the phase noise performance of the push-push VCO topology is still limited because of the lack of high-Q CMOS inductors. In this work, a glass-integrated passive device (GIPD) process is demonstrated to achieve high-Q passive components. Compared with a standard CMOS process, the GIPD provides thicker metal layers to reduce resistive losses and a low-loss glass substrate to reduce the substrate losses, as shown in Fig. 1. Therefore, passive components with superior performance are practical with the GIPD process, and popular CMOS RFICs can be also integrated into the glass substrate by bumpers in a flipchip form. The bumpers not only connect CMOS RFICs and GIPD chip but also support the weight of CMOS chip, avoiding damage to the 3-D structure. In this paper, we present the first push-push VCO which is also a differential Hartley topology in CMOS/ GIPD technologies, and the VCO exhibits excellent performance at millimeter frequencies. The second-harmonic output signal is taken from two fundamental differential buffers working in the triode region to deliver more output power. This paper is organized as follows. In Section II, the push-push VCO based on a transformer, or differential Hartley topology, is investigated; then, some passive components in the GIPD process for high Q-factors are also introduced. Section III details the implementation and experimental results of the push-push VCO. Finally, Section IV concludes this paper. II. Design Methodology A. Design of the Push-Push VCO Fig. 2 shows a conventional push-push VCO circuit which adopts an NMOS cross-coupled pair to generate negative conductances. The output signal is delivered from the middle of the inductor of the LC tank where the differential fundamental signals cancel out each other, and the second harmonic signals combine in phase [5], [6]. Although the push-push VCO demonstrates high oscillation frequencies, it still suffers high phase noise characteristics because of the poor quality factors of the passive components. Fig. 3 shows two independent Hartley oscillators combined into the differential form. The designed VCO is a differential Hartley oscillator to reduce the phase noise [7], [8]. The transformer formed by the coupled inductors
© 2014 IEEE
wang: a low-phase-noise ka-band push-push vco using cmos/gipd technologies
Fig. 1. Cross-sectional view of integrated passive device process using glass substrate.
(Ld and Lg) not only improves the quality factor of the LC tank, but also provides a dc path for the gate terminals. Moreover, the transformer can be realized by broadsidecoupled inductors to reduce the chip area. Fig. 4 shows the complete schematic of the proposed push-push VCO. To improve the quality factor of the transformer, inductors, and the 1/4λ transmission line (TL), an integrated passive device technology is adopted to realize these components. Thus, the phase noise and power consumption of the VCO can be both reduced. Other active devices, varactors, and capacitors are designed in a standard 0.18-μm CMOS process. Transistors M1 and M2 are the core of the differential Hartley oscillator mentioned previously. Moreover, an NMOS cross-coupled pair (M3 and M4) is also employed to enhance the oscillation condition at high frequencies. The LC tank is composed of the transformer and inversion-mode varactors. The varactors comprise a conventional NMOS transistor whose drain, source, and body terminals are connected together as one node of the varactor, and the other node is with polysilicon gate. No current source is used in the design to decrease the phase noise and to increase the voltage swing across the LC tank. Unlike the conventional topology, in which the second harmonic signal is extracted from the virtual short point inside the resonant tank, the second harmonic signal is first amplified through the common-
Fig. 2. Schematic diagram of a conventional NMOS-only cross-coupled push-push VCO.
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Fig. 3. Two independent Hartley oscillators combined into the differential form.
source buffers (M5 and M6), and then extracted from the middle of the two inductors (L1 and L2). To acquire more output power, M5 and M6 are both biased in the triode region. Therefore, the second harmonic power can be increased with the increased device nonlinearity. B. Design of the Passive Components in GIPD The passive components such as the transformer, transmission line, and inductors of the VCO are implemented in a three-layered glass substrate with a dielectric constant εr of 5.2, a loss tangent of 0.003, and a thickness of 200 μm. The top metal layer (M3) is formed by 12-μm-thick copper alloy which is suitable for high-Q inductors. The bottom two metal layers (M2 and M3) are formed by 3-um-thick copper. The distance and the dielectric constant between M2 and M3 is 0.2 μm and 7, respectively. Therefore, the two layers are suitable for high-capacitance-density capacitors. The properties of these passive components are verified through utilizing the 3-D electromagnetic simulator Ansoft high-frequency structure simulator (HFSS; Ansys Inc., Canonsburg, PA). Although the coupling coefficient of interleaved transformers is not the highest one among the four basic transformers, they are easy to implement and suitable for
Fig. 4. The proposed push-push transformer-based VCO and its circuit parameters.
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the magnified region in Fig. 7, the periodic structure and etched area of the meshed ground plane is 100 × 100 μm2 and 90 × 90 μm2, respectively. Considering all structural parameters including the glass substrate of the GIPD process, the transmission line can be characterized by the HFSS. Finally, the complex propagation constant (γ = α + jβ ) and the characteristic impedance (Zc) of the TL can be extracted from the S-parameters as shown in [13] (1 + S 11 2 − S 21 2)2 − (2S 11)2 2S 21 (3)
e γL = Fig. 5. Layout of the interleaved transformer based on the GIPD process with a chip area of 0.46 × 0.55 mm.
design of differential VCOs. Fig. 5 illustrates the layout of the interleaved transformer, which consists of the two coupled inductors (Ld and Lg). The line width and spacing between two inductors are both 10 μm. The inner radii of Ld and Lg are 83 μm and 47 μm, and the core area of the transformer is 0.36 mm × 0.35 mm. The height and diameter of bumpers are 70 μm and 100 μm, and the octagonal layout is BCB2. Because the size of bumpers is large enough to affect passive components, the effect must therefore be considered. Simulation results show that a bumper can be approximated as a 0.05-nH inductor and a 0.03-Ω resistor in series at 16 GHz. Based on the description of the process parameters mentioned previously and the structural parameters in Fig. 1, the electrical characteristics of the transformer can be extracted from
Q = Im[Z 11]/ Re[Z 11] (1)
L = Im[Z 11]/2π f , (2)
where Z11 represents the element of the two-port impedance matrix. Fig. 6 shows the simulated inductance and Q-factor of Ld and Lg including all structures in Fig. 1. The inductances of Ld and Lg are 1.2 nH and 0.58 nH at 16 GHz, respectively. The coupling coefficient (k) is about 0.56 at the frequency of interest. Moreover, both the Q-factors of the two inductors are higher than 30 at 16 GHz, which are impractical in a standard CMOS process. Typically, a transformer-based LC tank has a high quality factor which can be amplified by a multiplication factor of (1 + k) [9]–[12]. The designed synthetic TL is a periodical structure which offers another degree of freedom for controlling the propagation characteristics of conventional microstrip lines. Fig. 7 shows the layout of the λ/4 TL which uses the top metal layer as the signal line, and the bottom layer as the meshed ground plane. The TL is mainly used to block second harmonic signals and to provide a dc path. The length and width of the TL are 1.1 mm and 20 μm, respectively. The TL is not a straight line for easy integration, and the two bend angles are both 145° to reduce losses resulting from current discontinuities. As shown in
1 − S 11 2 + S 21 2 +
Zc = Zo
(1 + S 11)2 − S 21 2 , (4) (1 − S 11)2 − S 21 2
where Zo is the reference characteristic impedance, usually equal to 50 Ω; L is the total length of the TL. Fig. 8 shows the electrical characteristics of the λ/4 TL. The real part of characteristic impedance of the TL near 50 Ω, and the phase difference from one port to the other port is about 90° at 32 GHz, as shown in Fig. 8(a). Moreover, the slowwave factor (SWF) defined by βg/βo is 2.05, and the quality factor defined by (β/2α) is 31 at 32 GHz. Typically, synthetic TLs with meshed ground planes demonstrate high SWF, thus reducing the length of the TLs. III. Implementation and Measurement Fig. 9(a) shows the chip photo of the VCO which is fabricated by Taiwan Semiconductor Manufacturing Company (TSMC; Hsinchu, Taiwan) with a standard mixed/ signal/RF bulk 0.18-μm CMOS process. It is obvious that transistors and varactors are in the layout of the core area, as magnified in Fig. 9(a). With the optimized CMOS technology and deep n-well photolithography, this process provides ft and fmax better than 60 and 55 GHz, respectively. The process also provides one poly layer and six metal (1P6M) layers, and capacitors in the design are composed of metal-insulator-metal (MIM) capacitors
Fig. 6. Simulated inductance and Q factors of Ld and Lg.
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Fig. 7. Layout of the λ/4 transmission line using the IPD process.
Fig. 9. (a) The 0.18-μm CMOS chip with a chip size of 1.69 mm2. (b) The GIPD chip with a chip size of 6.5 mm2. (c) The fabricated pushpush VCO using flip-chip process.
Fig. 8. (a) Simulated Re[Zc] and phase. (b) Simulated slow-wave factors and Q factors of the λ/4 transmission line with consideration of the glass substrate in Fig. 1.
with a 1 fF/μm2 capacitance density. The aspect ratios of transistors M1–2 and M3–6 in Fig. 4 are 15 μm/0.18 μm and 16 μm/0.18 μm, respectively. The device sizes of the inversion-mode varactors, or NMOS transistors are 40 μm/0.18 μm. Power lines of the chip are all realized on the top metal layer to minimize resistive losses. As shown in Fig. 9(a), dummy metals are inserted to meet the design rules, and some bumpers are distributed over the edges of the chip to sustain the chip on the glass substrate. The weight of the
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Fig. 10. Pad extension for the metal planarization.
CMOS chip would result in collapse in the 3-D flip-chip process, and therefore it is necessary to increase the density of bumpers in the edges. The chip size including the bumpers is 1.69 mm2. The large chip area is mainly limited by the bumpers and dummy metals. Fig. 9(b) shows a photo of the GIPD chip, which consists of the interleaved transformer, inductors, and the 1/4λ TL. The chip size including all testing pads is 6.5 mm2. The octagonal layout corresponding to the bumpers in the CMOS chip is BCB2. As discussed in Section II, these passive components and power lines are mainly fabricated on the top metal layer, with a thickness of 12 μm. Finally, the CMOS chip is integrated into the GIPD chip by bumpers in a flip-chip form, as shown in Fig. 9(c). The chip integrated into the glass substrate is tested via on-wafer probing, and therefore, the planarization of pads must be considered for accurate results. As shown in Fig. 1, the ground plane of the chip is defined at the M1 layer, and the ground (G) pads are realized from M1 to M3 layers which are connected by via, M2, and BCB1 layers. Moreover, the signal (S) pads and power (P) pads are merely implemented on the top metal layer, or M3 layer. Fig. 10 shows the vertical and cross-section chip photo of the testing pads, and each testing pad is 148 μm × 74 μm. Because of the presence of via, M2, and BCB1 layers, the centers of the ground pads are sunken, and the heights of ground and signal pads are uneven. Therefore, it would damage probes physically or inaccurate results are obtained. To improve the metal planarization of testing pads, all the pads are extended to the M3 layer, as shown in Fig. 10. Finally, the pad extension provides smooth and even metal layers for standard measurements by coplanar waveguide (CPW) probes. The push-push VCO was characterized by on-wafer measurements with an Agilent E4448A 50-GHz spectrum analyzer (SA; Agilent Technologies Inc., Santa Clara, CA), and undesired parasitics of pads and interconnections were also removed by a de-embedding procedure. Typically, VCOs demonstrate better phase noise and stability at low frequencies because of the reduction of thermal noise in CMOS transistors. The measurement was conducted at a room temperature of 25°C, and the phase noise between 100 kHz and 10 MHz offset was emphasized because of the comparison of standard CMOS VCOs [9]. While operating at the supply voltage (VD1) of 1.8 V, the VCO consumes a dc power of 3.8 mW, excluding the
Fig. 11. Measured oscillation frequency with a control voltage of 1.0 V.
buffers. The resolution bandwidth, video bandwidth, and span of the SA are 10 kHz, 1 kHz, and 500 MHz, respectively. As shown in Fig. 11, the measured output power is −20.46 dBm at 30.84 GHz. The E4448A SA provides better phase noise accuracy at higher offset frequencies, and therefore the phase noise measurements were conducted from 100 kHz to 1 MHz offset frequency, as shown in Fig. 12. The measured phase noise is −109.18 dBc/Hz at 1 MHz offset. Moreover, considering a room temperature of 25°C, a quality factor of 60, and a 1/f corner frequency of 1 kHz, an estimated phase noise of −107.7 dBc/Hz can be also obtained by the Leeson equation, which is close to the measured result. The measured fundamental power from the second harmonic output is −44.96 dBm demonstrate a fundamental rejection of 24.5 dB, as shown in Fig. 13. Fig. 14 shows the measured oscillation frequency and output power versus control voltage. The oscillation frequency is from 29.8 to 32.4 GHz with control voltage between 0 and 2.5 V. That is, the VCO exhibits a tuning range of 8.4%. Similarly, the output power is from −21.06 dBm to −19.76 dBm with the same tuning range. As shown in Fig. 14, there is about 0.6 to 1 GHz frequency discrepancy and 0.2 to 0.6 dBm
Fig. 12. Measured phase noise at 1 MHz offset.
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Fig. 13. Measured output power from the second harmonic output.
discrepancy between the simulated and measured results. The small disagreement results from the parasitic effect and undesired interconnections in the layout. Finally, two figures of merit (FOM and FOMT) which allow comparison among VCOs at different frequencies are defined as follows:
f P FOM = L(∆f ) − 20 log osc + 10 log dc (5) ∆f 1 mW
f Tr P + 10 log dc , (6) FOM T = L(∆f ) − 20 log osc ∆f 10 1 mW where L(Δf ) is the measured phase noise at the frequency offset Δf from the carrier frequency fosc, Pdc is the VCO power consumption in milliwatts, and Tr is the tuning range in percent. Table I summarizes the previously reported CMOS-based VCOs. This work demonstrates a low-power design with a superior phase noise characteristic, a high FOM, and the highest FOMT with low power consumption among the VCOs. IV. Conclusion This paper presents the design of a Ka-band push-push VCO using an interleaved transformer in the Hartley differential structure. The core of VCO is implemented in
Fig. 14. Simulated and measured (a) oscillation frequency and (b) output power versus control voltage.
a standard 0.18-μm CMOS process, and then integrated into the GIPD process by bumpers in a flip-chip form. The designed transformer and 1/4λ TL are both fabricated in the GIPD to achieve superior performances. The chip shows very low phase noise, −109.18 dBc/Hz at 1 MHz offset at 30.84 GHz with a 2.6 GHz tuning range. Moreover, the layout of pads and bumpers is also investigated for measurement and implementation considerations. Good electrical characteristics of the VCO clearly show the potential of the state-of-the-art CMOS/GIPD process for the realization of RF circuits requiring high-Q or lowloss passive components.
TABLE I. Comparison of Previously Reported CMOS-Based VCOs in the K/Ka Band. Reference
Process
[9] [10] [11] [12] [14] [15] [16] This work
0.18-μm CMOS 0.18-μm CMOS 0.18-μm CMOS 0.13-μm CMOS 0.13-μm CMOS 0.18-μm CMOS 0.18-μm CMOS 0.18-μm CMOS + GIPD
fosc. (GHz)
Tuning range (%)
Phase noise @1MHz (dBc/Hz)
Pdc (mW)
FOM (dBc/Hz)
FOMT (dBc/Hz)
18.95 21.3 21.37 26.3 26.89 24.27 21.6 30.84
3.58 3.0 5.1 23.6 2.4 2.2 2.6 8.4
110.82 105.9 109.8 92.6 113 100.33 101.75 109.18
3.3 9.6 3.5 43 4.99 7.8 45 3.8
191.2 182.6 191.0 164.7 194.6 179.1 171.9 193.2
182.3 172.2 185.1 172.1 182.2 166.0 167.8 191.7
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Acknowledgments The authors thank the Chip Implementation Center (CIC) and Touch Micro-system Technology (TMT) Corporation of Taiwan for the chip implementation, and J.Y. Zhong at National Taiwan University for his technical assistance. References [1] W. Lerdsitsomboon and K. O. Kenneth, “Technique for integration of a wireless switch in a 2.4 GHz single chip radio,” IEEE J. SolidState Circuits, vol. 46, no. 2, pp. 368–377, Feb. 2011. [2] W. Winkler, J. Borngraber, B. Heinemann, and P. Weger, “60GHz and 76GHz oscillators in 0.25μm SiGe:C BiCMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, 2003, pp. 454–455. [3] F. X. Sinnesbichler, H. Geltinger, and G. R. Olbrich, “A 50 GHz SiGe HBT push-push oscillator,” in IEEE MTT-S Int. Microwave Symp. Dig., 1999, pp. 9–12. [4] F. Lenk, M. Schott, J. Hilsenbeck, J. Wurfl, and W. Heinrich, “Low phase-noise monolithic GaInP/GaAs-HBT VCO for 77 GHz,” in IEEE MTT-S Int. Microw. Symp. Dig., 2003, vol. 2, pp. 8–13. [5] P.-C. Huang, M.-D. Tsai, H. Wang, G. D. Vendelin, C.-H. Chen, and C.-S. Chang, “A low power 114-GHz push-push CMOS VCO using LC source degeneration,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1230–1239, Jun. 2007. [6] R.-C. Liu, H.-Y. Chang, C.-H. Wang, and H. Wang, “A 63-GHz VCO using a standard 0.25-μm CMOS process,” in IEEE Int. SolidState Circuit Conf. Dig. Tech. Papers, 2004, pp. 372–373. [7] J. Park, J. Park, Y. Choi, K. Sim, and D. Baek, “A fully-differential complementary Hartley VCO in 0.18-μm COMS technology,” IEEE Microw. Wirel. Compon. Lett., vol. 19, no. 9, pp. 789–792, Feb. 2010. [8] S. H. Lee, Y. H. Chuang, S. L. Jang, and C. C. Chen, “Low-phase noise Hartley differential CMOS voltage controlled oscillator,” IEEE Microw. Wirel. Compon. Lett., vol. 17, no. 2, pp. 889–893, Feb. 2007. [9] T.-P. Wang, “A K-band low-power Colpitts VCO with voltage-tocurrent positive-feedback network in 0.18 μm CMOS,” IEEE Microw. Wirel. Compon. Lett., vol. 21, no. 4, pp. 218–220, Apr. 2011.
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[10] C. C. Li, T. P. Wang, C. C. Kuo, M. C. Chuang, and H. Wang, “A 21 GHz complementary transformer-coupled CMOS VCO,” IEEE Microw. Wirel. Compon. Lett., vol. 16, no. 4, pp. 278–280, Apr. 2008. [11] S. L. Liu, K. H. Chen, T. Chang, and A. Chin, “A low-power Kband CMOS VCO with four-coil transformer feedback,” IEEE Microw. Wirel. Compon. Lett., vol. 20, no. 8, pp. 459–461, Aug. 2010. [12] K. Kwok and J. R. Long, “A 23-to-29 GHz transconductor-tuned VCO MMIC in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2878–2886, Dec. 2007. [13] S. Wang, B.-Z. Huang, and Z.-K. Li, “A miniaturized 10/24-GHz rat-race coupler using synthetic transmission lines on glass substrate,” IEICE Electron. Express, vol. 8, no. 17, pp. 1425–1430, Sep. 2011. [14] D. Y. Jung and C. S. Park, “Power efficient Ka-band low phase noise VCO in 0.13 μm CMOS,” Electron. Lett., vol. 44, no. 10, pp. 628–630, May 2008. [15] J. Yang, C. Y. Kim, D. W. Kim, and S. Hong, “Design of a 24 GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuit Syst. II, vol. 57, no. 3, pp. 173–177, Mar. 2010. [16] D. Ozis, N. Neihart, and D. Allstot, “Differential VCO and passive frequency doubler in 0.18 μm CMOS for 24 GHz applications,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., 2006, pp. 36–39.
Sen Wang (S’05–M’10) was born in Yi-lan, Taiwan, in 1982. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2004, and the M.S. and Ph.D. degrees from the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2006 and 2009, respectively. He joined the faculty of the Department of Electronic Engineering, National Taipei University of Technology in February 2010. He is currently an associate professor. His research interests include the design of microwave/millimeter-wave passive circuits, CMOS RF integrated circuits, and radar system engineering.
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control ,
vol. 61, no. 9,
September
2014
A Low-Phase-Noise Ka-Band Push-Push Voltage-Controlled Oscillator Using CMOS/ Glass-Integrated Passive Device Technologies Sen Wang, Member, IEEE Abstract—In this paper, a Ka-band CMOS push-push voltage-controlled oscillator (VCO) integrated into a glass-integrated passive device (GIPD) process is presented. The transformer, λ/4 transmission line, and inductors of the VCO are realized in the GIPD process, achieving superior performances, and therefore improve the phase noise of the VCO. Moreover, the transformer-based VCO is a differential Hartley topology to further reduce the phase noise and chip area. Operating at 1.8 V supply voltage, the VCO core consumes merely 3.8 mW of dc power. The measured phase noise is −109.18 dBc/Hz at 1 MHz offset from the 30.84 GHz oscillation frequency. The push-push VCO also demonstrates a 24.5 dB fundamental rejection, and exhibits an 8.4% tuning range. Compared with recently published CMOS-based VCOs, it is observed that the proposed VCO exhibits excellent performance under low power consumption.
I. Introduction
D
emands on wireless communications have motivated the development of RF front-end circuits toward tens of gigahertz to achieve high-data-rate transmission. Scalable and advanced CMOS technologies demonstrate low cost, high integration, and good reliability potentials which make digital, analog, and RF circuitry in a single chip realistic [1]. A voltage-controlled oscillator (VCO) is one of the key components to provide stable carrier frequencies in transceivers. However, the inherent lossy silicon substrate and low maximum oscillation frequency ( fmax) of active devices degrade the phase noise and limit the operating frequency of CMOS VCOs, respectively. Therefore, integrated VCOs are generally realized by III–V compound devices or SiGe HBTs at microwave and millimeter-wave frequencies [2]–[4]. These GaAs/InP/ SiGe-based VCOs have advantages in terms of good phase noise, high operating frequency, and output power, but a great deal of dc power is also required. Typically, a push-push VCO in a standard CMOS process is an attractive approach which achieves an output frequency twice the fundamental frequency and features a good fundamental rejection and wide tuning range [5], [6]. The output frequency, namely the second harmonic, is Manuscript received April 18, 2013; accepted June 6, 2014. The work was supported by the National Science Council of Taiwan under Grant NSC 101-2221-E-027-104. The author is with the Graduate Institute of Computer and Communication Engineering, Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan, R.O.C. (e-mail: wangsen @ntut.edu.tw). DOI http://dx.doi.org/10.1109/TUFFC.2014.3059 0885–3010
even able to work above the device fmax. Although demonstrating high oscillating frequency and acceptable output power, the phase noise performance of the push-push VCO topology is still limited because of the lack of high-Q CMOS inductors. In this work, a glass-integrated passive device (GIPD) process is demonstrated to achieve high-Q passive components. Compared with a standard CMOS process, the GIPD provides thicker metal layers to reduce resistive losses and a low-loss glass substrate to reduce the substrate losses, as shown in Fig. 1. Therefore, passive components with superior performance are practical with the GIPD process, and popular CMOS RFICs can be also integrated into the glass substrate by bumpers in a flipchip form. The bumpers not only connect CMOS RFICs and GIPD chip but also support the weight of CMOS chip, avoiding damage to the 3-D structure. In this paper, we present the first push-push VCO which is also a differential Hartley topology in CMOS/ GIPD technologies, and the VCO exhibits excellent performance at millimeter frequencies. The second-harmonic output signal is taken from two fundamental differential buffers working in the triode region to deliver more output power. This paper is organized as follows. In Section II, the push-push VCO based on a transformer, or differential Hartley topology, is investigated; then, some passive components in the GIPD process for high Q-factors are also introduced. Section III details the implementation and experimental results of the push-push VCO. Finally, Section IV concludes this paper. II. Design Methodology A. Design of the Push-Push VCO Fig. 2 shows a conventional push-push VCO circuit which adopts an NMOS cross-coupled pair to generate negative conductances. The output signal is delivered from the middle of the inductor of the LC tank where the differential fundamental signals cancel out each other, and the second harmonic signals combine in phase [5], [6]. Although the push-push VCO demonstrates high oscillation frequencies, it still suffers high phase noise characteristics because of the poor quality factors of the passive components. Fig. 3 shows two independent Hartley oscillators combined into the differential form. The designed VCO is a differential Hartley oscillator to reduce the phase noise [7], [8]. The transformer formed by the coupled inductors
© 2014 IEEE
wang: a low-phase-noise ka-band push-push vco using cmos/gipd technologies
Fig. 1. Cross-sectional view of integrated passive device process using glass substrate.
(Ld and Lg) not only improves the quality factor of the LC tank, but also provides a dc path for the gate terminals. Moreover, the transformer can be realized by broadsidecoupled inductors to reduce the chip area. Fig. 4 shows the complete schematic of the proposed push-push VCO. To improve the quality factor of the transformer, inductors, and the 1/4λ transmission line (TL), an integrated passive device technology is adopted to realize these components. Thus, the phase noise and power consumption of the VCO can be both reduced. Other active devices, varactors, and capacitors are designed in a standard 0.18-μm CMOS process. Transistors M1 and M2 are the core of the differential Hartley oscillator mentioned previously. Moreover, an NMOS cross-coupled pair (M3 and M4) is also employed to enhance the oscillation condition at high frequencies. The LC tank is composed of the transformer and inversion-mode varactors. The varactors comprise a conventional NMOS transistor whose drain, source, and body terminals are connected together as one node of the varactor, and the other node is with polysilicon gate. No current source is used in the design to decrease the phase noise and to increase the voltage swing across the LC tank. Unlike the conventional topology, in which the second harmonic signal is extracted from the virtual short point inside the resonant tank, the second harmonic signal is first amplified through the common-
Fig. 2. Schematic diagram of a conventional NMOS-only cross-coupled push-push VCO.
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Fig. 3. Two independent Hartley oscillators combined into the differential form.
source buffers (M5 and M6), and then extracted from the middle of the two inductors (L1 and L2). To acquire more output power, M5 and M6 are both biased in the triode region. Therefore, the second harmonic power can be increased with the increased device nonlinearity. B. Design of the Passive Components in GIPD The passive components such as the transformer, transmission line, and inductors of the VCO are implemented in a three-layered glass substrate with a dielectric constant εr of 5.2, a loss tangent of 0.003, and a thickness of 200 μm. The top metal layer (M3) is formed by 12-μm-thick copper alloy which is suitable for high-Q inductors. The bottom two metal layers (M2 and M3) are formed by 3-um-thick copper. The distance and the dielectric constant between M2 and M3 is 0.2 μm and 7, respectively. Therefore, the two layers are suitable for high-capacitance-density capacitors. The properties of these passive components are verified through utilizing the 3-D electromagnetic simulator Ansoft high-frequency structure simulator (HFSS; Ansys Inc., Canonsburg, PA). Although the coupling coefficient of interleaved transformers is not the highest one among the four basic transformers, they are easy to implement and suitable for
Fig. 4. The proposed push-push transformer-based VCO and its circuit parameters.
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the magnified region in Fig. 7, the periodic structure and etched area of the meshed ground plane is 100 × 100 μm2 and 90 × 90 μm2, respectively. Considering all structural parameters including the glass substrate of the GIPD process, the transmission line can be characterized by the HFSS. Finally, the complex propagation constant (γ = α + jβ ) and the characteristic impedance (Zc) of the TL can be extracted from the S-parameters as shown in [13] (1 + S 11 2 − S 21 2)2 − (2S 11)2 2S 21 (3)
e γL = Fig. 5. Layout of the interleaved transformer based on the GIPD process with a chip area of 0.46 × 0.55 mm.
design of differential VCOs. Fig. 5 illustrates the layout of the interleaved transformer, which consists of the two coupled inductors (Ld and Lg). The line width and spacing between two inductors are both 10 μm. The inner radii of Ld and Lg are 83 μm and 47 μm, and the core area of the transformer is 0.36 mm × 0.35 mm. The height and diameter of bumpers are 70 μm and 100 μm, and the octagonal layout is BCB2. Because the size of bumpers is large enough to affect passive components, the effect must therefore be considered. Simulation results show that a bumper can be approximated as a 0.05-nH inductor and a 0.03-Ω resistor in series at 16 GHz. Based on the description of the process parameters mentioned previously and the structural parameters in Fig. 1, the electrical characteristics of the transformer can be extracted from
Q = Im[Z 11]/ Re[Z 11] (1)
L = Im[Z 11]/2π f , (2)
where Z11 represents the element of the two-port impedance matrix. Fig. 6 shows the simulated inductance and Q-factor of Ld and Lg including all structures in Fig. 1. The inductances of Ld and Lg are 1.2 nH and 0.58 nH at 16 GHz, respectively. The coupling coefficient (k) is about 0.56 at the frequency of interest. Moreover, both the Q-factors of the two inductors are higher than 30 at 16 GHz, which are impractical in a standard CMOS process. Typically, a transformer-based LC tank has a high quality factor which can be amplified by a multiplication factor of (1 + k) [9]–[12]. The designed synthetic TL is a periodical structure which offers another degree of freedom for controlling the propagation characteristics of conventional microstrip lines. Fig. 7 shows the layout of the λ/4 TL which uses the top metal layer as the signal line, and the bottom layer as the meshed ground plane. The TL is mainly used to block second harmonic signals and to provide a dc path. The length and width of the TL are 1.1 mm and 20 μm, respectively. The TL is not a straight line for easy integration, and the two bend angles are both 145° to reduce losses resulting from current discontinuities. As shown in
1 − S 11 2 + S 21 2 +
Zc = Zo
(1 + S 11)2 − S 21 2 , (4) (1 − S 11)2 − S 21 2
where Zo is the reference characteristic impedance, usually equal to 50 Ω; L is the total length of the TL. Fig. 8 shows the electrical characteristics of the λ/4 TL. The real part of characteristic impedance of the TL near 50 Ω, and the phase difference from one port to the other port is about 90° at 32 GHz, as shown in Fig. 8(a). Moreover, the slowwave factor (SWF) defined by βg/βo is 2.05, and the quality factor defined by (β/2α) is 31 at 32 GHz. Typically, synthetic TLs with meshed ground planes demonstrate high SWF, thus reducing the length of the TLs. III. Implementation and Measurement Fig. 9(a) shows the chip photo of the VCO which is fabricated by Taiwan Semiconductor Manufacturing Company (TSMC; Hsinchu, Taiwan) with a standard mixed/ signal/RF bulk 0.18-μm CMOS process. It is obvious that transistors and varactors are in the layout of the core area, as magnified in Fig. 9(a). With the optimized CMOS technology and deep n-well photolithography, this process provides ft and fmax better than 60 and 55 GHz, respectively. The process also provides one poly layer and six metal (1P6M) layers, and capacitors in the design are composed of metal-insulator-metal (MIM) capacitors
Fig. 6. Simulated inductance and Q factors of Ld and Lg.
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Fig. 7. Layout of the λ/4 transmission line using the IPD process.
Fig. 9. (a) The 0.18-μm CMOS chip with a chip size of 1.69 mm2. (b) The GIPD chip with a chip size of 6.5 mm2. (c) The fabricated pushpush VCO using flip-chip process.
Fig. 8. (a) Simulated Re[Zc] and phase. (b) Simulated slow-wave factors and Q factors of the λ/4 transmission line with consideration of the glass substrate in Fig. 1.
with a 1 fF/μm2 capacitance density. The aspect ratios of transistors M1–2 and M3–6 in Fig. 4 are 15 μm/0.18 μm and 16 μm/0.18 μm, respectively. The device sizes of the inversion-mode varactors, or NMOS transistors are 40 μm/0.18 μm. Power lines of the chip are all realized on the top metal layer to minimize resistive losses. As shown in Fig. 9(a), dummy metals are inserted to meet the design rules, and some bumpers are distributed over the edges of the chip to sustain the chip on the glass substrate. The weight of the
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Fig. 10. Pad extension for the metal planarization.
CMOS chip would result in collapse in the 3-D flip-chip process, and therefore it is necessary to increase the density of bumpers in the edges. The chip size including the bumpers is 1.69 mm2. The large chip area is mainly limited by the bumpers and dummy metals. Fig. 9(b) shows a photo of the GIPD chip, which consists of the interleaved transformer, inductors, and the 1/4λ TL. The chip size including all testing pads is 6.5 mm2. The octagonal layout corresponding to the bumpers in the CMOS chip is BCB2. As discussed in Section II, these passive components and power lines are mainly fabricated on the top metal layer, with a thickness of 12 μm. Finally, the CMOS chip is integrated into the GIPD chip by bumpers in a flip-chip form, as shown in Fig. 9(c). The chip integrated into the glass substrate is tested via on-wafer probing, and therefore, the planarization of pads must be considered for accurate results. As shown in Fig. 1, the ground plane of the chip is defined at the M1 layer, and the ground (G) pads are realized from M1 to M3 layers which are connected by via, M2, and BCB1 layers. Moreover, the signal (S) pads and power (P) pads are merely implemented on the top metal layer, or M3 layer. Fig. 10 shows the vertical and cross-section chip photo of the testing pads, and each testing pad is 148 μm × 74 μm. Because of the presence of via, M2, and BCB1 layers, the centers of the ground pads are sunken, and the heights of ground and signal pads are uneven. Therefore, it would damage probes physically or inaccurate results are obtained. To improve the metal planarization of testing pads, all the pads are extended to the M3 layer, as shown in Fig. 10. Finally, the pad extension provides smooth and even metal layers for standard measurements by coplanar waveguide (CPW) probes. The push-push VCO was characterized by on-wafer measurements with an Agilent E4448A 50-GHz spectrum analyzer (SA; Agilent Technologies Inc., Santa Clara, CA), and undesired parasitics of pads and interconnections were also removed by a de-embedding procedure. Typically, VCOs demonstrate better phase noise and stability at low frequencies because of the reduction of thermal noise in CMOS transistors. The measurement was conducted at a room temperature of 25°C, and the phase noise between 100 kHz and 10 MHz offset was emphasized because of the comparison of standard CMOS VCOs [9]. While operating at the supply voltage (VD1) of 1.8 V, the VCO consumes a dc power of 3.8 mW, excluding the
Fig. 11. Measured oscillation frequency with a control voltage of 1.0 V.
buffers. The resolution bandwidth, video bandwidth, and span of the SA are 10 kHz, 1 kHz, and 500 MHz, respectively. As shown in Fig. 11, the measured output power is −20.46 dBm at 30.84 GHz. The E4448A SA provides better phase noise accuracy at higher offset frequencies, and therefore the phase noise measurements were conducted from 100 kHz to 1 MHz offset frequency, as shown in Fig. 12. The measured phase noise is −109.18 dBc/Hz at 1 MHz offset. Moreover, considering a room temperature of 25°C, a quality factor of 60, and a 1/f corner frequency of 1 kHz, an estimated phase noise of −107.7 dBc/Hz can be also obtained by the Leeson equation, which is close to the measured result. The measured fundamental power from the second harmonic output is −44.96 dBm demonstrate a fundamental rejection of 24.5 dB, as shown in Fig. 13. Fig. 14 shows the measured oscillation frequency and output power versus control voltage. The oscillation frequency is from 29.8 to 32.4 GHz with control voltage between 0 and 2.5 V. That is, the VCO exhibits a tuning range of 8.4%. Similarly, the output power is from −21.06 dBm to −19.76 dBm with the same tuning range. As shown in Fig. 14, there is about 0.6 to 1 GHz frequency discrepancy and 0.2 to 0.6 dBm
Fig. 12. Measured phase noise at 1 MHz offset.
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Fig. 13. Measured output power from the second harmonic output.
discrepancy between the simulated and measured results. The small disagreement results from the parasitic effect and undesired interconnections in the layout. Finally, two figures of merit (FOM and FOMT) which allow comparison among VCOs at different frequencies are defined as follows:
f P FOM = L(∆f ) − 20 log osc + 10 log dc (5) ∆f 1 mW
f Tr P + 10 log dc , (6) FOM T = L(∆f ) − 20 log osc ∆f 10 1 mW where L(Δf ) is the measured phase noise at the frequency offset Δf from the carrier frequency fosc, Pdc is the VCO power consumption in milliwatts, and Tr is the tuning range in percent. Table I summarizes the previously reported CMOS-based VCOs. This work demonstrates a low-power design with a superior phase noise characteristic, a high FOM, and the highest FOMT with low power consumption among the VCOs. IV. Conclusion This paper presents the design of a Ka-band push-push VCO using an interleaved transformer in the Hartley differential structure. The core of VCO is implemented in
Fig. 14. Simulated and measured (a) oscillation frequency and (b) output power versus control voltage.
a standard 0.18-μm CMOS process, and then integrated into the GIPD process by bumpers in a flip-chip form. The designed transformer and 1/4λ TL are both fabricated in the GIPD to achieve superior performances. The chip shows very low phase noise, −109.18 dBc/Hz at 1 MHz offset at 30.84 GHz with a 2.6 GHz tuning range. Moreover, the layout of pads and bumpers is also investigated for measurement and implementation considerations. Good electrical characteristics of the VCO clearly show the potential of the state-of-the-art CMOS/GIPD process for the realization of RF circuits requiring high-Q or lowloss passive components.
TABLE I. Comparison of Previously Reported CMOS-Based VCOs in the K/Ka Band. Reference
Process
[9] [10] [11] [12] [14] [15] [16] This work
0.18-μm CMOS 0.18-μm CMOS 0.18-μm CMOS 0.13-μm CMOS 0.13-μm CMOS 0.18-μm CMOS 0.18-μm CMOS 0.18-μm CMOS + GIPD
fosc. (GHz)
Tuning range (%)
Phase noise @1MHz (dBc/Hz)
Pdc (mW)
FOM (dBc/Hz)
FOMT (dBc/Hz)
18.95 21.3 21.37 26.3 26.89 24.27 21.6 30.84
3.58 3.0 5.1 23.6 2.4 2.2 2.6 8.4
110.82 105.9 109.8 92.6 113 100.33 101.75 109.18
3.3 9.6 3.5 43 4.99 7.8 45 3.8
191.2 182.6 191.0 164.7 194.6 179.1 171.9 193.2
182.3 172.2 185.1 172.1 182.2 166.0 167.8 191.7
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Acknowledgments The authors thank the Chip Implementation Center (CIC) and Touch Micro-system Technology (TMT) Corporation of Taiwan for the chip implementation, and J.Y. Zhong at National Taiwan University for his technical assistance. References [1] W. Lerdsitsomboon and K. O. Kenneth, “Technique for integration of a wireless switch in a 2.4 GHz single chip radio,” IEEE J. SolidState Circuits, vol. 46, no. 2, pp. 368–377, Feb. 2011. [2] W. Winkler, J. Borngraber, B. Heinemann, and P. Weger, “60GHz and 76GHz oscillators in 0.25μm SiGe:C BiCMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, 2003, pp. 454–455. [3] F. X. Sinnesbichler, H. Geltinger, and G. R. Olbrich, “A 50 GHz SiGe HBT push-push oscillator,” in IEEE MTT-S Int. Microwave Symp. Dig., 1999, pp. 9–12. [4] F. Lenk, M. Schott, J. Hilsenbeck, J. Wurfl, and W. Heinrich, “Low phase-noise monolithic GaInP/GaAs-HBT VCO for 77 GHz,” in IEEE MTT-S Int. Microw. Symp. Dig., 2003, vol. 2, pp. 8–13. [5] P.-C. Huang, M.-D. Tsai, H. Wang, G. D. Vendelin, C.-H. Chen, and C.-S. Chang, “A low power 114-GHz push-push CMOS VCO using LC source degeneration,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1230–1239, Jun. 2007. [6] R.-C. Liu, H.-Y. Chang, C.-H. Wang, and H. Wang, “A 63-GHz VCO using a standard 0.25-μm CMOS process,” in IEEE Int. SolidState Circuit Conf. Dig. Tech. Papers, 2004, pp. 372–373. [7] J. Park, J. Park, Y. Choi, K. Sim, and D. Baek, “A fully-differential complementary Hartley VCO in 0.18-μm COMS technology,” IEEE Microw. Wirel. Compon. Lett., vol. 19, no. 9, pp. 789–792, Feb. 2010. [8] S. H. Lee, Y. H. Chuang, S. L. Jang, and C. C. Chen, “Low-phase noise Hartley differential CMOS voltage controlled oscillator,” IEEE Microw. Wirel. Compon. Lett., vol. 17, no. 2, pp. 889–893, Feb. 2007. [9] T.-P. Wang, “A K-band low-power Colpitts VCO with voltage-tocurrent positive-feedback network in 0.18 μm CMOS,” IEEE Microw. Wirel. Compon. Lett., vol. 21, no. 4, pp. 218–220, Apr. 2011.
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[10] C. C. Li, T. P. Wang, C. C. Kuo, M. C. Chuang, and H. Wang, “A 21 GHz complementary transformer-coupled CMOS VCO,” IEEE Microw. Wirel. Compon. Lett., vol. 16, no. 4, pp. 278–280, Apr. 2008. [11] S. L. Liu, K. H. Chen, T. Chang, and A. Chin, “A low-power Kband CMOS VCO with four-coil transformer feedback,” IEEE Microw. Wirel. Compon. Lett., vol. 20, no. 8, pp. 459–461, Aug. 2010. [12] K. Kwok and J. R. Long, “A 23-to-29 GHz transconductor-tuned VCO MMIC in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2878–2886, Dec. 2007. [13] S. Wang, B.-Z. Huang, and Z.-K. Li, “A miniaturized 10/24-GHz rat-race coupler using synthetic transmission lines on glass substrate,” IEICE Electron. Express, vol. 8, no. 17, pp. 1425–1430, Sep. 2011. [14] D. Y. Jung and C. S. Park, “Power efficient Ka-band low phase noise VCO in 0.13 μm CMOS,” Electron. Lett., vol. 44, no. 10, pp. 628–630, May 2008. [15] J. Yang, C. Y. Kim, D. W. Kim, and S. Hong, “Design of a 24 GHz CMOS VCO with an asymmetric-width transformer,” IEEE Trans. Circuit Syst. II, vol. 57, no. 3, pp. 173–177, Mar. 2010. [16] D. Ozis, N. Neihart, and D. Allstot, “Differential VCO and passive frequency doubler in 0.18 μm CMOS for 24 GHz applications,” in Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symp., 2006, pp. 36–39.
Sen Wang (S’05–M’10) was born in Yi-lan, Taiwan, in 1982. He received the B.S. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 2004, and the M.S. and Ph.D. degrees from the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2006 and 2009, respectively. He joined the faculty of the Department of Electronic Engineering, National Taipei University of Technology in February 2010. He is currently an associate professor. His research interests include the design of microwave/millimeter-wave passive circuits, CMOS RF integrated circuits, and radar system engineering.
