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Fluorinated polymer-grafted organic dielectrics for organic field-effect transistors with low-voltage and electrical stability† Kyunghun Kim,a Haekyoung Kim,*b Se Hyun Kim*c and Chan Eon Park*a The electrical stabilities of low-voltage organic field-effect transistors (OFETs) were improved by applying graftable fluorinated polymer (gPFS) layers onto poly(4-vinyl phenol)-based cross-linked dielectrics (cPVP). As a result, a smooth and hydrophobic surface was formed, and the dielectric film displayed a low-leakage current density. The chemisorbed gPFS groups enabled the solution processing of an overlying 5,11bis(triethylsilylethynyl)anthradithiophene semiconductor, which formed favorable terrace-like crystalline structures after solvent annealing. The top-contact OFETs showed superior operational stability compared
Received 1st April 2015, Accepted 24th May 2015
to cPVP-based OFETs. Hysteresis was negligible, and the off-current of the transfer curve was one order
DOI: 10.1039/c5cp01909e
after a sustained gate bias stress for 1 h decreased significantly after introduction of the hydrophobic gPFS
of magnitude lower than that obtained from cPVP-based OFETs. The threshold voltage shift measured treatment; the energetic barrier to creating charge trapping sites increased, and the trap distribution
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narrowed, as supported by the stretched exponential function model.
1. Introduction Organic field-effect transistors (OFETs) with low operating voltages are necessary for future commercial applications that require reduced power consumption for portable and wearable electronic devices. Typically, OFETs with low operating voltages have been achieved by using high-capacitance dielectrics.1,2 The capacitance Ci per unit area of a dielectric layer is expressed by Ci = ke0/d, where k is the dielectric constant, e0 is the permittivity in a vacuum, and d is the thickness of the dielectric layer. A high Ci may be achieved by using a high-k inorganic dielectric material such as aluminum oxide (k = 7), hafnium oxide (k = 10), or zirconium oxide (k = 25), or by reducing d while maintaining a low leakage current through the dielectric layer.3–5 Polymer dielectric materials, which are necessary for flexible electronic devices, generally have k o 4, except for some polymers, such as polyvinylidene fluoride, poly(vinyl alcohol).6,7
a
POSTECH Organic Electronics Laboratory, Polymer Research Institute, Department of Chemical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea. E-mail: [email protected]; Fax: +82-54-279-8298; Tel: +82-54-279-2269 b School of Materials Science and Engineering, Yeungnam University, Gyeongsan 712-749, Korea. E-mail: [email protected]; Fax: +82-53-810-4628; Tel: +82-53-810-2536 c School of Chemical Engineering, Yeungnam University, Gyeongsan 712-749, Korea. E-mail: [email protected]; Fax: +82-53-810-4686; Tel: +82-53-810-2788 † Electronic supplementary information (ESI) available. See DOI: 10.1039/ c5cp01909e
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Therefore, reducing d provides an efficient approach to obtaining a high value of Ci for low-voltage operation. Poly(4-vinylphenol) (PVP) has been used extensively in this capacity because it has a relatively high k E 4 and can be easily cross-linked by a chemical reaction between the hydroxyl groups in the PVP backbone and cross-linking agents, such as poly(melamine-co-formaldehyde) methylated (PMFA), 4,4 0 -(hexafluoroisopropylidene)diphthalic anhydride, and pentaerythritol tetra(3-mercapto propionate). Several studies have reported that a few tens of nanometersthick cross-linked PVP dielectric layers permit the corresponding OFETs to operate at |5 V|.8–11 However, it is difficult to fully cross-link PVP polymer chains because the molecular motions of the polymer chains decrease due to the increase in molecular weight upon cross-linking. As a result, a certain number of hydroxyl groups in the PVP remain even after cross-linking. In general, hydroxyl groups present in the dielectric layer of an OFET can trap charges at the semiconductor/dielectric interface, thereby introducing operational problems in the OFETs, such as a decrease in the field-effect mobility mFET, hysteresis behavior, and a threshold voltage shift DVth under gate-bias stress.12 Therefore, to realize highly reliable PVP-based OFETs with low operational voltages, the quantity of hydroxyl groups at the dielectric interface must be reduced. In our previous report, the device stabilities of pentacene and N,N 0 -ditridecyl perylene diimide-based OFETs were improved significantly by the introduction of polypentafluorostyrene (PFS)-based graftable polymer nanolayers (gPFS) as an interface engineering material between the semiconductor and SiO2
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Fig. 1
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Chemical structures of the materials and schematic of the top-contact-electrode OFETs investigated in this study.
dielectric layers.13 A 4 nm-thick gPFS layer effectively passivates the hydroxyl groups present on the SiO2 surface as a consequence of a chemical reaction between the gPFS and the SiO2 surface. The excellent device stabilities of the OFETs relied on the efficient coverage of the gPFS, which consisted of C–F bonds that provided a low surface energy and chemical inertness. However, the operating voltages of the OFETs prepared in this way were unfortunately high (40 V) due to the low capacitance (about 10 nF cm2) of the 300 nm-thick SiO2 dielectric. In the present study, with the goal of achieving low-voltage operation and excellent electrical stability in the OFETs, we introduced a gPFS treatment to the 40 nm-thick cross-linked PVP polymer dielectrics (cPVP) (Fig. 1). Additionally, the universal applicability of gPFS onto various dielectric films including oxides (Al2O3, TiO2) and polystyrene (PS) polymers was also investigated. A solution-processed 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) semiconductor was grown on the gPFS-treated cPVP (F-cPVP) dielectric. The corresponding OFETs yielded mFET = 0.80 cm2 V1 s1, negligible hysteresis at a low operating voltage (3 V to 3 V), and excellent electrical stabilities under an applied gate bias of 3 V for 1 h. Stretched exponential function modeling was used to quantify the electrical stability of the OFETs, revealing that the gPFS treatment of the cPVP films increased the energetic barriers to creating charge traps at the semiconductor/dielectric interface and narrowed the trap distribution.
2. Experimental Sample preparation Silicon substrates were cleaned using acetone and UV-ozone exposure. TES-ADT was synthesized following established procedures.14
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To confirm the applicability of gPFS with various substrates, polymers (cPVP and PS) and metal oxides (Al2O3, TiO2) films were prepared using plasma-enhanced atomic layer deposition (PEALD) and spin-coating methods, respectively. PVP, PMFA, triethylamine (Net3), mercaptopropyltrimethoxysilane (MPS), methyl ethyl ketone (MEK), PFS, and PS were purchased from Aldrich or Polymer Source Inc., respectively. The cPVP films were fabricated by blending the cross-linker PMFA into the PVP in a PVP : PMFA weight ratio of 3 : 1 in N,N 0 -dimethyl formamide. A 2 wt% solution was spin-coated onto a 40 nm-thick Al gate patterned glass substrate, followed by a thermal annealing process in a vacuum oven at 160 1C for 1 h. 100 nm-thick PS film was formed by spin-casting 4 wt% PS solution in toluene. Subsequent UV- and O2 plasma-treatment, respectively, made the film cross-link and generated hydroxyl groups on the surface for the chemisorption with gPFS. 50 nm-thick Al2O3 and TiO2 films were deposited by a previously reported PEALD method.15 The prepared dielectric films (Al2O3, TiO2, cPVP, and PS) were treated by a synthesized gPFS. To perform a para-fluorine click reaction, the PFS precursor polymer (20 mg) was dissolved in MEK and stirred at 40 1C for 5 h in the presence of MPS (5 mL) and the Net3 catalyst (17.5 mL).13 The solution was spin-coated onto the films, and the resulting films were annealed at 120 1C for 1 h. The unreacted residue was removed by rinsing the annealed samples in excess amounts of MEK, followed by sonication in a bath for 3 min. Solution-processed TES-ADT films were spin-coated onto the cPVP dielectrics from an 0.8 wt% dichloroethane (DCE) solution in a N2-purged glove box (H2O, O2 o 0.1 ppm), followed by a solvent annealing process in a closed jar under DCE vapor for 15–20 min. Thermal evaporation of Au onto the TES-ADT electrodes through a shadow mask yielded top-contact
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PCCP Table 1
Paper Surface energies of the organic gate dielectrics 2
Gate dielectrics
ywater
yDII
gps
cPVP F-cPVP PFS
72 100 100
30 60 60
6.39 0.47 0.47
[mJ m ]
gds
2
[mJ m ]
39.12 28.3 28.3
2
gs [mJ m ] 45.51 28.77 28.77
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electrode OFETs. The channel length (L) and width (W ) were 100 and 1000 um, respectively. Characterization The surface morphologies were characterized using atomic force microscopy (AFM) (Multimode SPM, Digital Instruments) and X-ray Photoemission Spectroscopy (XPS) with a Mg Ka X-ray source at 1253.6 eV. Film thicknesses were determined using an ellipsometer ( J.A. Woollam Co. Inc.). The surface energies of the dielectrics films were evaluated by measuring the contact angles of two test liquids: water (ywater) and diiodomethane (yDII). The dispersion (gds) and polar components (gps) of the surface energy were obtained, and the total surface energy (gs) was calculated from the sum of these components according to the equation: 1 þ cos y ¼
2 gds
1 2
gds
glv
1 2
þ
2 gps
1 2
gplv
1 2
glv p
where glv is the surface energy of the test liquid and gdlv and glv refer to the dispersive and polar components, respectively. (The data are summarized in Table 1). The value of Ci was measured using an HP4284A Precision LCR meter (Agilent Tech.). All the electrical measurements were carried out in a N2-purged globe box, using a Keithley 4200 SCS. The field-effect mobility (mFET) and Vth of the TES-ADT OFETs were calculated in the saturation regime using the equation, ID = mFETCi(W/2L) (VG Vth)2.
3. Results and discussion To confirm that gPFS was chemisorbed onto the cPVP surface as a consequence of a chemical reaction between the methoxy groups of gPFS and the residual hydroxyl groups of cPVP, XPS and surface energy gs were measured in samples of cPVP film and F-cPVP film. The XPS profiles (Fig. 2a) of the cPVP sample included only O 1s and N 1s peaks, which corresponded to the PVP and PMFA moieties, respectively. The XPS profile of the F-cPVP included F 1s peaks due to the gPFS layer, and showed lower intensities of O 1s and N 1s peaks compared with in the cPVP spectra. cPVP had a gs = 45.5 mJ m2, whereas F-cPVP had a gs = 28.7 mJ m2, which is comparable to the gs of the as-spun PFS (Table 1). These results suggest that gPFS was grafted well onto cPVP to form a robust fluorinated film on its surface. The gs and XPS measurements on Al2O3, TiO2, and PS films extended the usability of gPFS. They showed gs values similar to those measured from gPFS-treated cPVP film (Fig. 2b and Fig. S1a, ESI†). XPS measurement on gPFS-treated PS film (F-PS) revealed a discernible F 1s peak when gPFS was applied onto the UV- and O2 plasma-treated PS film (Fig. S1b, ESI†). These results imply
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that gPFS was successfully grafted onto a variety of dielectric substrates containing surface hydroxyl groups such as the cPVP film. Generally, the polar dielectric surfaces in OFETs are typically treated to enhance their hydrophobicity using self-assembled monolayers (SAMs), such as hexamethyldisilazane, octadecyltrichlorosilane, or octyltrichlorosilane;16–18 however, SAM treatment has revealed that the packing density depends on the underlying substrate, leading to differences in the SAM ordering, which can affect the growth of the semiconductor layer.19 Furthermore, the relatively short length of SAM molecules compared with conventional polymers are not sufficient to guarantee full coverage of the underlying polar substrate. For these reasons, SAMs treated on a cPVP surface induced a lower hydrophobicity than that based on a SiO2 surface. Consequently, our gPFS treatment must be one of the most efficient surface treatments for improving hydrophobicity of a polar substrate. The surface morphologies of the cPVP and F-cPVP dielectrics were examined using AFM methods. As shown in Fig. 3, both samples displayed smooth surfaces with no significant features, and their RMS roughness values were 0.440 (cPVP) and 0.449 nm (F-cPVP). The surface roughness of a dielectric can influence the molecular orientations of the overlying semiconductor layer. A rough surface hinders the diffusion of growing semiconductors, thereby inducing grain boundaries and lowering the crystallinity. It has been reported that a surface roughness below 1 nm is sufficient to induce efficient semiconductor growth.20,21 Fig. 4 shows the current density–electric field characteristics of F-cPVP and cPVP films that were sandwiched between a top Au dot and a bottom Au substrate. The device structure is described in the inset. Both the F-cPVP and cPVP films yielded current densities below 107 A cm2 under an electric field of 1.5 MV cm1, although the former exhibited a slightly lower current density than the latter at a relatively high electric field (exceeding 1 MV cm1). cPVP tends to maintain good insulating properties due to its cross-linked structure. Because free volumes within a dielectric film can act as leakage pathways, denser dielectric structures can reduce the current density through a film. Many studies have reported the preparation of OFETs that operate at low voltages (o5 V) based on ultrathin (B50 nm) cPVP dielectrics.8,10 The introduction of a fluorinated layer onto the dielectrics can further improve the insulating properties, possibly by enhancing the chemical inertness.22 The cPVP and F-cPVP films exhibited Ci values of 70 and 59 nF cm2, respectively, for film thicknesses of 40 (cPVP) and 44 nm (F-cPVP). Both of the Ci values were high enough for the OFETs to operate at low voltages. In order to figure out the growth behavior of a solutionprocessed semiconductor on the F-cPVP dielectric, TES-ADT films were spin-cast and then were annealed in solvent vapor to form crystalline structures. Fig. 5a and d show polarized optical microscopy images of the solvent-annealed TES-ADT films on cPVP and F-cPVP dielectrics, respectively. The low surface roughness of the bottom cPVP and F-cPVP layers induced the TES-ADT molecules to grow up to millimeter-sized crystals without hindrance from the surface roughness. The morphologies
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Fig. 2 (a) F 1s, O 1s, N 1s XPS profiles of cPVP (black) and F-cPVP (blue) devices and (b) optical images of seeded water drops on the various substrates.
Fig. 3
AFM topographies of the (a) cPVP, (b) F-cPVP dielectric films.
of the TES-ADT films analyzed by AFM revealed that both films exhibited similar morphologies, with large terrace-like crystalline structures (Fig. 5b and e). The heights of each terrace agreed with the c-axis length of the TES-ADT crystal unit cell (16.1 Å), suggesting that the flat grains were stacked along the out-of-plane direction.14 The molecular orientations were further investigated by collecting grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns from the films. The GIWAXS patterns shown in Fig. 5c and f include intense (001) and {hk} plane reflections along the qz (out-ofplane) and qxy (in-plane) axes, respectively, suggesting that the TESADT molecules on both dielectric films formed 3D multi-layered triclinic structures. It should be noted that the triclinic crystalline structures of the TES-ADT films grown on both cPVP and F-cPVP dielectrics were comparable to those grown on a variety of substrates reported to date,19 possibly because the crystal structures of the TES-ADT films depend strongly on the post solvent annealing conditions rather than on the dielectric surfaces properties (surface energy or functional groups).23–25
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Fig. 4 Current density–electric field characteristics of the F-cPVP and cPVP gate dielectrics. Inset: device structure.
Solvent-annealing processes assist molecules in forming triclinic crystalline structures and yielding much better electrical performances compared to those observed in thermally-annealed monoclinic structures.26 The electrical characteristics of the TES-ADT OFETs prepared with cPVP or F-cPVP dielectrics were obtained by fabricating topcontact bottom-gate transistor architectures. Fig. 6 shows the transfer and output characteristics typical of the two OFETs. Despite having similar crystal morphologies in the TES-ADT films prepared on both dielectrics, the mFET values of the F-cPVP device (0.80 0.07 cm2 V1 s1) were higher than those of the cPVP device (0.62 0.06 cm2 V1 s1), as summarized in
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Fig. 5 Polarized optical microscopy images (a, d), AFM topographies (b, e), and GIWAXS patterns (c, f), obtained from the TES-ADT films deposited onto (top) cPVP, (bottom) F-cPVP dielectric films.
Table 2. Previous studies have reported that polar functionalities (such as hydroxyl groups) act as charge trapping sites that degrade the OFET performances.10,11,13,27–29 The higher mFET values observed in the F-cPVP device were attributed to the effective passivation of the unreacted hydroxyl groups on the cPVP surface using gPFS. In addition, the F-cPVP device exhibited lower Vth (0.042 0.017 V) and SS (0.110 10 V per decade) values compared with those measured from the cPVP device (which yielded Vth and SS values of 0.546 0.124 V and 0.110 10 V per decade, respectively). The reduced Vth and SS are advantageous for high-speed low-power-consumption electronics. These results may be due to the highly electronegative fluorine atoms that generate a local electric field and accumulate holes, in addition to lower amounts of charge trap sites.16
Table 2 Electrical characteristics of the solution-processed TES-ADT semiconductor-based OFETs prepared with either of the two organic dielectrics
Gate dielectrics m [cm2 V1 s1] Vth [V] cPVP F-cPVP
0.62 0.06 0.80 0.07
Ion/Ioff
SS [mV]
0.546 0.124 2.25 105 186 0.042 0.017 1.46 106 110
In the aspect of operational stability, F-cPVP OFETs showed much more stable operation than cPVP-based OFETs. The off-currents of the cPVP OFETs were one order of magnitude higher than the values from the F-cPVP-based OFETs, as shown in Fig. 6a. These results suggested that a high leakage current could flow through the cPVP dielectrics, even when the OFETs were turned off. The higher leakage current could
Fig. 6 (a) ID–VG transfer characteristics of the TES-ADT OFETs prepared with the gate dielectrics. ID–VD output characteristics of the OFETs prepared with (b) F-cPVP and (c) cPVP gate dielectrics.
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Fig. 7 ID–VG transfer characteristics of the TES-ADT OFETs prepared based on the (a) F-cPVP or (b) cPVP gate dielectrics, under a gate bias-stress of VG = 3 V over 1 h.
increase the static power consumption of the integrated circuits and reduce the durability of the dielectric films. Hysteresis, which is defined as the difference between the off-to-on and on-to-off swept transfer curves, was observed with an anticlockwise behavior due to the hole traps caused by the residual hydroxyl groups in the cPVP films.12 Applying a negative VG during the off-toon gate sweep filled the hole traps with mobile holes, and these traps remained filled during the on-to-off gate sweep, thereby reducing the ID. Therefore, the hole traps contributed to the anticlockwise hysteresis behavior. On the other hand, the F-cPVP-based OFETs maintained an off-current below 1011 A and showed negligible hysteresis in the transfer curves. The bias stabilities of the OFETs employing cPVP and F-cPVP dielectrics were further investigated by measuring the values of Vth as a function of time under a sustained gate bias (Fig. 7). A VG of 3 V was applied to the devices over an hour, and VD was held constant at 0 V. The ID–VG transfer curves shifted toward negative values without changing mFET. The DVth values obtained from the cPVP-based OFETs were 1.31 V, which is high considering the operational voltage of 3 V. These results were related to the presence of deep energy level traps generated by hydroxyl groups at the dielectric surface. By contrast, the F-cPVP-based OFETs showed much lower DVth values of 0.31 V, suggesting that the fluorine groups at the F-cPVP surface suppressed trap creation, as revealed by several previous reports.13,30,31 The experimental DVth values were modeled using a stretched exponential function:32,33 Vth Vth;i ¼1 VG Vth;i
1 1 ðEth EA Þ ða 1Þ 1 exp kB T 0
Table 3 Values of EA and kBT0 in the TES-ADT OFETs based on cPVP and F-cPVP dielectric layers
EA (eV) kBT0 (eV)
Phys. Chem. Chem. Phys.
F-cPVP
cPVP
0.051 0.008 0.550 0.025
0.095 0.008 0.474 0.016
where Vth,i is the initial Vth, EA is the activation energy typical of trap creation, kBT0 is the slope of the activation energy distribution, and a is a constant. Eth corresponded to the thermalization energy, defined by kBT0 ln(nt). Here, kB and n are the Boltzmann constant and the frequency of attempted barrier crossing, respectively. The value of DVth as a function of the bias-stress time could be clearly fitted to the equation, as shown in Fig. 7c. The values of n and a were set to 105 Hz and 1.5, respectively, to obtain an optimal fit, which was in good agreement with the values reported previously. The EA and kBT0 values measured from the two OFETs are summarized in Table 3. The F-cPVP-based OFETs showed higher EA values of 0.550 0.025 eV (0.474 0.016 eV in the case of the cPVP-based OFETs) and lower kBT0 values of 0.051 0.008 eV (0.095 0.008 eV), suggesting that the F-cPVP dielectrics reinforced the resistance against trap creation at the semiconductor/dielectric interface and also narrowed the trap energy distribution. Previous reports indicated that the presence of a fluorinated polymer at the semiconductor/dielectric interface could increase the gap between the HOMO level of the dielectric and that of the semiconductor, thereby increasing the energetic barrier to charge carrier trapping at the interface.30 Therefore, this is the reason why F-cPVP-based OFETs show a higher gate bias stability compared to cPVP based OFETs.
4. Conclusions In summary, we demonstrated the development of electrically stable OFETs that operate at low voltages based on F-cPVP gate dielectrics. The gPFS was synthesized using a simple approach and chemisorbed onto the cPVP dielectrics to passivate the residual hydroxyl groups, forming a 4 nm-thick smooth surface. The hydrophobic surface reduced the leakage current density relative to that observed in the cPVP films. The TES-ADT thin films grown on F-cPVP formed large and flat grains after solvent annealing, and OFETs prepared from these films displayed higher mFET values compared to the cPVP-based device due to the effective coverage of residual hydroxyl groups on the cPVP. Operational and bias stability tests revealed that the F-cPVPbased OFETs showed a low off-current, negligible hysteresis, and a DVth of only 0.31 V. The results were fitted to a stretched
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exponential model, which suggested that the F-cPVP dielectric suppressed trap creation by increasing the activation energy and narrowing the trap energy distribution.
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Acknowledgements This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (2014R1A2A1A05004993), and was also supported by the Yeungnam University research grants in 2014.
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Fluorinated polymer-grafted organic dielectrics for organic field-effect transistors with low-voltage and electrical stability† Kyunghun Kim,a Haekyoung Kim,*b Se Hyun Kim*c and Chan Eon Park*a The electrical stabilities of low-voltage organic field-effect transistors (OFETs) were improved by applying graftable fluorinated polymer (gPFS) layers onto poly(4-vinyl phenol)-based cross-linked dielectrics (cPVP). As a result, a smooth and hydrophobic surface was formed, and the dielectric film displayed a low-leakage current density. The chemisorbed gPFS groups enabled the solution processing of an overlying 5,11bis(triethylsilylethynyl)anthradithiophene semiconductor, which formed favorable terrace-like crystalline structures after solvent annealing. The top-contact OFETs showed superior operational stability compared
Received 1st April 2015, Accepted 24th May 2015
to cPVP-based OFETs. Hysteresis was negligible, and the off-current of the transfer curve was one order
DOI: 10.1039/c5cp01909e
after a sustained gate bias stress for 1 h decreased significantly after introduction of the hydrophobic gPFS
of magnitude lower than that obtained from cPVP-based OFETs. The threshold voltage shift measured treatment; the energetic barrier to creating charge trapping sites increased, and the trap distribution
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narrowed, as supported by the stretched exponential function model.
1. Introduction Organic field-effect transistors (OFETs) with low operating voltages are necessary for future commercial applications that require reduced power consumption for portable and wearable electronic devices. Typically, OFETs with low operating voltages have been achieved by using high-capacitance dielectrics.1,2 The capacitance Ci per unit area of a dielectric layer is expressed by Ci = ke0/d, where k is the dielectric constant, e0 is the permittivity in a vacuum, and d is the thickness of the dielectric layer. A high Ci may be achieved by using a high-k inorganic dielectric material such as aluminum oxide (k = 7), hafnium oxide (k = 10), or zirconium oxide (k = 25), or by reducing d while maintaining a low leakage current through the dielectric layer.3–5 Polymer dielectric materials, which are necessary for flexible electronic devices, generally have k o 4, except for some polymers, such as polyvinylidene fluoride, poly(vinyl alcohol).6,7
a
POSTECH Organic Electronics Laboratory, Polymer Research Institute, Department of Chemical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea. E-mail: [email protected]; Fax: +82-54-279-8298; Tel: +82-54-279-2269 b School of Materials Science and Engineering, Yeungnam University, Gyeongsan 712-749, Korea. E-mail: [email protected]; Fax: +82-53-810-4628; Tel: +82-53-810-2536 c School of Chemical Engineering, Yeungnam University, Gyeongsan 712-749, Korea. E-mail: [email protected]; Fax: +82-53-810-4686; Tel: +82-53-810-2788 † Electronic supplementary information (ESI) available. See DOI: 10.1039/ c5cp01909e
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Therefore, reducing d provides an efficient approach to obtaining a high value of Ci for low-voltage operation. Poly(4-vinylphenol) (PVP) has been used extensively in this capacity because it has a relatively high k E 4 and can be easily cross-linked by a chemical reaction between the hydroxyl groups in the PVP backbone and cross-linking agents, such as poly(melamine-co-formaldehyde) methylated (PMFA), 4,4 0 -(hexafluoroisopropylidene)diphthalic anhydride, and pentaerythritol tetra(3-mercapto propionate). Several studies have reported that a few tens of nanometersthick cross-linked PVP dielectric layers permit the corresponding OFETs to operate at |5 V|.8–11 However, it is difficult to fully cross-link PVP polymer chains because the molecular motions of the polymer chains decrease due to the increase in molecular weight upon cross-linking. As a result, a certain number of hydroxyl groups in the PVP remain even after cross-linking. In general, hydroxyl groups present in the dielectric layer of an OFET can trap charges at the semiconductor/dielectric interface, thereby introducing operational problems in the OFETs, such as a decrease in the field-effect mobility mFET, hysteresis behavior, and a threshold voltage shift DVth under gate-bias stress.12 Therefore, to realize highly reliable PVP-based OFETs with low operational voltages, the quantity of hydroxyl groups at the dielectric interface must be reduced. In our previous report, the device stabilities of pentacene and N,N 0 -ditridecyl perylene diimide-based OFETs were improved significantly by the introduction of polypentafluorostyrene (PFS)-based graftable polymer nanolayers (gPFS) as an interface engineering material between the semiconductor and SiO2
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Fig. 1
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Chemical structures of the materials and schematic of the top-contact-electrode OFETs investigated in this study.
dielectric layers.13 A 4 nm-thick gPFS layer effectively passivates the hydroxyl groups present on the SiO2 surface as a consequence of a chemical reaction between the gPFS and the SiO2 surface. The excellent device stabilities of the OFETs relied on the efficient coverage of the gPFS, which consisted of C–F bonds that provided a low surface energy and chemical inertness. However, the operating voltages of the OFETs prepared in this way were unfortunately high (40 V) due to the low capacitance (about 10 nF cm2) of the 300 nm-thick SiO2 dielectric. In the present study, with the goal of achieving low-voltage operation and excellent electrical stability in the OFETs, we introduced a gPFS treatment to the 40 nm-thick cross-linked PVP polymer dielectrics (cPVP) (Fig. 1). Additionally, the universal applicability of gPFS onto various dielectric films including oxides (Al2O3, TiO2) and polystyrene (PS) polymers was also investigated. A solution-processed 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) semiconductor was grown on the gPFS-treated cPVP (F-cPVP) dielectric. The corresponding OFETs yielded mFET = 0.80 cm2 V1 s1, negligible hysteresis at a low operating voltage (3 V to 3 V), and excellent electrical stabilities under an applied gate bias of 3 V for 1 h. Stretched exponential function modeling was used to quantify the electrical stability of the OFETs, revealing that the gPFS treatment of the cPVP films increased the energetic barriers to creating charge traps at the semiconductor/dielectric interface and narrowed the trap distribution.
2. Experimental Sample preparation Silicon substrates were cleaned using acetone and UV-ozone exposure. TES-ADT was synthesized following established procedures.14
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To confirm the applicability of gPFS with various substrates, polymers (cPVP and PS) and metal oxides (Al2O3, TiO2) films were prepared using plasma-enhanced atomic layer deposition (PEALD) and spin-coating methods, respectively. PVP, PMFA, triethylamine (Net3), mercaptopropyltrimethoxysilane (MPS), methyl ethyl ketone (MEK), PFS, and PS were purchased from Aldrich or Polymer Source Inc., respectively. The cPVP films were fabricated by blending the cross-linker PMFA into the PVP in a PVP : PMFA weight ratio of 3 : 1 in N,N 0 -dimethyl formamide. A 2 wt% solution was spin-coated onto a 40 nm-thick Al gate patterned glass substrate, followed by a thermal annealing process in a vacuum oven at 160 1C for 1 h. 100 nm-thick PS film was formed by spin-casting 4 wt% PS solution in toluene. Subsequent UV- and O2 plasma-treatment, respectively, made the film cross-link and generated hydroxyl groups on the surface for the chemisorption with gPFS. 50 nm-thick Al2O3 and TiO2 films were deposited by a previously reported PEALD method.15 The prepared dielectric films (Al2O3, TiO2, cPVP, and PS) were treated by a synthesized gPFS. To perform a para-fluorine click reaction, the PFS precursor polymer (20 mg) was dissolved in MEK and stirred at 40 1C for 5 h in the presence of MPS (5 mL) and the Net3 catalyst (17.5 mL).13 The solution was spin-coated onto the films, and the resulting films were annealed at 120 1C for 1 h. The unreacted residue was removed by rinsing the annealed samples in excess amounts of MEK, followed by sonication in a bath for 3 min. Solution-processed TES-ADT films were spin-coated onto the cPVP dielectrics from an 0.8 wt% dichloroethane (DCE) solution in a N2-purged glove box (H2O, O2 o 0.1 ppm), followed by a solvent annealing process in a closed jar under DCE vapor for 15–20 min. Thermal evaporation of Au onto the TES-ADT electrodes through a shadow mask yielded top-contact
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PCCP Table 1
Paper Surface energies of the organic gate dielectrics 2
Gate dielectrics
ywater
yDII
gps
cPVP F-cPVP PFS
72 100 100
30 60 60
6.39 0.47 0.47
[mJ m ]
gds
2
[mJ m ]
39.12 28.3 28.3
2
gs [mJ m ] 45.51 28.77 28.77
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electrode OFETs. The channel length (L) and width (W ) were 100 and 1000 um, respectively. Characterization The surface morphologies were characterized using atomic force microscopy (AFM) (Multimode SPM, Digital Instruments) and X-ray Photoemission Spectroscopy (XPS) with a Mg Ka X-ray source at 1253.6 eV. Film thicknesses were determined using an ellipsometer ( J.A. Woollam Co. Inc.). The surface energies of the dielectrics films were evaluated by measuring the contact angles of two test liquids: water (ywater) and diiodomethane (yDII). The dispersion (gds) and polar components (gps) of the surface energy were obtained, and the total surface energy (gs) was calculated from the sum of these components according to the equation: 1 þ cos y ¼
2 gds
1 2
gds
glv
1 2
þ
2 gps
1 2
gplv
1 2
glv p
where glv is the surface energy of the test liquid and gdlv and glv refer to the dispersive and polar components, respectively. (The data are summarized in Table 1). The value of Ci was measured using an HP4284A Precision LCR meter (Agilent Tech.). All the electrical measurements were carried out in a N2-purged globe box, using a Keithley 4200 SCS. The field-effect mobility (mFET) and Vth of the TES-ADT OFETs were calculated in the saturation regime using the equation, ID = mFETCi(W/2L) (VG Vth)2.
3. Results and discussion To confirm that gPFS was chemisorbed onto the cPVP surface as a consequence of a chemical reaction between the methoxy groups of gPFS and the residual hydroxyl groups of cPVP, XPS and surface energy gs were measured in samples of cPVP film and F-cPVP film. The XPS profiles (Fig. 2a) of the cPVP sample included only O 1s and N 1s peaks, which corresponded to the PVP and PMFA moieties, respectively. The XPS profile of the F-cPVP included F 1s peaks due to the gPFS layer, and showed lower intensities of O 1s and N 1s peaks compared with in the cPVP spectra. cPVP had a gs = 45.5 mJ m2, whereas F-cPVP had a gs = 28.7 mJ m2, which is comparable to the gs of the as-spun PFS (Table 1). These results suggest that gPFS was grafted well onto cPVP to form a robust fluorinated film on its surface. The gs and XPS measurements on Al2O3, TiO2, and PS films extended the usability of gPFS. They showed gs values similar to those measured from gPFS-treated cPVP film (Fig. 2b and Fig. S1a, ESI†). XPS measurement on gPFS-treated PS film (F-PS) revealed a discernible F 1s peak when gPFS was applied onto the UV- and O2 plasma-treated PS film (Fig. S1b, ESI†). These results imply
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that gPFS was successfully grafted onto a variety of dielectric substrates containing surface hydroxyl groups such as the cPVP film. Generally, the polar dielectric surfaces in OFETs are typically treated to enhance their hydrophobicity using self-assembled monolayers (SAMs), such as hexamethyldisilazane, octadecyltrichlorosilane, or octyltrichlorosilane;16–18 however, SAM treatment has revealed that the packing density depends on the underlying substrate, leading to differences in the SAM ordering, which can affect the growth of the semiconductor layer.19 Furthermore, the relatively short length of SAM molecules compared with conventional polymers are not sufficient to guarantee full coverage of the underlying polar substrate. For these reasons, SAMs treated on a cPVP surface induced a lower hydrophobicity than that based on a SiO2 surface. Consequently, our gPFS treatment must be one of the most efficient surface treatments for improving hydrophobicity of a polar substrate. The surface morphologies of the cPVP and F-cPVP dielectrics were examined using AFM methods. As shown in Fig. 3, both samples displayed smooth surfaces with no significant features, and their RMS roughness values were 0.440 (cPVP) and 0.449 nm (F-cPVP). The surface roughness of a dielectric can influence the molecular orientations of the overlying semiconductor layer. A rough surface hinders the diffusion of growing semiconductors, thereby inducing grain boundaries and lowering the crystallinity. It has been reported that a surface roughness below 1 nm is sufficient to induce efficient semiconductor growth.20,21 Fig. 4 shows the current density–electric field characteristics of F-cPVP and cPVP films that were sandwiched between a top Au dot and a bottom Au substrate. The device structure is described in the inset. Both the F-cPVP and cPVP films yielded current densities below 107 A cm2 under an electric field of 1.5 MV cm1, although the former exhibited a slightly lower current density than the latter at a relatively high electric field (exceeding 1 MV cm1). cPVP tends to maintain good insulating properties due to its cross-linked structure. Because free volumes within a dielectric film can act as leakage pathways, denser dielectric structures can reduce the current density through a film. Many studies have reported the preparation of OFETs that operate at low voltages (o5 V) based on ultrathin (B50 nm) cPVP dielectrics.8,10 The introduction of a fluorinated layer onto the dielectrics can further improve the insulating properties, possibly by enhancing the chemical inertness.22 The cPVP and F-cPVP films exhibited Ci values of 70 and 59 nF cm2, respectively, for film thicknesses of 40 (cPVP) and 44 nm (F-cPVP). Both of the Ci values were high enough for the OFETs to operate at low voltages. In order to figure out the growth behavior of a solutionprocessed semiconductor on the F-cPVP dielectric, TES-ADT films were spin-cast and then were annealed in solvent vapor to form crystalline structures. Fig. 5a and d show polarized optical microscopy images of the solvent-annealed TES-ADT films on cPVP and F-cPVP dielectrics, respectively. The low surface roughness of the bottom cPVP and F-cPVP layers induced the TES-ADT molecules to grow up to millimeter-sized crystals without hindrance from the surface roughness. The morphologies
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Fig. 2 (a) F 1s, O 1s, N 1s XPS profiles of cPVP (black) and F-cPVP (blue) devices and (b) optical images of seeded water drops on the various substrates.
Fig. 3
AFM topographies of the (a) cPVP, (b) F-cPVP dielectric films.
of the TES-ADT films analyzed by AFM revealed that both films exhibited similar morphologies, with large terrace-like crystalline structures (Fig. 5b and e). The heights of each terrace agreed with the c-axis length of the TES-ADT crystal unit cell (16.1 Å), suggesting that the flat grains were stacked along the out-of-plane direction.14 The molecular orientations were further investigated by collecting grazing-incidence wide-angle X-ray scattering (GIWAXS) patterns from the films. The GIWAXS patterns shown in Fig. 5c and f include intense (001) and {hk} plane reflections along the qz (out-ofplane) and qxy (in-plane) axes, respectively, suggesting that the TESADT molecules on both dielectric films formed 3D multi-layered triclinic structures. It should be noted that the triclinic crystalline structures of the TES-ADT films grown on both cPVP and F-cPVP dielectrics were comparable to those grown on a variety of substrates reported to date,19 possibly because the crystal structures of the TES-ADT films depend strongly on the post solvent annealing conditions rather than on the dielectric surfaces properties (surface energy or functional groups).23–25
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Fig. 4 Current density–electric field characteristics of the F-cPVP and cPVP gate dielectrics. Inset: device structure.
Solvent-annealing processes assist molecules in forming triclinic crystalline structures and yielding much better electrical performances compared to those observed in thermally-annealed monoclinic structures.26 The electrical characteristics of the TES-ADT OFETs prepared with cPVP or F-cPVP dielectrics were obtained by fabricating topcontact bottom-gate transistor architectures. Fig. 6 shows the transfer and output characteristics typical of the two OFETs. Despite having similar crystal morphologies in the TES-ADT films prepared on both dielectrics, the mFET values of the F-cPVP device (0.80 0.07 cm2 V1 s1) were higher than those of the cPVP device (0.62 0.06 cm2 V1 s1), as summarized in
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Fig. 5 Polarized optical microscopy images (a, d), AFM topographies (b, e), and GIWAXS patterns (c, f), obtained from the TES-ADT films deposited onto (top) cPVP, (bottom) F-cPVP dielectric films.
Table 2. Previous studies have reported that polar functionalities (such as hydroxyl groups) act as charge trapping sites that degrade the OFET performances.10,11,13,27–29 The higher mFET values observed in the F-cPVP device were attributed to the effective passivation of the unreacted hydroxyl groups on the cPVP surface using gPFS. In addition, the F-cPVP device exhibited lower Vth (0.042 0.017 V) and SS (0.110 10 V per decade) values compared with those measured from the cPVP device (which yielded Vth and SS values of 0.546 0.124 V and 0.110 10 V per decade, respectively). The reduced Vth and SS are advantageous for high-speed low-power-consumption electronics. These results may be due to the highly electronegative fluorine atoms that generate a local electric field and accumulate holes, in addition to lower amounts of charge trap sites.16
Table 2 Electrical characteristics of the solution-processed TES-ADT semiconductor-based OFETs prepared with either of the two organic dielectrics
Gate dielectrics m [cm2 V1 s1] Vth [V] cPVP F-cPVP
0.62 0.06 0.80 0.07
Ion/Ioff
SS [mV]
0.546 0.124 2.25 105 186 0.042 0.017 1.46 106 110
In the aspect of operational stability, F-cPVP OFETs showed much more stable operation than cPVP-based OFETs. The off-currents of the cPVP OFETs were one order of magnitude higher than the values from the F-cPVP-based OFETs, as shown in Fig. 6a. These results suggested that a high leakage current could flow through the cPVP dielectrics, even when the OFETs were turned off. The higher leakage current could
Fig. 6 (a) ID–VG transfer characteristics of the TES-ADT OFETs prepared with the gate dielectrics. ID–VD output characteristics of the OFETs prepared with (b) F-cPVP and (c) cPVP gate dielectrics.
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Fig. 7 ID–VG transfer characteristics of the TES-ADT OFETs prepared based on the (a) F-cPVP or (b) cPVP gate dielectrics, under a gate bias-stress of VG = 3 V over 1 h.
increase the static power consumption of the integrated circuits and reduce the durability of the dielectric films. Hysteresis, which is defined as the difference between the off-to-on and on-to-off swept transfer curves, was observed with an anticlockwise behavior due to the hole traps caused by the residual hydroxyl groups in the cPVP films.12 Applying a negative VG during the off-toon gate sweep filled the hole traps with mobile holes, and these traps remained filled during the on-to-off gate sweep, thereby reducing the ID. Therefore, the hole traps contributed to the anticlockwise hysteresis behavior. On the other hand, the F-cPVP-based OFETs maintained an off-current below 1011 A and showed negligible hysteresis in the transfer curves. The bias stabilities of the OFETs employing cPVP and F-cPVP dielectrics were further investigated by measuring the values of Vth as a function of time under a sustained gate bias (Fig. 7). A VG of 3 V was applied to the devices over an hour, and VD was held constant at 0 V. The ID–VG transfer curves shifted toward negative values without changing mFET. The DVth values obtained from the cPVP-based OFETs were 1.31 V, which is high considering the operational voltage of 3 V. These results were related to the presence of deep energy level traps generated by hydroxyl groups at the dielectric surface. By contrast, the F-cPVP-based OFETs showed much lower DVth values of 0.31 V, suggesting that the fluorine groups at the F-cPVP surface suppressed trap creation, as revealed by several previous reports.13,30,31 The experimental DVth values were modeled using a stretched exponential function:32,33 Vth Vth;i ¼1 VG Vth;i
1 1 ðEth EA Þ ða 1Þ 1 exp kB T 0
Table 3 Values of EA and kBT0 in the TES-ADT OFETs based on cPVP and F-cPVP dielectric layers
EA (eV) kBT0 (eV)
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F-cPVP
cPVP
0.051 0.008 0.550 0.025
0.095 0.008 0.474 0.016
where Vth,i is the initial Vth, EA is the activation energy typical of trap creation, kBT0 is the slope of the activation energy distribution, and a is a constant. Eth corresponded to the thermalization energy, defined by kBT0 ln(nt). Here, kB and n are the Boltzmann constant and the frequency of attempted barrier crossing, respectively. The value of DVth as a function of the bias-stress time could be clearly fitted to the equation, as shown in Fig. 7c. The values of n and a were set to 105 Hz and 1.5, respectively, to obtain an optimal fit, which was in good agreement with the values reported previously. The EA and kBT0 values measured from the two OFETs are summarized in Table 3. The F-cPVP-based OFETs showed higher EA values of 0.550 0.025 eV (0.474 0.016 eV in the case of the cPVP-based OFETs) and lower kBT0 values of 0.051 0.008 eV (0.095 0.008 eV), suggesting that the F-cPVP dielectrics reinforced the resistance against trap creation at the semiconductor/dielectric interface and also narrowed the trap energy distribution. Previous reports indicated that the presence of a fluorinated polymer at the semiconductor/dielectric interface could increase the gap between the HOMO level of the dielectric and that of the semiconductor, thereby increasing the energetic barrier to charge carrier trapping at the interface.30 Therefore, this is the reason why F-cPVP-based OFETs show a higher gate bias stability compared to cPVP based OFETs.
4. Conclusions In summary, we demonstrated the development of electrically stable OFETs that operate at low voltages based on F-cPVP gate dielectrics. The gPFS was synthesized using a simple approach and chemisorbed onto the cPVP dielectrics to passivate the residual hydroxyl groups, forming a 4 nm-thick smooth surface. The hydrophobic surface reduced the leakage current density relative to that observed in the cPVP films. The TES-ADT thin films grown on F-cPVP formed large and flat grains after solvent annealing, and OFETs prepared from these films displayed higher mFET values compared to the cPVP-based device due to the effective coverage of residual hydroxyl groups on the cPVP. Operational and bias stability tests revealed that the F-cPVPbased OFETs showed a low off-current, negligible hysteresis, and a DVth of only 0.31 V. The results were fitted to a stretched
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exponential model, which suggested that the F-cPVP dielectric suppressed trap creation by increasing the activation energy and narrowing the trap energy distribution.
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Acknowledgements This work was supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIP) (2014R1A2A1A05004993), and was also supported by the Yeungnam University research grants in 2014.
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