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Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2015 Nanotechnology 26 115202 (http://iopscience.iop.org/0957-4484/26/11/115202) View the table of contents for this issue, or go to the journal homepage for more
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Nanotechnology Nanotechnology 26 (2015) 115202 (8pp)
doi:10.1088/0957-4484/26/11/115202
Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene Matin Amani1, Robert A Burke, Robert M Proie and Madan Dubey Sensors and Electron Devices Directorate, US Army Research Laboratory, Adelphi MD 20783, USA E-mail: [email protected] Received 2 October 2014, revised 1 December 2014 Accepted for publication 16 December 2014 Published 24 February 2015 Abstract
Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >107 and field effect mobilities as high as 16.4 cm2 V−1 s−1. Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W−1. Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322–1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform. S Online supplementary data available from stacks.iop.org/NANO/26/115202/mmedia Keywords: flexible electronics, integrated circuits, MoS2, graphene, heterostructures (Some figures may appear in colour only in the online journal) One of the defining factors for the next generation of electronic devices will be their ability to operate with non-standard packaging, conform to surfaces required for their specific application and have a high degree of ruggedization [1–3]. Additionally, to economically expand into these new markets, high performance electronics that are compatible with low cost fabrication, such as roll-to-roll processing, need to be developed [4]. Electronics fabricated directly on flexible substrates as well as thinned silicon chips are currently the two primary contenders for this application space. Thinned silicon provides superior performance, but relies on
conventional wafer based fabrication. Meanwhile, direct fabrication on flexible materials presents processing limitations for both layer registry and thermal budget, ultimately forcing the use of organic or amorphous channel materials with low mobility and performance. Two dimensional (2D) atomic crystals, which have been under extensive investigation since the isolation of graphene in 2004, are in a unique position to excel in flexible electronics applications due to their extreme thinness and ability to reversibly undergo high strains (as high as 12% for graphene). Additionally, they are ideally suited to either be directly deposited by inkjet printing or to be grown over large areas by chemical vapor deposition (CVD) and subsequently transferred to arbitrary flexible
1
Present address: Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA.
0957-4484/15/115202+08$33.00
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© 2015 IOP Publishing Ltd Printed in the UK
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Nanotechnology 26 (2015) 115202
substrates while preserving their electronic performance [5–9]. While much of the initial work in this area focused on graphene, which showed early promise as a device for digital electronics, it’s natural zero band-gap prevented its direct use in the area of low power logic [10]. The recent discovery and investigation of new 2D materials with semiconducting, insulating and metallic properties has resulted in several materials that hold promise to fulfill the electronic and optoelectronic roles previously not accessible with graphene. One of these materials, single layer thick molybdenum disulphide (MoS2), is being studied as a direct band gap semiconductor by numerous researchers. Several groups have demonstrated novel device structures and validated that MoS2 possesses qualities required for device scaling in next generation electronic systems [6, 11]. One of the key limiting factors in MoS2 devices is a prohibitively large contact resistance and Fermi level pinning observed for traditional metal/semiconductor junctions [12]. Limited improvements to this parasitic resistance have been made through the use of very low work function metals and vacuum annealing; the most significant milestone to date, however, has been the use of 2D graphene contacts [13, 14]. These heterojunctions have not only been shown to dramatically reduce the access resistance to MoS2 and enable Schottky barrier height tuning using graphene’s carrier density dependent work function, but they are also ideal for flexible devices since the most common point of failure in these systems are metal contacts [15]. We show for the first time in this letter that MoS2 transistors with graphene contacts, integrated circuits, non-volatile memory and photodetectors based on all CVD grown monolayer material can be integrated on a single flexible substrate while still maintaining similar electronic quality to equivalent structures fabricated on traditional substrates. In fact, the performance of our monolayer MoS2 devices represents one of the highest values obtained at room temperature, without excluding the contribution of contact resistance, on both flexible and non-flexible substrates. Continuous films of single layer MoS2 were grown on Si/ SiO2 by atmospheric pressure CVD in a hot-wall tube furnace at a substrate temperature of 700 °C using MoO3 and sulfur powders as the reactants. The substrates were cleaned with piranha solution, acetone, IPA and DI water and treated in an O2 plasma to make them hydrophilic prior to application of PTAS (perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt), which has been shown to promote the growth of monolayer MoS2 by serving as a nucleation site [16]. After growth, the presence of high quality material was confirmed by Raman and PL mapping as shown in figure S1 and discussed in the supplementary materials. Graphene was grown by low pressure chemical vapor deposition on copper foils at 1000 °C using well established techniques [4, 17]. Detailed information about the growth process is included in the supplementary information. Atomically smooth, 16 μm thick polyimide (PI) films were deposited using multiple spincoats of PI-2611 (HDMicrosystems) on pre-diced Si/SiO2 substrates. The PI samples were subsequently cured in a nitrogen environment at
315 °C for two hours and passivated with a 20 nm thick HfO2 layer grown by plasma-enhanced atomic layer deposition (ALD). The PI substrates offered superior processing compatibility and stability compared to conventional plastics such as polyethylene naphthalate or polyethylene terephthalate and had substantially lower surface roughness (0.3–0.4 nm RMS after ALD passivation, as shown in figure S2) compared to Kapton films or tapes. Devices were subsequently fabricated directly on PI substrates using an eleven mask layer process with standard optical lithography techniques (3 transfers/mesa etches of 2D-layers, 3 via etches and 5 metal depositions). A cross sectional image showing the various layers is shown in figure 1(a), while the steps for graphene/MoS2 contact formation are depicted and described in figures 1(b)–(e). All interlayer dielectrics are based on ALD grown Al2O3 (35 nm gate oxide, 5 nm tunneling oxide) and vias were created by wet etching in dilute tetramethylammonium hydroxide. Prior to ALD deposition on either graphene or MoS2 a 1 nm thick blanket Al film was deposited by e-beam evaporation and allowed to oxidize in air to act as a seed layer for the oxide growth. Both graphene and MoS2 were placed on the target substrate by PMMA-mediated wet transfer which is described in detail for both materials in [17] and [18], respectively. It should be noted that the start of the channel and the metal etch stop layer are separated by 10 μm, which is over an order of magnitude greater than the characteristic transfer length for MoS2 extracted using transmission line measurements and therefore should not impact the access resistance to the MoS2 [19]. High magnification optical micrographs of a top gated FET, a completed contact, a top gated FET with control gates to tune the source/drain contact resistance and an inverter circuit prior to releasing the PI from the carrier wafer are shown in figures 1(f)–(i), respectively. Electrical characterization was carried out both before and after releasing the PI film from the carrier wafer and subsequent flexing of the devices (figure S3). Three primary transistor types are fabricated in this process: back gated, enhancement mode (e-mode) and depletion mode (d-mode) FETs. Back gated devices are locally gated with a patterned Au gate metal and a 40 nm Al2O3 oxide, while e-mode and d-mode devices are top gated with Pd or Al gate metals, respectively, through a 35 nm Al2O3 oxide. Pd and Al gate metals were utilized in order to take advantage of band bending caused by the difference in the semiconductor Fermi level compared to the gate metal work function. A high work function metal (Pd) reduces the number of electrons in the channel, while a low work function (Al) increases the number of electrons in the channel. A detailed discussion of this phenomenon is included in [6]. In our study we investigated at least fifteen devices from each category all of which showed similar behavior. Typical devices were chosen and were characterized in greater detail. The field effect mobility was calculated as a function of back gate bias using the standard expression μFE = dIDS/dVG × [L/ (WCOxVDS)] where IDS, VDS, VG and COx are the source–drain current, source–drain voltage, gate voltage and gate capacitance respectively. The field effect mobility reported here 2
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Nanotechnology 26 (2015) 115202
Figure 1. Cross section showing the various device types fabricated on a single HfO2 passivated PI substrate using graphene both as floating gates for memory and as contacts to MoS2 (a). Illustrations showing the process used to form G/MoS2 heterojunction contacts (b)–(e): a via is etched to expose Au (yellow) (b) and graphene (gray) is transferred and patterned by O2 RIE to form a contact to the routing metals (c), a Ti/ Au layer is then deposited over the via (yellow, marked by dotted line), both serving to reduce the contact resistance of the graphene to the metal and act as an etch stop during the RIE of MoS2 (d). Finally, MoS2 (red) is transferred on top of the graphene and patterned to include a small overlap between the MoS2 and the Au to maintain continuity of the graphene after the MoS2 RIE (e). Pre-release optical micrographs showing a single transistor, scale bar is 50 μm (f) and a high magnification image showing the detailed G/MoS2 junction and vias, scale bar is 20 μm (g), MoS2 transistor with individually gated G/MoS2 contacts, scale bar is 50 μm (h) and an inverter integrated circuit, scale bar is 50 μm (i). Image of a delaminated flexible device set (14 × 14 mm) during a bending cycle (j).
effectively modulated using an applied electric field according to:
does not remove the impact of parasitic resistances originating from both the MoS2/graphene and graphene/metal contacts. Figure 2(a) shows transport measurements taken on a back gated device with a high on/off ratio of 108, maximum field effect mobility of 4.3 cm2 V−1 s−1 and a subthreshold swing of 518 mV/decade. The VDS–IDS characteristics are measured at several gate voltages and are shown in figure 2(b). Linear behavior is observed at low electric fields and, is plotted in greater detail in the insert. This indicates that graphene makes an ohmic contact to monolayer MoS2, consistent with previous reports [14]. Additionally, we observe current saturation at higher values of VDS, which is expected with long channel FETs. From the transport measurements it can be clearly seen that the devices are heavily electron doped. We can calculate the carrier density, ND = COx · VTh/e, where VTh is the threshold voltage and e is the elementary charge. For the back gated devices, the carrier density was found to be 4.6 × 1012 cm−2. The heavy doping is likely due to combined effects from transferring the synthetic MoS2, which has been previously shown to dope the material by 3 × 1012 cm−2 on standard Si/SiO2 substrates and the full encapsulation by the ALD dielectric, which also is known to cause a negative shift in the threshold voltage due to fixed charge present in the oxide [20, 21]. Figure 2(c) shows VGS– IDS curves for both enhancement and depletion mode devices and the field effect mobility as a function of gate voltage for the three device types is shown in figure 2(d). One of the primary advantages of using graphene as a contact material is that its work function (Wg) can be
Wg = E F = −sgn ( n 0 ) ℏν F π n 0 ,
(1)
where EF is the Fermi level, n0 is the carrier concentration of graphene, ħ is Plank’s constant and νF is the Fermi velocity. Work function changes as high as 200 meV have been experimentally observed using low electric fields [22]. In the first demonstration of large area G/MoS2 contacts, Lili et al were able to show that back gate modulation of their devices results in a ∼110 meV shift in the barrier height; however, this was done using a global back gate which simultaneously modulates the carrier density in MoS2 [14]. In our fabrication scheme, we were able to fabricate devices with local back gates directly under the contacts (contact gate, VCG), as shown in figure 1(h) and investigate the effect of work function modulation on the contact resistance of MoS2 directly. Transport measurements taken at various contact gate voltages, shown in figure 3(a), indicate an increase in the device’s on-current as the contact gate voltage is increased. This charge corresponds to a reduction in Wg and is consistent with ref [13]. Additionally, we calculated the field effect mobility without compensating for contact resistance and show that it steadily improved at high contact gate bias as seen in figure 3(b), reaching a maximum value of 16.4 cm2 V−1 s−1. Due to substrate limitations, we are not able to perform temperature dependent measurements to extract barrier heights for these devices. Instead we utilized a modified Y3
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Figure 2. VGS–IDS transport data plotted on a linear and logarithmic scale for a back gated MoS2 transistor (35 nm Al2O3 dielectric, Au gate metal) (a). VDS–IDS output characteristics taken at various gate voltages, insert shows measurements taken at low drain source bias showing that the contacts are ohmic (b). VGS–IDS transport data plotted on a linear and logarithmic scale for enhancement and depletion mode top gated (35 nm Al2O3 dielectric, Pd or Al gate metals for E-mode and D-mode respectively) devices, insert shows the same data plotted on logarithmic scale (c). Field effect mobility as a function of gate voltage for the three device types shown (d).
Figure 3. VGS–IDS transport data plotted at various contact gate values. The insert shows the Y-function calculated for all five VCG values. The average low-field mobility and threshold voltages are extracted from a linear fit to the strong inversion region for all sweeps (a). Log scale transfer characteristics for the same device are shown in figure S4. Field effect mobility plotted for the same devices. The insert shows a schematic band diagram illustrating how the contact resistance is raised/lowered using the contact gate (b).
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function method, which has recently been developed and validated for MoS2 devices, to characterize transistors performance and extract values for contact resistance (Rc). This method is valid even in the presence of a Schottky barrier which is typically observed in metal/MoS2 contacts but is not present in these graphene contact devices [23, 24]. We utilized the simplified model developed and described in detail by Chang et al where we first assume that the contact resistance is not dependent on Vg to extract VT and low-field mobility (μ0) according to equation (2): Y=
IDS = gm
μ 0 Cox VDS W L
( VG − VT ),
(2)
where gm is the channel transconductance. These values are then fit to the effective mobility attenuation factor, θ = θ0 + μ0CoxRcW/L using, ⎛ ⎞ μ0 W ⎟⎟ Cox ( VG − VT ) VDS. IDS = ⎜⎜ L ⎝ 1 + θ ( VG − VT ) ⎠
(3)
The contact resistance of the device can then be found from the θ function when the device is in strong inversion. We also confirm the value of the contact resistance using an empirical technique described for all 2D transistors by Roy et al [25]. The Y-function is calculated at all five contact gate voltages and plotted in the insert of figure 3(a), showing little variation. Furthermore, we can extract an average low-field mobility, which excludes the effect of contact resistance of μ0 = 18.9 ± 1.1 cm2 V−1 s−1 and measure a minimum achievable contact resistance of 322 Ω mm, which is comparable to values obtained on silicon for G/MoS2 junctions (∼100 Ω mm) and significantly lower than typical metal contacts (>1 kΩ mm) to other monolayer material [14, 26, 27]. In figure S5 we show both the values μ0 and μFE as well as the percentage contribution of contact resistance to the total device resistance (which can be modulated from ∼30% to 8%) in the on-state as a function of contact gate voltage. This effect can be easily explained using the qualitative band diagram in figure 3(b), where increasing the Fermi level in graphene reduces the effective barrier height for electron injection into MoS2. One of the key factors that has been suggested in recent manuscripts discussing 2D heterostructures, specifically graphene contacts to MoS2, is the potential for these devices to be used for transparent electronics. However, these manuscripts did not study the sensitivity of their heterojunction devices to visible light [14, 28]. We characterize this behavior by examining the transport data of our devices by performing measurements in the dark, under 470 nm illumination and again in the dark as shown in figure 4(a). An increase in the off state current from 10−8 (dark) to 10−4 (light) μA is observed and the process was found to be reversible. Similar tests performed on devices with back gates (optically exposed MoS2) and metallic contacts showed no measurable photosensitivity, indicating that the G/MoS2 junction induces the
Figure 4. VGS–IDS transport data taken on a transistor sequentially in the dark, under illumination and again in the dark. The insert shows a band diagram of the proposed photocurrent generation mechanism whereby photoexcited carriers are generated in the MoS2 layer and can then be transported to the graphene by either the applied potential or built in electric field of the heterostructure (a). Time dependent photoresponse of the heterostructure showing rapid decay of the persistent photocurrent during an applied gate pulse (b). Response of the photodetector in the dark and under various illumination intensities (c). All illumination was performed using a 470 nm LED and VDS = 0.25 V.
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Figure 5. Output characteristic (a) and gain (b) of an inverter circuit as a function of input voltage taken at a supply/drive voltage of 20 V.
Output voltage for a NAND gate (c) and NOR gate (d) taken at a supply/drive voltage of 20 V for the four possible input voltage combinations (0,0), (0,1), (1,0) and (1,1). Performance of MoS2 non-volatile memory cell with a graphene floating gate, showing the drain current at varying program states with a bipolar pulse train centered at −10 V (Tpulse = 100 ms, VDS = 0.25 V) (e). Transfer characteristics for the non-volatile memory cell showing a large hysteresis window of 18 V, which is caused by the accumulation of charge on the graphene floating gate. The insert shows the log plot (f).
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photoresponse. The response mechanism can be explained using the results of Zhang et al who were able to fabricate a heterojunction photodetector with a photoresponse as high as 108 using an optimized metal-semiconductor-metal structure [29]. In this device, carriers are photoexcited in the MoS2 and are subsequently transported to the graphene layer via an applied electric field. This mechanism is further elucidated by the time dependent measurements shown in figure 4(b), where it can be seen that a persistent photocurrent is still measured in the device, even after the device has been kept in the dark for 200 s. This is caused by carrier localization in the MoS2 which undergoes logarithmic scale relaxation and can be reset by applying an electric field through the gate [30]. We show the response of our sensor to various illumination power in figure 4(c) and calculate a maximum responsively of γ = 33.2 A W−1 at a back gate voltage of −15 V. The responsivity is calculated using γ = (IOn−IOff)/PLED, where IOn and IOff is the current in the device under a particular drain voltage and gate bias with and without illumination, respectively and PLED is the power density of the light source normalized by the active device area. While this value is several orders of magnitude lower than what has been achieved for exfoliated graphene/ MoS2 heterojunction devices which are typically of much higher material quality and were designed using optimized structures, these basic measurements still show a photo response which is significantly higher than monolayer MoS2 devices [29–31]. Based on the transistors described above, we have fabricated several integrated circuits to demonstrate the feasibility of this material system for flexible logic and circuit applications. Devices were processed and integrated in a traditional depletion loaded NMOS regime, which has been previously demonstrated with carbon nanotube and exfoliated MoS2 devices [6, 32]. In figures 5(a) and (b), we show the input–output characteristics as well as the gain of an inverter circuit at a drive voltages of −15 V. Due to the high n-type doping of the MoS2, which can be attributed to the both transfer processes and the high defect density in the CVD grown material, the threshold voltage of the devices is shifted heavily towards negative gate voltages, which requires us to use a negative input voltage to drive the device. As new growth and doping techniques emerge to produce large area MoS2 with simultaneously low defect density and high electronic quality, this issue is likely to be mitigated and better controlled. To further analyze the performance of our inverter, we performed switching measurements at 500 kHz driving an active probe with a 0.9 pF input capacitance as shown in figure S6(a). Compensating for cable delay and averaging over 100 switching cycles, we determined that our devices had an average propagation delay of 85 ± 2.6 ns, which is comparable to values previously measured on exfoliated MoS2 devices with Ti/Au contacts. In addition to an inverter, we also demonstrated a NAND gate and a NOR gate, either of which can be used as the basic building block for more complex logic, using devices with graphene/MoS2 heterojunction contacts as shown in figures 5(c) and (d). These gates were all tested using voltage levels such that the
output would be sufficient to drive the subsequent gates, a key requirement for any digital logic technology. An additional component in electronic systems is nonvolatile data storage. We demonstrated this using a floating gate transistor architecture with graphene as the floating gate. Graphene has previously been shown to be an ideal material for this application, since it can simultaneously act as a smooth, ultra-thin layer while still providing a relatively high density of states for charge storage [33]. For these devices a third layer of graphene was transferred and patterned over a control gate coated with a 35 nm oxide. A thin tunneling oxide (5 nm) was deposited over the floating graphene gate. During operation the control gate can be used to induce tunneling of charge to or from the transistor to the floating gate which shifts the threshold voltage. Switching characteristics for the memory are shown in figure 5(e), being driven by a bipolar pulse train centered at −10 V and applying a +20 V for 100 μs to store a value of ‘1’ and −20 V for 100 μs to store a value of ‘0’. The negative gate bias is required to read data due to the high n-type doping of the MoS2 which results in the transistor being on in both the ‘1’ and ‘0’ states. Transport measurements on these devices are presented in figure 5(f) and show a large switching ratio (∼104) as well as a high operating window of 18 V. Retention measurements were also performed and are shown in figure S5(b). In conclusion, we have implemented a complex, large area 2D system comprising of three separate 2D atomic layers on a flexible platform. We have shown that we can simultaneously implement MoS2 based logic devices, non-volatile memory, photodetectors and transistors with tunable contacts on a single sample. Furthermore, we have shown that our flexible MoS2 FETs with graphene heterojunction ohmic contacts have excellent electronic properties and are comparable to previously reported devices fabricated on conventional substrates and even four terminal measurements on single MoS2 crystals [11, 13, 14, 19, 34]. Since these devices are fabricated using low-cost and highly scalable CVD grown graphene and MoS2 layers, this process can be easily manufactured on much larger scales, overcoming the limitations of standard Si based processing.
Acknowledgments The authors acknowledge the support of the US Army Research Lab (ARL) Director’s Strategic Initiative (DSI) program on interfaces in stacked 2D atomic layered materials. The authors would also like to thank Dr Pani Varanasi of the Army Research Office for his in-depth technical discussion on 2D atomic layers R and D. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the ARL or the US Government. The US Government is authorized to reproduce or distribute reprints for Government purposes notwithstanding any copyright notation herein. 7
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Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2015 Nanotechnology 26 115202 (http://iopscience.iop.org/0957-4484/26/11/115202) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 202.28.191.34 This content was downloaded on 22/03/2015 at 13:50
Please note that terms and conditions apply.
Nanotechnology Nanotechnology 26 (2015) 115202 (8pp)
doi:10.1088/0957-4484/26/11/115202
Flexible integrated circuits and multifunctional electronics based on single atomic layers of MoS2 and graphene Matin Amani1, Robert A Burke, Robert M Proie and Madan Dubey Sensors and Electron Devices Directorate, US Army Research Laboratory, Adelphi MD 20783, USA E-mail: [email protected] Received 2 October 2014, revised 1 December 2014 Accepted for publication 16 December 2014 Published 24 February 2015 Abstract
Two-dimensional materials, such as graphene and its analogues, have been investigated by numerous researchers for high performance flexible and conformal electronic systems, because they offer the ultimate level of thickness scaling, atomically smooth surfaces and high crystalline quality. Here, we use layer-by-layer transfer of large area molybdenum disulphide (MoS2) and graphene grown by chemical vapor deposition (CVD) to demonstrate electronics on flexible polyimide (PI) substrates. On the same PI substrate, we are able to simultaneously fabricate MoS2 based logic, non-volatile memory cells with graphene floating gates, photo-detectors and MoS2 transistors with tunable source and drain contacts. We are also able to demonstrate that these flexible heterostructure devices have very high electronic performance, comparable to four point measurements taken on SiO2 substrates, with on/off ratios >107 and field effect mobilities as high as 16.4 cm2 V−1 s−1. Additionally, the heterojunctions show high optoelectronic sensitivity and were operated as photodetectors with responsivities over 30 A W−1. Through local gating of the individual graphene/MoS2 contacts, we are able to tune the contact resistance over the range of 322–1210 Ω mm for each contact, by modulating the graphene work function. This leads to devices with tunable and multifunctional performance that can be implemented in a conformable platform. S Online supplementary data available from stacks.iop.org/NANO/26/115202/mmedia Keywords: flexible electronics, integrated circuits, MoS2, graphene, heterostructures (Some figures may appear in colour only in the online journal) One of the defining factors for the next generation of electronic devices will be their ability to operate with non-standard packaging, conform to surfaces required for their specific application and have a high degree of ruggedization [1–3]. Additionally, to economically expand into these new markets, high performance electronics that are compatible with low cost fabrication, such as roll-to-roll processing, need to be developed [4]. Electronics fabricated directly on flexible substrates as well as thinned silicon chips are currently the two primary contenders for this application space. Thinned silicon provides superior performance, but relies on
conventional wafer based fabrication. Meanwhile, direct fabrication on flexible materials presents processing limitations for both layer registry and thermal budget, ultimately forcing the use of organic or amorphous channel materials with low mobility and performance. Two dimensional (2D) atomic crystals, which have been under extensive investigation since the isolation of graphene in 2004, are in a unique position to excel in flexible electronics applications due to their extreme thinness and ability to reversibly undergo high strains (as high as 12% for graphene). Additionally, they are ideally suited to either be directly deposited by inkjet printing or to be grown over large areas by chemical vapor deposition (CVD) and subsequently transferred to arbitrary flexible
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Present address: Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA.
0957-4484/15/115202+08$33.00
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© 2015 IOP Publishing Ltd Printed in the UK
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substrates while preserving their electronic performance [5–9]. While much of the initial work in this area focused on graphene, which showed early promise as a device for digital electronics, it’s natural zero band-gap prevented its direct use in the area of low power logic [10]. The recent discovery and investigation of new 2D materials with semiconducting, insulating and metallic properties has resulted in several materials that hold promise to fulfill the electronic and optoelectronic roles previously not accessible with graphene. One of these materials, single layer thick molybdenum disulphide (MoS2), is being studied as a direct band gap semiconductor by numerous researchers. Several groups have demonstrated novel device structures and validated that MoS2 possesses qualities required for device scaling in next generation electronic systems [6, 11]. One of the key limiting factors in MoS2 devices is a prohibitively large contact resistance and Fermi level pinning observed for traditional metal/semiconductor junctions [12]. Limited improvements to this parasitic resistance have been made through the use of very low work function metals and vacuum annealing; the most significant milestone to date, however, has been the use of 2D graphene contacts [13, 14]. These heterojunctions have not only been shown to dramatically reduce the access resistance to MoS2 and enable Schottky barrier height tuning using graphene’s carrier density dependent work function, but they are also ideal for flexible devices since the most common point of failure in these systems are metal contacts [15]. We show for the first time in this letter that MoS2 transistors with graphene contacts, integrated circuits, non-volatile memory and photodetectors based on all CVD grown monolayer material can be integrated on a single flexible substrate while still maintaining similar electronic quality to equivalent structures fabricated on traditional substrates. In fact, the performance of our monolayer MoS2 devices represents one of the highest values obtained at room temperature, without excluding the contribution of contact resistance, on both flexible and non-flexible substrates. Continuous films of single layer MoS2 were grown on Si/ SiO2 by atmospheric pressure CVD in a hot-wall tube furnace at a substrate temperature of 700 °C using MoO3 and sulfur powders as the reactants. The substrates were cleaned with piranha solution, acetone, IPA and DI water and treated in an O2 plasma to make them hydrophilic prior to application of PTAS (perylene-3,4,9,10-tetracarboxylic acid tetrapotassium salt), which has been shown to promote the growth of monolayer MoS2 by serving as a nucleation site [16]. After growth, the presence of high quality material was confirmed by Raman and PL mapping as shown in figure S1 and discussed in the supplementary materials. Graphene was grown by low pressure chemical vapor deposition on copper foils at 1000 °C using well established techniques [4, 17]. Detailed information about the growth process is included in the supplementary information. Atomically smooth, 16 μm thick polyimide (PI) films were deposited using multiple spincoats of PI-2611 (HDMicrosystems) on pre-diced Si/SiO2 substrates. The PI samples were subsequently cured in a nitrogen environment at
315 °C for two hours and passivated with a 20 nm thick HfO2 layer grown by plasma-enhanced atomic layer deposition (ALD). The PI substrates offered superior processing compatibility and stability compared to conventional plastics such as polyethylene naphthalate or polyethylene terephthalate and had substantially lower surface roughness (0.3–0.4 nm RMS after ALD passivation, as shown in figure S2) compared to Kapton films or tapes. Devices were subsequently fabricated directly on PI substrates using an eleven mask layer process with standard optical lithography techniques (3 transfers/mesa etches of 2D-layers, 3 via etches and 5 metal depositions). A cross sectional image showing the various layers is shown in figure 1(a), while the steps for graphene/MoS2 contact formation are depicted and described in figures 1(b)–(e). All interlayer dielectrics are based on ALD grown Al2O3 (35 nm gate oxide, 5 nm tunneling oxide) and vias were created by wet etching in dilute tetramethylammonium hydroxide. Prior to ALD deposition on either graphene or MoS2 a 1 nm thick blanket Al film was deposited by e-beam evaporation and allowed to oxidize in air to act as a seed layer for the oxide growth. Both graphene and MoS2 were placed on the target substrate by PMMA-mediated wet transfer which is described in detail for both materials in [17] and [18], respectively. It should be noted that the start of the channel and the metal etch stop layer are separated by 10 μm, which is over an order of magnitude greater than the characteristic transfer length for MoS2 extracted using transmission line measurements and therefore should not impact the access resistance to the MoS2 [19]. High magnification optical micrographs of a top gated FET, a completed contact, a top gated FET with control gates to tune the source/drain contact resistance and an inverter circuit prior to releasing the PI from the carrier wafer are shown in figures 1(f)–(i), respectively. Electrical characterization was carried out both before and after releasing the PI film from the carrier wafer and subsequent flexing of the devices (figure S3). Three primary transistor types are fabricated in this process: back gated, enhancement mode (e-mode) and depletion mode (d-mode) FETs. Back gated devices are locally gated with a patterned Au gate metal and a 40 nm Al2O3 oxide, while e-mode and d-mode devices are top gated with Pd or Al gate metals, respectively, through a 35 nm Al2O3 oxide. Pd and Al gate metals were utilized in order to take advantage of band bending caused by the difference in the semiconductor Fermi level compared to the gate metal work function. A high work function metal (Pd) reduces the number of electrons in the channel, while a low work function (Al) increases the number of electrons in the channel. A detailed discussion of this phenomenon is included in [6]. In our study we investigated at least fifteen devices from each category all of which showed similar behavior. Typical devices were chosen and were characterized in greater detail. The field effect mobility was calculated as a function of back gate bias using the standard expression μFE = dIDS/dVG × [L/ (WCOxVDS)] where IDS, VDS, VG and COx are the source–drain current, source–drain voltage, gate voltage and gate capacitance respectively. The field effect mobility reported here 2
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Figure 1. Cross section showing the various device types fabricated on a single HfO2 passivated PI substrate using graphene both as floating gates for memory and as contacts to MoS2 (a). Illustrations showing the process used to form G/MoS2 heterojunction contacts (b)–(e): a via is etched to expose Au (yellow) (b) and graphene (gray) is transferred and patterned by O2 RIE to form a contact to the routing metals (c), a Ti/ Au layer is then deposited over the via (yellow, marked by dotted line), both serving to reduce the contact resistance of the graphene to the metal and act as an etch stop during the RIE of MoS2 (d). Finally, MoS2 (red) is transferred on top of the graphene and patterned to include a small overlap between the MoS2 and the Au to maintain continuity of the graphene after the MoS2 RIE (e). Pre-release optical micrographs showing a single transistor, scale bar is 50 μm (f) and a high magnification image showing the detailed G/MoS2 junction and vias, scale bar is 20 μm (g), MoS2 transistor with individually gated G/MoS2 contacts, scale bar is 50 μm (h) and an inverter integrated circuit, scale bar is 50 μm (i). Image of a delaminated flexible device set (14 × 14 mm) during a bending cycle (j).
effectively modulated using an applied electric field according to:
does not remove the impact of parasitic resistances originating from both the MoS2/graphene and graphene/metal contacts. Figure 2(a) shows transport measurements taken on a back gated device with a high on/off ratio of 108, maximum field effect mobility of 4.3 cm2 V−1 s−1 and a subthreshold swing of 518 mV/decade. The VDS–IDS characteristics are measured at several gate voltages and are shown in figure 2(b). Linear behavior is observed at low electric fields and, is plotted in greater detail in the insert. This indicates that graphene makes an ohmic contact to monolayer MoS2, consistent with previous reports [14]. Additionally, we observe current saturation at higher values of VDS, which is expected with long channel FETs. From the transport measurements it can be clearly seen that the devices are heavily electron doped. We can calculate the carrier density, ND = COx · VTh/e, where VTh is the threshold voltage and e is the elementary charge. For the back gated devices, the carrier density was found to be 4.6 × 1012 cm−2. The heavy doping is likely due to combined effects from transferring the synthetic MoS2, which has been previously shown to dope the material by 3 × 1012 cm−2 on standard Si/SiO2 substrates and the full encapsulation by the ALD dielectric, which also is known to cause a negative shift in the threshold voltage due to fixed charge present in the oxide [20, 21]. Figure 2(c) shows VGS– IDS curves for both enhancement and depletion mode devices and the field effect mobility as a function of gate voltage for the three device types is shown in figure 2(d). One of the primary advantages of using graphene as a contact material is that its work function (Wg) can be
Wg = E F = −sgn ( n 0 ) ℏν F π n 0 ,
(1)
where EF is the Fermi level, n0 is the carrier concentration of graphene, ħ is Plank’s constant and νF is the Fermi velocity. Work function changes as high as 200 meV have been experimentally observed using low electric fields [22]. In the first demonstration of large area G/MoS2 contacts, Lili et al were able to show that back gate modulation of their devices results in a ∼110 meV shift in the barrier height; however, this was done using a global back gate which simultaneously modulates the carrier density in MoS2 [14]. In our fabrication scheme, we were able to fabricate devices with local back gates directly under the contacts (contact gate, VCG), as shown in figure 1(h) and investigate the effect of work function modulation on the contact resistance of MoS2 directly. Transport measurements taken at various contact gate voltages, shown in figure 3(a), indicate an increase in the device’s on-current as the contact gate voltage is increased. This charge corresponds to a reduction in Wg and is consistent with ref [13]. Additionally, we calculated the field effect mobility without compensating for contact resistance and show that it steadily improved at high contact gate bias as seen in figure 3(b), reaching a maximum value of 16.4 cm2 V−1 s−1. Due to substrate limitations, we are not able to perform temperature dependent measurements to extract barrier heights for these devices. Instead we utilized a modified Y3
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Figure 2. VGS–IDS transport data plotted on a linear and logarithmic scale for a back gated MoS2 transistor (35 nm Al2O3 dielectric, Au gate metal) (a). VDS–IDS output characteristics taken at various gate voltages, insert shows measurements taken at low drain source bias showing that the contacts are ohmic (b). VGS–IDS transport data plotted on a linear and logarithmic scale for enhancement and depletion mode top gated (35 nm Al2O3 dielectric, Pd or Al gate metals for E-mode and D-mode respectively) devices, insert shows the same data plotted on logarithmic scale (c). Field effect mobility as a function of gate voltage for the three device types shown (d).
Figure 3. VGS–IDS transport data plotted at various contact gate values. The insert shows the Y-function calculated for all five VCG values. The average low-field mobility and threshold voltages are extracted from a linear fit to the strong inversion region for all sweeps (a). Log scale transfer characteristics for the same device are shown in figure S4. Field effect mobility plotted for the same devices. The insert shows a schematic band diagram illustrating how the contact resistance is raised/lowered using the contact gate (b).
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function method, which has recently been developed and validated for MoS2 devices, to characterize transistors performance and extract values for contact resistance (Rc). This method is valid even in the presence of a Schottky barrier which is typically observed in metal/MoS2 contacts but is not present in these graphene contact devices [23, 24]. We utilized the simplified model developed and described in detail by Chang et al where we first assume that the contact resistance is not dependent on Vg to extract VT and low-field mobility (μ0) according to equation (2): Y=
IDS = gm
μ 0 Cox VDS W L
( VG − VT ),
(2)
where gm is the channel transconductance. These values are then fit to the effective mobility attenuation factor, θ = θ0 + μ0CoxRcW/L using, ⎛ ⎞ μ0 W ⎟⎟ Cox ( VG − VT ) VDS. IDS = ⎜⎜ L ⎝ 1 + θ ( VG − VT ) ⎠
(3)
The contact resistance of the device can then be found from the θ function when the device is in strong inversion. We also confirm the value of the contact resistance using an empirical technique described for all 2D transistors by Roy et al [25]. The Y-function is calculated at all five contact gate voltages and plotted in the insert of figure 3(a), showing little variation. Furthermore, we can extract an average low-field mobility, which excludes the effect of contact resistance of μ0 = 18.9 ± 1.1 cm2 V−1 s−1 and measure a minimum achievable contact resistance of 322 Ω mm, which is comparable to values obtained on silicon for G/MoS2 junctions (∼100 Ω mm) and significantly lower than typical metal contacts (>1 kΩ mm) to other monolayer material [14, 26, 27]. In figure S5 we show both the values μ0 and μFE as well as the percentage contribution of contact resistance to the total device resistance (which can be modulated from ∼30% to 8%) in the on-state as a function of contact gate voltage. This effect can be easily explained using the qualitative band diagram in figure 3(b), where increasing the Fermi level in graphene reduces the effective barrier height for electron injection into MoS2. One of the key factors that has been suggested in recent manuscripts discussing 2D heterostructures, specifically graphene contacts to MoS2, is the potential for these devices to be used for transparent electronics. However, these manuscripts did not study the sensitivity of their heterojunction devices to visible light [14, 28]. We characterize this behavior by examining the transport data of our devices by performing measurements in the dark, under 470 nm illumination and again in the dark as shown in figure 4(a). An increase in the off state current from 10−8 (dark) to 10−4 (light) μA is observed and the process was found to be reversible. Similar tests performed on devices with back gates (optically exposed MoS2) and metallic contacts showed no measurable photosensitivity, indicating that the G/MoS2 junction induces the
Figure 4. VGS–IDS transport data taken on a transistor sequentially in the dark, under illumination and again in the dark. The insert shows a band diagram of the proposed photocurrent generation mechanism whereby photoexcited carriers are generated in the MoS2 layer and can then be transported to the graphene by either the applied potential or built in electric field of the heterostructure (a). Time dependent photoresponse of the heterostructure showing rapid decay of the persistent photocurrent during an applied gate pulse (b). Response of the photodetector in the dark and under various illumination intensities (c). All illumination was performed using a 470 nm LED and VDS = 0.25 V.
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Figure 5. Output characteristic (a) and gain (b) of an inverter circuit as a function of input voltage taken at a supply/drive voltage of 20 V.
Output voltage for a NAND gate (c) and NOR gate (d) taken at a supply/drive voltage of 20 V for the four possible input voltage combinations (0,0), (0,1), (1,0) and (1,1). Performance of MoS2 non-volatile memory cell with a graphene floating gate, showing the drain current at varying program states with a bipolar pulse train centered at −10 V (Tpulse = 100 ms, VDS = 0.25 V) (e). Transfer characteristics for the non-volatile memory cell showing a large hysteresis window of 18 V, which is caused by the accumulation of charge on the graphene floating gate. The insert shows the log plot (f).
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photoresponse. The response mechanism can be explained using the results of Zhang et al who were able to fabricate a heterojunction photodetector with a photoresponse as high as 108 using an optimized metal-semiconductor-metal structure [29]. In this device, carriers are photoexcited in the MoS2 and are subsequently transported to the graphene layer via an applied electric field. This mechanism is further elucidated by the time dependent measurements shown in figure 4(b), where it can be seen that a persistent photocurrent is still measured in the device, even after the device has been kept in the dark for 200 s. This is caused by carrier localization in the MoS2 which undergoes logarithmic scale relaxation and can be reset by applying an electric field through the gate [30]. We show the response of our sensor to various illumination power in figure 4(c) and calculate a maximum responsively of γ = 33.2 A W−1 at a back gate voltage of −15 V. The responsivity is calculated using γ = (IOn−IOff)/PLED, where IOn and IOff is the current in the device under a particular drain voltage and gate bias with and without illumination, respectively and PLED is the power density of the light source normalized by the active device area. While this value is several orders of magnitude lower than what has been achieved for exfoliated graphene/ MoS2 heterojunction devices which are typically of much higher material quality and were designed using optimized structures, these basic measurements still show a photo response which is significantly higher than monolayer MoS2 devices [29–31]. Based on the transistors described above, we have fabricated several integrated circuits to demonstrate the feasibility of this material system for flexible logic and circuit applications. Devices were processed and integrated in a traditional depletion loaded NMOS regime, which has been previously demonstrated with carbon nanotube and exfoliated MoS2 devices [6, 32]. In figures 5(a) and (b), we show the input–output characteristics as well as the gain of an inverter circuit at a drive voltages of −15 V. Due to the high n-type doping of the MoS2, which can be attributed to the both transfer processes and the high defect density in the CVD grown material, the threshold voltage of the devices is shifted heavily towards negative gate voltages, which requires us to use a negative input voltage to drive the device. As new growth and doping techniques emerge to produce large area MoS2 with simultaneously low defect density and high electronic quality, this issue is likely to be mitigated and better controlled. To further analyze the performance of our inverter, we performed switching measurements at 500 kHz driving an active probe with a 0.9 pF input capacitance as shown in figure S6(a). Compensating for cable delay and averaging over 100 switching cycles, we determined that our devices had an average propagation delay of 85 ± 2.6 ns, which is comparable to values previously measured on exfoliated MoS2 devices with Ti/Au contacts. In addition to an inverter, we also demonstrated a NAND gate and a NOR gate, either of which can be used as the basic building block for more complex logic, using devices with graphene/MoS2 heterojunction contacts as shown in figures 5(c) and (d). These gates were all tested using voltage levels such that the
output would be sufficient to drive the subsequent gates, a key requirement for any digital logic technology. An additional component in electronic systems is nonvolatile data storage. We demonstrated this using a floating gate transistor architecture with graphene as the floating gate. Graphene has previously been shown to be an ideal material for this application, since it can simultaneously act as a smooth, ultra-thin layer while still providing a relatively high density of states for charge storage [33]. For these devices a third layer of graphene was transferred and patterned over a control gate coated with a 35 nm oxide. A thin tunneling oxide (5 nm) was deposited over the floating graphene gate. During operation the control gate can be used to induce tunneling of charge to or from the transistor to the floating gate which shifts the threshold voltage. Switching characteristics for the memory are shown in figure 5(e), being driven by a bipolar pulse train centered at −10 V and applying a +20 V for 100 μs to store a value of ‘1’ and −20 V for 100 μs to store a value of ‘0’. The negative gate bias is required to read data due to the high n-type doping of the MoS2 which results in the transistor being on in both the ‘1’ and ‘0’ states. Transport measurements on these devices are presented in figure 5(f) and show a large switching ratio (∼104) as well as a high operating window of 18 V. Retention measurements were also performed and are shown in figure S5(b). In conclusion, we have implemented a complex, large area 2D system comprising of three separate 2D atomic layers on a flexible platform. We have shown that we can simultaneously implement MoS2 based logic devices, non-volatile memory, photodetectors and transistors with tunable contacts on a single sample. Furthermore, we have shown that our flexible MoS2 FETs with graphene heterojunction ohmic contacts have excellent electronic properties and are comparable to previously reported devices fabricated on conventional substrates and even four terminal measurements on single MoS2 crystals [11, 13, 14, 19, 34]. Since these devices are fabricated using low-cost and highly scalable CVD grown graphene and MoS2 layers, this process can be easily manufactured on much larger scales, overcoming the limitations of standard Si based processing.
Acknowledgments The authors acknowledge the support of the US Army Research Lab (ARL) Director’s Strategic Initiative (DSI) program on interfaces in stacked 2D atomic layered materials. The authors would also like to thank Dr Pani Varanasi of the Army Research Office for his in-depth technical discussion on 2D atomic layers R and D. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the ARL or the US Government. The US Government is authorized to reproduce or distribute reprints for Government purposes notwithstanding any copyright notation herein. 7
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