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Exploration of yttria films as gate dielectrics in sub50 nm carbon nanotube field-effect transistors† Li Ding,a Zhiyong Zhang,*a Jun Su,b Qunqing Lic and Lian-Mao Peng*a Thin yttria films were investigated for use as gate dielectrics in carbon nanotube field-effect transistors (CNTFETs) with the gate length scaled down to sub-50 nm size. The yttria film provided an omegashaped gate dielectric with a low interface trap density, a low average sub-threshold swing of 74 mV per decade for both long and short CNTFETs, and a small drain-induced barrier lowering. It was also shown
Received 22nd June 2014 Accepted 25th July 2014
that the performance of CNTFETs increases with decreasing temperature, with an excellent subthreshold swing of 22 mV per decade at liquid nitrogen temperatures. A method was developed to
DOI: 10.1039/c4nr03475a
retrieve the interface trap density in CNTFETs and a low interface trap density of 5.2 106 cm1 was
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achieved, indicating the high electric quality of the yttria films.
Introduction Field-effect transistors (FETs), devices that use an electric eld to control the conductivity of a semiconductor channel, are the most important and widely used electrical devices in modern integrated circuits (ICs). A high-performance FET must have all of the following properties: excellent semiconducting channel materials; ideal ohmic source–drain contacts; and a highquality gate dielectric. As the FET devices most oen used, i.e. silicon-based metal oxide semiconductors, were developed almost 50 years ago, they are expected to reach their limit, both scientically and technologically, in the near future based on the predictions of Moore's law.1,2 Carbon nanotubes (CNTs) are considered to be one of the most promising candidate materials to replace silicon as the channel material in the next generation high-performance FETs, mainly owing to their unique structural, mechanical, chemical and, in particular, electrical properties, including an ultra-thin body, high carrier mobility and high saturation velocity.3–6 Since the rst FETs based on CNTs were developed in 1998,7 great advances have been made in developing high-performance CNTFETs, circuits and systems.4–11 In particular, ideal ohmic contacts have been realized in CNTFETs through adopting Sc12 and Y13 for n-type and Pd4 for p-type contacts, leading to a contact resistance that approaches the quantum
a
Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing, 100871, P. R. China. E-mail: zyzhang@pku. edu.cn; [email protected]
b
Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, 430074, P. R. China
c Department of Physics and Tsinghua-Foxconn Nanotechnology Research Center, Tsinghua University, Beijing, 100084, P. R. China
† Electronic supplementary 10.1039/c4nr03475a
information
11316 | Nanoscale, 2014, 6, 11316–11321
(ESI)
available.
See
DOI:
limit. Moreover high-k dielectrics such as HfO2, ZrO2 and Al2O3 have been explored for use as gate dielectrics to enhance the gate efficiency of CNTFETs. High values of trans-conductance and low sub-threshold swing (SS) have been achieved in both nand p-type FETs for relatively long gate length (>100 nm) devices.14–20 However, these conventional high-k dielectrics are not suitable for providing the highest gate efficiency in CNTs. Experimentally, almost all top-gated CNTFETs with a short gate length (80 mV per decade21–23 The SS is important because it is the key parameter for describing the turn-off speed of an FET. In general, the smaller the SS, the smaller the off-state current at a xed supply voltage and therefore the power dissipation is reduced. CNT-based FETs have now been scaled down to sub-10 nm in size and have shown a much better on-state current than silicon metal oxide semiconductor FETs, with little degradation of the SS. However, these sub-10 nm CNTFETs were fabricated using a back-gate device geometry,24,25 which avoids the difficult task of growing ultra-thin high-k top-gate dielectrics. To fabricate high-performance top-gate CNTFETs that are more suitable for constructing large-scale ICs, an ultra-thin dielectric layer needs to be fabricated on the CNT to ensure efficient gate control on the channel. However, dielectric layers thinner than 8 nm cannot be readily grown on CNTs using conventional methods, such as atomic layer deposition.26 This is because the usual high-k dielectric layer cannot nucleate on a perfect CNT without defects and therefore thick dielectric layers are usually grown from an SiO2 substrate to bury the CNTs. It is highly desirable to have an ultra-thin, high-quality gate dielectric to provide the efficient control required for small CNTFETs with a gate length 12 mA and gm increases to 17 mS at Vds ¼ 0.5 V (Fig. 1d). The increase in saturation current and trans-conductance is a direct consequence of scaling down the transistor. Furthermore, the on-state performance of the CNTFET can be further improved if a self-aligned gate structure is used to fabricate the short gate FETs. We now consider further the electrical characterization of the Y2O3 gate dielectric in CNTFETs, including the leakage current and hysteresis. Less than 10 pA leakage current and 80 mV hysteresis were typically found for these CNTFETs (Fig. S2 and S3†). It is thus concluded that, by adopting a Y2O lm as the gate dielectric in CNTFETs, we can take full advantage of the scaling of the dimensions of the device with few short channel effects, such as degradation of the SS and an increased DIBL. An ideal gate dielectric should enable a consistent yield with a low SS in the device,27 which, in turn, reects the quality and uniformity of the dielectric layer and the interface between the dielectric layer and the CNT. To test this consistency, we fabricated and measured numerous CNTFETs, including 10 devices with a short gate length and 19 devices with a long gate length. The transfer characteristics of these short and long gate length CNTFETs are plotted in Fig. 1e and f, respectively. Although the 19 long gate devices were fabricated using different CNTs on different regions of the silicon wafer, the results show little variation in the SS (from 62 to 82 mV per decade). The average SS value is as low as 74 mV per decade, which is nearly equal to that of the best back-gate CNTFETs with lanthanum oxide as the gate dielectric.27 The variation in threshold voltage (Vt) is about 0.38 V as a result of the uctuations in the CNT diameter and the environment of different CNTFETs on the silicon wafer. For the 10 short channel devices with a gate length of about 50 nm, the SS varies from 64 to 88 mV per decade and the average SS value is 74 mV per decade. Statistical analysis showed no SS
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degradation as the gate length decreased from 1.5 mm to 50 nm, i.e. these devices are hardly affected by short channel effects down to the sub-50 nm scale. Compared with the results for long channel devices, the variation in Vt is around 0.5 V for the short gate length devices, which is a little larger (about 120 mV) than that of the long gate length devices. By denition, low SS means a low off-state current for a given bias. The off-state current is an important parameter for an FET in the design of low power circuits and it determines the static power dissipation of the IC.30 Ideally, an FET should have a low off-state current and thus a low static power dissipation, and a high on-state current for high speed and driving ability. To evaluate our CNTFETs, two typical CNTFETs (with long and short gate lengths, respectively) were examined at Vds ¼ 0.5 V. The transfer characteristics of the two devices are shown in Fig. 2a, in which the long gate device with Lg ¼ 1.5 mm shows an SS of 65 mV per decade, whereas the short gate device with Lg ¼ 56 nm shows an SS of 75 mV per decade. From these transfer characteristics, the on- and off-state currents may be extracted using a standard method,31 as shown in Fig. 2b. A blue box with a width Vds ¼ 0.5 V is rst dened around the threshold voltage of the device Vth extending from 1/3Vds as the lower voltage to 2/3Vds as the higher voltage. This box intercepts the transfer characteristics (which are aligned with Vth) and the le and right intercepts are Ioff and Ion, respectively. The Ioff/Ion ratio is 1.8 mA/4.7 nA (383) for the long device and 7.6 mA/14 nA (543) for the short device. This increased current on/off ratio is a direct consequence of the more rapidly increased on-state current than off-state current for this short CNTFET, given the condition that the SS of the device is not signicantly decreased. To obtain a statistical analysis, the on- and off-state currents for 10 short gate devices are presented in Fig. 2c and the on- and off-state currents for 16 long gate devices in Fig. 2d. For long
Paper
gate devices, Ion varies from 0.4 to 3.5 mA and Ioff varies from 0.6 to 55 nA. For short gate devices, Ion varies from 2.9 to 8.0 mA and Ioff varies from 14 to 314 nA. Although Ioff increases in short gate devices compared with long gate devices, the current on/off ratio remains around several hundred, which is similar to that of long gate devices (Fig. S4†). As a benet of the scaling of the FET, the distribution of the Ion values of short devices is obviously narrower than that of long gate devices as the sub-50 nm devices begin to be dominated by ballistic transport and to be immune to the effects of channel scattering. To compare the performance of the CNTFETs with Y2O3 as the gate dielectric with silicon metal oxide semiconductor FETs and CNTFETs fabricated using other gate dielectrics with comparable gate lengths, two key popular metrics were used, i.e. the SS and intrinsic gate delay, to benchmark the switching-off and turning-on properties of our short gate CNTFETs. Fig. 3 shows the SS values of various short channel FETs with Lg < 120 nm. For a gate length of about 100 nm, the CNTFETs with Y2O3 as the gate dielectric show a similar SS to the planar silicon FETs. As gate length scales down to 50 nm, the SS of planar Si FETs is degraded to beyond 80 mV per decade as a result of the short channel effects, while the SS of our CNTFETs does not increase signicantly. Signicantly, the SS of our CNTFETs is as good as (or even better than) that of the conventional semiconductor-based FETs with well-designed gates such as the Fingate, Tri-gate and gate-all-around, and we attribute this excellent performance to the combination of the ultra-thin body of the CNTs and the high gate efficiency of the high-quality Y2O3 gate dielectric used in this work. Compared with other
Performance comparison between CNT FETs and silicon devices. The data for the silicon devices is taken from Chau et al.31 and F-BG, F-TG, J 2013 and J 2004 are taken from ref. 21, 22, 23 and 25, respectively; and Zhang is taken from ref. 16 and 32. (a) SS and (b) intrinsic gate delay versus gate length. (c) Typical cross-sectional TEM image showing a CNT device with Y2O3 as the gate dielectric. Scale bar denotes 10 nm. Inset in top corner is an enlarged region of Y2O3 marked by the white square in the image. (d) Atomic ratio of Y to O extracted from XPS results measured at three different depths (0, 2 and 6 nm) from the Y2O3 a film surface. Fig. 3
On- and off-state current extraction for CNTFETs with Y2O3 gate dielectric. (a) Transfer characteristics of typical long gate and typical short gate CNTFETs at Vds ¼ 0.5 V. (b) On- and off-state current extraction. (c) On- and off-state current data extracted from 10 short gate devices of Fig. 1e. (d) On- and off-state current data extracted from 16 long gate devices of Fig. 1f. Fig. 2
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published sub-50 nm CNTFETS,21–23 our devices obviously show a lower SS as a result of the greater gate control ability of the Y2O3 dielectric layer and the lower trap density at the Y2O3–CNT interface. It is obvious from Fig. 3a that almost all the FETs show a degradation in SS as the gate length is scaled down to the sub-100 nm level, whereas our CNTFETs with Y2O3 the as gate dielectric show no visible tendency of SS degradation down to 45 nm. The intrinsic gate delay of our CNTFETs was calculated using the method of Chau et al.,31 which was also used in earlier work.13,15,16,32 The results are plotted in Fig. 3b, together with those for previously reported n-type FETs.16,32 The gate delay values of our CNTFETs are systematically smaller than those of silicon n-FETs with the same gate length. The use of Y2O3 allows the gate delay of n-type CNTFETs to be scaled down with gate length according to the scaling track of our previous work.16,32 The best gate delay of n-type CNTFETs is further decreased to 0.41 ps in one device with a gate length of about 45 nm. The excellent gate delay of our n-type CNTFETs results from the use of the excellent n-type ohmic contact, the high-quality Y2O3 gate dielectric, the nature of the quasi-ballistic transport in short channel CNTFETs and the very high Fermi velocity of CNTs.3 The transmission electron microscopy (TEM) image in Fig. 3c shows a cross-section of the gate stack used in our devices. The CNT is seen to have been fully covered by a thin Y2O3 lm, which forms an excellent omega-shaped gate stack around the CNT. Platinum metal was deposited above the Y2O3 to protect the device from being damaged during focused ion beam cutting of the device to prepare an electron beam transparent sample for TEM examination. Two important observations may be made from the TEM image, which may have remarkable inuences on the performance of the device. First, the yttria layer wets very well with the CNT, which results from the excellent wetting behavior of the metal Y and the CNT. As a direct result, the yttria layer uniformly wraps around the CNT to form a perfect omega-shaped gate, which may yield excellent electrostatic gate control on the CNT channel and a high gate efficiency.33 Second, the yttria layer clearly has a continuous polycrystalline structure in which no large defects such as pinholes are observed. The high crystallinity indicates that the structural quality of the yttria lm is high; this is further conrmed by the XPS results shown in Fig. 3d. The Y : O element ratios at various depths in the yttria lm were extracted from the XPS results (Fig. S5†). The Y : O ratio is 0.667 for an ideal yttria lm, which is almost true for most of the 6 nm thick lm, except at the interface with the SiO2 substrate where some intermixing may have occurred, leading to a slightly higher O to Y ratio at the interface. An excellent gate dielectric for an FET not only leads to a large gate capacitance and small leakage current, but also a low interface trap density. The interface traps may result in hysteresis in the transfer characteristic of the FET and induce SS degradation. Therefore the interface trap density is an important parameter for characterising the gate dielectric and should be reliably retrieved from experimental results. For an FET, the SS is given by.
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SS ¼
dVg kT ¼ m$lnð10Þ$ ; q dðlog Ids Þ
(1)
where k is the Boltzmann constant, T is the temperature, q is the charge of an electron and m is usually referred to as an ideality factor.2,34 According to eqn (1), the SS of a device is proportional to temperature T, meaning that the CNTFETs show a better switching-off behavior at low temperatures. Measurements were thus conducted at various temperatures on a typical short gate CNTFET with Lg ¼ 50 nm and the results are presented in Fig. 4. Fig. 4a shows the transfer characteristics of the device measured at room temperature (300 K) and at liquid nitrogen temperature (77 K) at Vds ¼ 0.1 V. It is obvious that the transistor shows a much better performance at lower temperatures, i.e. a larger onstate current and a lower off-state current. In particular, SS is reduced from 80 mV per decade at 300 K to 24 mV per decade at 77 K. The increased on-state current at lower temperatures is mainly a result of the freezing of phonon scatterings, whereas the perfect linear Ids–Vds relation at low bias in Fig. 4b shows that the perfect ohmic contact to the CNT used in the device is retained at temperatures as low as 77 K. As shown in Fig. 4c, the interface traps in a CNTFET are usually located at the interface between the CNT and the gate dielectric layer. The interface trap states usually lie within the CNT band gap and may quickly exchange charges with the CNT.2,34 In addition to interface trap charges, xed oxide charges, ionic mobile charges and oxide trap charges may also exist and are located near the interface or inside the oxide layer. In principle, all the different types of charge near the CNT channel could affect the device performance, e.g. the SS, but the interface trap charges near the interface dominate because the electrostatic interaction decays rapidly with distance. To a good approximation, the factor m in eqn (1) may be expressed as:15,17–20,27
Fig. 4 Low temperature measurements of CNTFETs with Y2O3 as the gate dielectric layer. (a) Transfer characteristics of one device measured at room temperature (black line) and 77 K (red line) at Vds ¼ 0.1 V. (b) Output characteristics of the device in (a) measured at 77 K. (c) Schematic diagram showing interface traps in top-gated CNTFETs. (d) Experimental and fitted SS values from room temperature to 77 K.
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Nanoscale Table 1
Comparison of some typical gate dielectrics used in CNTFETs
Martel et al.17 Kumar et al.20 Franklin et al.27 This work
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Paper
Oxide
Process
3r
m
Cox (pF cm1)
Cit (pF cm1)
Nit (1 106 cm1) @ 1 V
SiO2 SiO2 Lanthanum oxide Y2O3
Thermal oxidation Thermal oxidation MBE/CBE Thermal oxidation
3.9 3.9 27 10
12.2 16 1.22 1.39
N/A 0.18 6.2 2.16
N/A 2.72 1.35 0.84
N/A 18 8.4 5.2
m¼1þ
Cit ; Cox
(2)
where Cox represents the oxide capacitance and Cit represents the capacitance due to the interface traps. In a CNTFET, the oxide dielectric capacitance Cox can be calculated as 2.16 pF mm1 using the relation Cox ¼ 2p3r30/ln(2tox/r),
(3)
where 3r is the relative dielectric constant of Y2O3 (about 10),29 tox is the thickness of the Y2O3 layer (about 6 nm) and the radius of the CNT r is about 1 nm. Cit may be readily extracted from the SS values of the device measured at different temperatures once the oxide capacitance Cox is known accurately. Indeed, several groups have obtained the interface trap density using this direct method.17,20,27 However, this direct method assumes that the SS value is 0 mV per decade at 0 K, which is not true for real devices. This is because measurement errors and the precision limit induced by instruments and wiring may result in a deviation of the actual SS value from its ideal value. We note that this systematic deviation is not dependent on the sample temperature as all measurement instruments are kept at room temperature. To account for this systematic error, we propose here an improved method to obtain the interface trap density through tting the temperature-dependent SS values. A representative CNTFET value was measured at 77, 170 and 290 K and the temperature dependent SS of the CNTFET is plotted in Fig. 4d, which shows a good linear dependence on temperature. The tted slope of the SS–T data set is 0.27 0.031, which is, in turn, used to retrieve the ideality factor of eqn (1) to yield m ¼ 1.39 and Cit ¼ 0.39 Cox ¼ 0.84 pF mm1. The capacitance associated with the interface trap states is dened as the interface trap charges divided by the surface potential, i.e. Cit ¼ Qit/4s, where the surface potential 4s is the potential applied by the gate voltage at the interface between the CNT and Y2O3. The interface trap charge Qit is dened as Qit ¼ qNit with Nit being the interface trap density. We may thus obtain the interface trap density from the interface trap capacitance to obtain Nit ¼ 5.2 106 cm1 at 4s ¼ 1 V. This and other relevant quantities are summarized in Table 1 and compared with the results of three other research groups. It is worth mentioning that the interface trap density found in our transistors is much smaller than that of reported CNTFETs with other gate dielectrics made by a thermal oxidation process17,20 and even a molecular beam epitaxy/chemical beam epitaxy process.27 The low interface trap density indicates that our Y2O3 lm is of a very high quality as a dielectric layer and the combination of a low
11320 | Nanoscale, 2014, 6, 11316–11321
interface trap density and large Cox ensures an excellent SS for CNTFETs integrated with a Y2O3 gate dielectric.
Experimental The CNTs used in this work were directionally grown on a silicon substrate and semiconducting single-walled CNTs were identied via eld-effect measurements using the substrate as the back-gate. A three-step process was used to fabricate the CNTFETs using Y2O3 as the top-gate dielectric. Large test pads were rst developed via an electron beam lithography process and a bilayer metal, Ti (5 nm)/Au (35 nm), was deposited on the silicon wafer via electron beam evaporation. A subsequent standard li-off was carried out to form a test pad. A 3 nm thick layer of Y (99.9% purity, purchased from Grirem Advanced Materials Co. Ltd) was then deposited at a rate of 1 A s1 through the electron beam evaporator with a vacuum >5 108 Torr. Aer thermal oxidization on a hot-plate at 240 C in air, a Y2O3 lm of 6 nm was formed. The last step involved fabricating the gate and source–drain electrodes through electron beam lithography and electron beam evaporation. The gate electrode was usually metal layers of 5 nm/70 nm thick Ti/Au (or Pd), while the source–drain contact metal was 70 nm Sc for n-type FETs. It should be noted that the Sc lm was evaporated under an ultrahigh base vacuum of up to 5 108 Torr to form a highperformance n-type ohmic contact with the CNT.12 All the electrical measurements were carried out using a probe station. The temperature properties of the devices were tested in the probe station in air, whereas the low temperature measurements were made using a low temperature probe station (Lakeshore TTP-4) in a vacuum at temperatures varying from room temperature to liquid nitrogen temperatures. A Keithley 4200 semiconductor analyzer and an Agilent 4156 semiconductor analyzer were used in the DC transport measurements.
Conclusions We have fabricated top-gated sub-50 nm CNTFETs using completely oxidized high-quality Y2O3 as the gate dielectric. This forms a continuous polycrystalline structure without any large defects. With an omega-shaped gate geometry and a low interface trap density, the Y2O3 lm showed an excellent gate control ability for CNTFETs. In particular, for both long gate and short gate CNTFETs with a sub-50 nm gate length, a low average SS of 74 mV per decade was achieved and a small DIBL observed. The performance of the CNTFETs was shown to
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increase with decreasing temperature and an excellent SS down to 22 mV per decade was obtained at liquid nitrogen temperatures. In addition, a method based on variable temperature measurement data was developed to retrieve the interface trap density in CNTFETs with Y2O3 as the gate dielectric and a relatively low interface trap density (about 5.2 106 cm1 at a 1 V surface potential) was achieved.
Acknowledgements This work was supported by the Ministry of Science and Technology of China (Grant no. 2011CB933001 and 2011CB933002), the National Science Foundation of China (Grant no. 61322105, 61271051, 61376126, 61321001 and 61390504) and the Beijing Municipal Science and Technology Commission (Grant no. Z131100003213021 and 20121000102).
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Exploration of yttria films as gate dielectrics in sub50 nm carbon nanotube field-effect transistors† Li Ding,a Zhiyong Zhang,*a Jun Su,b Qunqing Lic and Lian-Mao Peng*a Thin yttria films were investigated for use as gate dielectrics in carbon nanotube field-effect transistors (CNTFETs) with the gate length scaled down to sub-50 nm size. The yttria film provided an omegashaped gate dielectric with a low interface trap density, a low average sub-threshold swing of 74 mV per decade for both long and short CNTFETs, and a small drain-induced barrier lowering. It was also shown
Received 22nd June 2014 Accepted 25th July 2014
that the performance of CNTFETs increases with decreasing temperature, with an excellent subthreshold swing of 22 mV per decade at liquid nitrogen temperatures. A method was developed to
DOI: 10.1039/c4nr03475a
retrieve the interface trap density in CNTFETs and a low interface trap density of 5.2 106 cm1 was
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achieved, indicating the high electric quality of the yttria films.
Introduction Field-effect transistors (FETs), devices that use an electric eld to control the conductivity of a semiconductor channel, are the most important and widely used electrical devices in modern integrated circuits (ICs). A high-performance FET must have all of the following properties: excellent semiconducting channel materials; ideal ohmic source–drain contacts; and a highquality gate dielectric. As the FET devices most oen used, i.e. silicon-based metal oxide semiconductors, were developed almost 50 years ago, they are expected to reach their limit, both scientically and technologically, in the near future based on the predictions of Moore's law.1,2 Carbon nanotubes (CNTs) are considered to be one of the most promising candidate materials to replace silicon as the channel material in the next generation high-performance FETs, mainly owing to their unique structural, mechanical, chemical and, in particular, electrical properties, including an ultra-thin body, high carrier mobility and high saturation velocity.3–6 Since the rst FETs based on CNTs were developed in 1998,7 great advances have been made in developing high-performance CNTFETs, circuits and systems.4–11 In particular, ideal ohmic contacts have been realized in CNTFETs through adopting Sc12 and Y13 for n-type and Pd4 for p-type contacts, leading to a contact resistance that approaches the quantum
a
Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing, 100871, P. R. China. E-mail: zyzhang@pku. edu.cn; [email protected]
b
Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and Technology, Wuhan, 430074, P. R. China
c Department of Physics and Tsinghua-Foxconn Nanotechnology Research Center, Tsinghua University, Beijing, 100084, P. R. China
† Electronic supplementary 10.1039/c4nr03475a
information
11316 | Nanoscale, 2014, 6, 11316–11321
(ESI)
available.
See
DOI:
limit. Moreover high-k dielectrics such as HfO2, ZrO2 and Al2O3 have been explored for use as gate dielectrics to enhance the gate efficiency of CNTFETs. High values of trans-conductance and low sub-threshold swing (SS) have been achieved in both nand p-type FETs for relatively long gate length (>100 nm) devices.14–20 However, these conventional high-k dielectrics are not suitable for providing the highest gate efficiency in CNTs. Experimentally, almost all top-gated CNTFETs with a short gate length (80 mV per decade21–23 The SS is important because it is the key parameter for describing the turn-off speed of an FET. In general, the smaller the SS, the smaller the off-state current at a xed supply voltage and therefore the power dissipation is reduced. CNT-based FETs have now been scaled down to sub-10 nm in size and have shown a much better on-state current than silicon metal oxide semiconductor FETs, with little degradation of the SS. However, these sub-10 nm CNTFETs were fabricated using a back-gate device geometry,24,25 which avoids the difficult task of growing ultra-thin high-k top-gate dielectrics. To fabricate high-performance top-gate CNTFETs that are more suitable for constructing large-scale ICs, an ultra-thin dielectric layer needs to be fabricated on the CNT to ensure efficient gate control on the channel. However, dielectric layers thinner than 8 nm cannot be readily grown on CNTs using conventional methods, such as atomic layer deposition.26 This is because the usual high-k dielectric layer cannot nucleate on a perfect CNT without defects and therefore thick dielectric layers are usually grown from an SiO2 substrate to bury the CNTs. It is highly desirable to have an ultra-thin, high-quality gate dielectric to provide the efficient control required for small CNTFETs with a gate length 12 mA and gm increases to 17 mS at Vds ¼ 0.5 V (Fig. 1d). The increase in saturation current and trans-conductance is a direct consequence of scaling down the transistor. Furthermore, the on-state performance of the CNTFET can be further improved if a self-aligned gate structure is used to fabricate the short gate FETs. We now consider further the electrical characterization of the Y2O3 gate dielectric in CNTFETs, including the leakage current and hysteresis. Less than 10 pA leakage current and 80 mV hysteresis were typically found for these CNTFETs (Fig. S2 and S3†). It is thus concluded that, by adopting a Y2O lm as the gate dielectric in CNTFETs, we can take full advantage of the scaling of the dimensions of the device with few short channel effects, such as degradation of the SS and an increased DIBL. An ideal gate dielectric should enable a consistent yield with a low SS in the device,27 which, in turn, reects the quality and uniformity of the dielectric layer and the interface between the dielectric layer and the CNT. To test this consistency, we fabricated and measured numerous CNTFETs, including 10 devices with a short gate length and 19 devices with a long gate length. The transfer characteristics of these short and long gate length CNTFETs are plotted in Fig. 1e and f, respectively. Although the 19 long gate devices were fabricated using different CNTs on different regions of the silicon wafer, the results show little variation in the SS (from 62 to 82 mV per decade). The average SS value is as low as 74 mV per decade, which is nearly equal to that of the best back-gate CNTFETs with lanthanum oxide as the gate dielectric.27 The variation in threshold voltage (Vt) is about 0.38 V as a result of the uctuations in the CNT diameter and the environment of different CNTFETs on the silicon wafer. For the 10 short channel devices with a gate length of about 50 nm, the SS varies from 64 to 88 mV per decade and the average SS value is 74 mV per decade. Statistical analysis showed no SS
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degradation as the gate length decreased from 1.5 mm to 50 nm, i.e. these devices are hardly affected by short channel effects down to the sub-50 nm scale. Compared with the results for long channel devices, the variation in Vt is around 0.5 V for the short gate length devices, which is a little larger (about 120 mV) than that of the long gate length devices. By denition, low SS means a low off-state current for a given bias. The off-state current is an important parameter for an FET in the design of low power circuits and it determines the static power dissipation of the IC.30 Ideally, an FET should have a low off-state current and thus a low static power dissipation, and a high on-state current for high speed and driving ability. To evaluate our CNTFETs, two typical CNTFETs (with long and short gate lengths, respectively) were examined at Vds ¼ 0.5 V. The transfer characteristics of the two devices are shown in Fig. 2a, in which the long gate device with Lg ¼ 1.5 mm shows an SS of 65 mV per decade, whereas the short gate device with Lg ¼ 56 nm shows an SS of 75 mV per decade. From these transfer characteristics, the on- and off-state currents may be extracted using a standard method,31 as shown in Fig. 2b. A blue box with a width Vds ¼ 0.5 V is rst dened around the threshold voltage of the device Vth extending from 1/3Vds as the lower voltage to 2/3Vds as the higher voltage. This box intercepts the transfer characteristics (which are aligned with Vth) and the le and right intercepts are Ioff and Ion, respectively. The Ioff/Ion ratio is 1.8 mA/4.7 nA (383) for the long device and 7.6 mA/14 nA (543) for the short device. This increased current on/off ratio is a direct consequence of the more rapidly increased on-state current than off-state current for this short CNTFET, given the condition that the SS of the device is not signicantly decreased. To obtain a statistical analysis, the on- and off-state currents for 10 short gate devices are presented in Fig. 2c and the on- and off-state currents for 16 long gate devices in Fig. 2d. For long
Paper
gate devices, Ion varies from 0.4 to 3.5 mA and Ioff varies from 0.6 to 55 nA. For short gate devices, Ion varies from 2.9 to 8.0 mA and Ioff varies from 14 to 314 nA. Although Ioff increases in short gate devices compared with long gate devices, the current on/off ratio remains around several hundred, which is similar to that of long gate devices (Fig. S4†). As a benet of the scaling of the FET, the distribution of the Ion values of short devices is obviously narrower than that of long gate devices as the sub-50 nm devices begin to be dominated by ballistic transport and to be immune to the effects of channel scattering. To compare the performance of the CNTFETs with Y2O3 as the gate dielectric with silicon metal oxide semiconductor FETs and CNTFETs fabricated using other gate dielectrics with comparable gate lengths, two key popular metrics were used, i.e. the SS and intrinsic gate delay, to benchmark the switching-off and turning-on properties of our short gate CNTFETs. Fig. 3 shows the SS values of various short channel FETs with Lg < 120 nm. For a gate length of about 100 nm, the CNTFETs with Y2O3 as the gate dielectric show a similar SS to the planar silicon FETs. As gate length scales down to 50 nm, the SS of planar Si FETs is degraded to beyond 80 mV per decade as a result of the short channel effects, while the SS of our CNTFETs does not increase signicantly. Signicantly, the SS of our CNTFETs is as good as (or even better than) that of the conventional semiconductor-based FETs with well-designed gates such as the Fingate, Tri-gate and gate-all-around, and we attribute this excellent performance to the combination of the ultra-thin body of the CNTs and the high gate efficiency of the high-quality Y2O3 gate dielectric used in this work. Compared with other
Performance comparison between CNT FETs and silicon devices. The data for the silicon devices is taken from Chau et al.31 and F-BG, F-TG, J 2013 and J 2004 are taken from ref. 21, 22, 23 and 25, respectively; and Zhang is taken from ref. 16 and 32. (a) SS and (b) intrinsic gate delay versus gate length. (c) Typical cross-sectional TEM image showing a CNT device with Y2O3 as the gate dielectric. Scale bar denotes 10 nm. Inset in top corner is an enlarged region of Y2O3 marked by the white square in the image. (d) Atomic ratio of Y to O extracted from XPS results measured at three different depths (0, 2 and 6 nm) from the Y2O3 a film surface. Fig. 3
On- and off-state current extraction for CNTFETs with Y2O3 gate dielectric. (a) Transfer characteristics of typical long gate and typical short gate CNTFETs at Vds ¼ 0.5 V. (b) On- and off-state current extraction. (c) On- and off-state current data extracted from 10 short gate devices of Fig. 1e. (d) On- and off-state current data extracted from 16 long gate devices of Fig. 1f. Fig. 2
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published sub-50 nm CNTFETS,21–23 our devices obviously show a lower SS as a result of the greater gate control ability of the Y2O3 dielectric layer and the lower trap density at the Y2O3–CNT interface. It is obvious from Fig. 3a that almost all the FETs show a degradation in SS as the gate length is scaled down to the sub-100 nm level, whereas our CNTFETs with Y2O3 the as gate dielectric show no visible tendency of SS degradation down to 45 nm. The intrinsic gate delay of our CNTFETs was calculated using the method of Chau et al.,31 which was also used in earlier work.13,15,16,32 The results are plotted in Fig. 3b, together with those for previously reported n-type FETs.16,32 The gate delay values of our CNTFETs are systematically smaller than those of silicon n-FETs with the same gate length. The use of Y2O3 allows the gate delay of n-type CNTFETs to be scaled down with gate length according to the scaling track of our previous work.16,32 The best gate delay of n-type CNTFETs is further decreased to 0.41 ps in one device with a gate length of about 45 nm. The excellent gate delay of our n-type CNTFETs results from the use of the excellent n-type ohmic contact, the high-quality Y2O3 gate dielectric, the nature of the quasi-ballistic transport in short channel CNTFETs and the very high Fermi velocity of CNTs.3 The transmission electron microscopy (TEM) image in Fig. 3c shows a cross-section of the gate stack used in our devices. The CNT is seen to have been fully covered by a thin Y2O3 lm, which forms an excellent omega-shaped gate stack around the CNT. Platinum metal was deposited above the Y2O3 to protect the device from being damaged during focused ion beam cutting of the device to prepare an electron beam transparent sample for TEM examination. Two important observations may be made from the TEM image, which may have remarkable inuences on the performance of the device. First, the yttria layer wets very well with the CNT, which results from the excellent wetting behavior of the metal Y and the CNT. As a direct result, the yttria layer uniformly wraps around the CNT to form a perfect omega-shaped gate, which may yield excellent electrostatic gate control on the CNT channel and a high gate efficiency.33 Second, the yttria layer clearly has a continuous polycrystalline structure in which no large defects such as pinholes are observed. The high crystallinity indicates that the structural quality of the yttria lm is high; this is further conrmed by the XPS results shown in Fig. 3d. The Y : O element ratios at various depths in the yttria lm were extracted from the XPS results (Fig. S5†). The Y : O ratio is 0.667 for an ideal yttria lm, which is almost true for most of the 6 nm thick lm, except at the interface with the SiO2 substrate where some intermixing may have occurred, leading to a slightly higher O to Y ratio at the interface. An excellent gate dielectric for an FET not only leads to a large gate capacitance and small leakage current, but also a low interface trap density. The interface traps may result in hysteresis in the transfer characteristic of the FET and induce SS degradation. Therefore the interface trap density is an important parameter for characterising the gate dielectric and should be reliably retrieved from experimental results. For an FET, the SS is given by.
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SS ¼
dVg kT ¼ m$lnð10Þ$ ; q dðlog Ids Þ
(1)
where k is the Boltzmann constant, T is the temperature, q is the charge of an electron and m is usually referred to as an ideality factor.2,34 According to eqn (1), the SS of a device is proportional to temperature T, meaning that the CNTFETs show a better switching-off behavior at low temperatures. Measurements were thus conducted at various temperatures on a typical short gate CNTFET with Lg ¼ 50 nm and the results are presented in Fig. 4. Fig. 4a shows the transfer characteristics of the device measured at room temperature (300 K) and at liquid nitrogen temperature (77 K) at Vds ¼ 0.1 V. It is obvious that the transistor shows a much better performance at lower temperatures, i.e. a larger onstate current and a lower off-state current. In particular, SS is reduced from 80 mV per decade at 300 K to 24 mV per decade at 77 K. The increased on-state current at lower temperatures is mainly a result of the freezing of phonon scatterings, whereas the perfect linear Ids–Vds relation at low bias in Fig. 4b shows that the perfect ohmic contact to the CNT used in the device is retained at temperatures as low as 77 K. As shown in Fig. 4c, the interface traps in a CNTFET are usually located at the interface between the CNT and the gate dielectric layer. The interface trap states usually lie within the CNT band gap and may quickly exchange charges with the CNT.2,34 In addition to interface trap charges, xed oxide charges, ionic mobile charges and oxide trap charges may also exist and are located near the interface or inside the oxide layer. In principle, all the different types of charge near the CNT channel could affect the device performance, e.g. the SS, but the interface trap charges near the interface dominate because the electrostatic interaction decays rapidly with distance. To a good approximation, the factor m in eqn (1) may be expressed as:15,17–20,27
Fig. 4 Low temperature measurements of CNTFETs with Y2O3 as the gate dielectric layer. (a) Transfer characteristics of one device measured at room temperature (black line) and 77 K (red line) at Vds ¼ 0.1 V. (b) Output characteristics of the device in (a) measured at 77 K. (c) Schematic diagram showing interface traps in top-gated CNTFETs. (d) Experimental and fitted SS values from room temperature to 77 K.
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Comparison of some typical gate dielectrics used in CNTFETs
Martel et al.17 Kumar et al.20 Franklin et al.27 This work
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Oxide
Process
3r
m
Cox (pF cm1)
Cit (pF cm1)
Nit (1 106 cm1) @ 1 V
SiO2 SiO2 Lanthanum oxide Y2O3
Thermal oxidation Thermal oxidation MBE/CBE Thermal oxidation
3.9 3.9 27 10
12.2 16 1.22 1.39
N/A 0.18 6.2 2.16
N/A 2.72 1.35 0.84
N/A 18 8.4 5.2
m¼1þ
Cit ; Cox
(2)
where Cox represents the oxide capacitance and Cit represents the capacitance due to the interface traps. In a CNTFET, the oxide dielectric capacitance Cox can be calculated as 2.16 pF mm1 using the relation Cox ¼ 2p3r30/ln(2tox/r),
(3)
where 3r is the relative dielectric constant of Y2O3 (about 10),29 tox is the thickness of the Y2O3 layer (about 6 nm) and the radius of the CNT r is about 1 nm. Cit may be readily extracted from the SS values of the device measured at different temperatures once the oxide capacitance Cox is known accurately. Indeed, several groups have obtained the interface trap density using this direct method.17,20,27 However, this direct method assumes that the SS value is 0 mV per decade at 0 K, which is not true for real devices. This is because measurement errors and the precision limit induced by instruments and wiring may result in a deviation of the actual SS value from its ideal value. We note that this systematic deviation is not dependent on the sample temperature as all measurement instruments are kept at room temperature. To account for this systematic error, we propose here an improved method to obtain the interface trap density through tting the temperature-dependent SS values. A representative CNTFET value was measured at 77, 170 and 290 K and the temperature dependent SS of the CNTFET is plotted in Fig. 4d, which shows a good linear dependence on temperature. The tted slope of the SS–T data set is 0.27 0.031, which is, in turn, used to retrieve the ideality factor of eqn (1) to yield m ¼ 1.39 and Cit ¼ 0.39 Cox ¼ 0.84 pF mm1. The capacitance associated with the interface trap states is dened as the interface trap charges divided by the surface potential, i.e. Cit ¼ Qit/4s, where the surface potential 4s is the potential applied by the gate voltage at the interface between the CNT and Y2O3. The interface trap charge Qit is dened as Qit ¼ qNit with Nit being the interface trap density. We may thus obtain the interface trap density from the interface trap capacitance to obtain Nit ¼ 5.2 106 cm1 at 4s ¼ 1 V. This and other relevant quantities are summarized in Table 1 and compared with the results of three other research groups. It is worth mentioning that the interface trap density found in our transistors is much smaller than that of reported CNTFETs with other gate dielectrics made by a thermal oxidation process17,20 and even a molecular beam epitaxy/chemical beam epitaxy process.27 The low interface trap density indicates that our Y2O3 lm is of a very high quality as a dielectric layer and the combination of a low
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interface trap density and large Cox ensures an excellent SS for CNTFETs integrated with a Y2O3 gate dielectric.
Experimental The CNTs used in this work were directionally grown on a silicon substrate and semiconducting single-walled CNTs were identied via eld-effect measurements using the substrate as the back-gate. A three-step process was used to fabricate the CNTFETs using Y2O3 as the top-gate dielectric. Large test pads were rst developed via an electron beam lithography process and a bilayer metal, Ti (5 nm)/Au (35 nm), was deposited on the silicon wafer via electron beam evaporation. A subsequent standard li-off was carried out to form a test pad. A 3 nm thick layer of Y (99.9% purity, purchased from Grirem Advanced Materials Co. Ltd) was then deposited at a rate of 1 A s1 through the electron beam evaporator with a vacuum >5 108 Torr. Aer thermal oxidization on a hot-plate at 240 C in air, a Y2O3 lm of 6 nm was formed. The last step involved fabricating the gate and source–drain electrodes through electron beam lithography and electron beam evaporation. The gate electrode was usually metal layers of 5 nm/70 nm thick Ti/Au (or Pd), while the source–drain contact metal was 70 nm Sc for n-type FETs. It should be noted that the Sc lm was evaporated under an ultrahigh base vacuum of up to 5 108 Torr to form a highperformance n-type ohmic contact with the CNT.12 All the electrical measurements were carried out using a probe station. The temperature properties of the devices were tested in the probe station in air, whereas the low temperature measurements were made using a low temperature probe station (Lakeshore TTP-4) in a vacuum at temperatures varying from room temperature to liquid nitrogen temperatures. A Keithley 4200 semiconductor analyzer and an Agilent 4156 semiconductor analyzer were used in the DC transport measurements.
Conclusions We have fabricated top-gated sub-50 nm CNTFETs using completely oxidized high-quality Y2O3 as the gate dielectric. This forms a continuous polycrystalline structure without any large defects. With an omega-shaped gate geometry and a low interface trap density, the Y2O3 lm showed an excellent gate control ability for CNTFETs. In particular, for both long gate and short gate CNTFETs with a sub-50 nm gate length, a low average SS of 74 mV per decade was achieved and a small DIBL observed. The performance of the CNTFETs was shown to
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increase with decreasing temperature and an excellent SS down to 22 mV per decade was obtained at liquid nitrogen temperatures. In addition, a method based on variable temperature measurement data was developed to retrieve the interface trap density in CNTFETs with Y2O3 as the gate dielectric and a relatively low interface trap density (about 5.2 106 cm1 at a 1 V surface potential) was achieved.
Acknowledgements This work was supported by the Ministry of Science and Technology of China (Grant no. 2011CB933001 and 2011CB933002), the National Science Foundation of China (Grant no. 61322105, 61271051, 61376126, 61321001 and 61390504) and the Beijing Municipal Science and Technology Commission (Grant no. Z131100003213021 and 20121000102).
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