Nanoscale View Article Online

Published on 12 March 2014. Downloaded by University of Alberta on 26/10/2014 22:17:38.

PAPER

View Journal | View Issue

Cite this: Nanoscale, 2014, 6, 5479

High performance Si nanowire field-effecttransistors based on a CMOS inverter with tunable threshold voltage† Ngoc Huynh Van,a Jae-Hyun Lee,b Jung Inn Sohn,c Seung Nam Cha,c Dongmok Whang,b Jong Min Kimc and Dae Joon Kang*a We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a lowtemperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the

Received 17th December 2013 Accepted 9th March 2014

nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (#3 pW) for high-performance digital inverter devices. This result offers a viable means of

DOI: 10.1039/c3nr06690h

fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-

www.rsc.org/nanoscale

temperature fabrication processing technique suitable for next-generation flexible electronics.

1. Introduction Complementary metal-oxide semiconductor (CMOS) based logic devices involving n-type and p-type eld-effect-transistors (FETs) are used almost exclusively in digital circuits due to their simplicity, noise immunity and low static power consumption. Of these logic devices, inverters are one of the most common building blocks in digital circuit designs.1 Semiconductors in the form of one-dimensional nanostructures such as nanowires (NWs), nanotubes, and nanocables have been used as conducting channels in FETs. These materials have recently attracted a great deal of attention due to their unique and superior physical properties, as well as their potential to overcome critical technical and physical limitations encountered when scaling-down traditional lithography-based thin-lm transistor (TFT) devices.2–4 The high crystalline quality of semiconducting NWs allows them to function as a superior carrier transport channel as they display enhanced eld effect mobility and sub-threshold slope and operation voltage.5–8 Additionally, the small dimensions of NWs allow for a high-density area in devices. It has been proposed that NWFETs could exhibit higher performance and more stable

a

Department of Physics, Institute of Basic Science, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746, Republic of Korea. E-mail: [email protected]; Fax: +82-31-290-5947; Tel: +82-31-290-5906

b

School of Advanced Materials Science and Engineering, SKKU Advanced Institute of Nanotechnology, Sungkyunkwan University, Suwon 440-746, Republic of Korea

c

Department of Engineering Science, University of Oxford, Oxfordshire OX1 3PJ, UK

† Electronic supplementary 10.1039/c3nr06690h

information

(ESI)

This journal is © The Royal Society of Chemistry 2014

available.

See

DOI:

transistor characteristics than conventional, amorphous siliconand polysilicon-based TFTs.9 The superior carrier mobility and small size characteristics of CNTs and graphene ribbons have been exploited to surpass the current Si technology in terms of operation speed in logic device applications.10–13 Despite advances in these materials, there is still a large gap between the status of CNT- and graphene-ribbonbased FETs and industrial application requirements, in particular the low ION/IOFF ratio of graphene FETs and the OFF-state leakage problem, largely owing to unwanted tunnelling mechanisms and ambipolar behavior. The difficulty in selecting metallic or semiconducting CNTs also limits their use in industrial applications. Thus far, Si remains the best candidate for conducting channels in terms of mobility, and thus Si nanowires have been intensively investigated by many research groups as a replacement for standard CMOS-based TFT technology.6,7,14 Despite the high performance, sensitivity, and efficiency of NWFETs, some outstanding issues must be resolved before NWFETs are viable for practical digital applications. One critical issue is the operating mechanism of the n-type NWFETs. The negative threshold voltage, which is due to the depletion mode in typical n-type NWFETs, causes NW-based CMOS inverters to operate at tri-state voltages (negative, zero and positive). This limits the use of NWFETs to digital logic circuits that require either a positive or a negative voltage to represent two logic levels (0 and 1), such as TTL, CMOS and ECL voltage standards for logic levels. Modern digital logic circuits require TFTs to operate at voltages lower than 1 V (ref. 15) and to have less than a 60 mV dec1 sub-threshold for high-performance, lowpower operation of electronic devices.16–18 In this study, we

Nanoscale, 2014, 6, 5479–5483 | 5479

View Article Online

Nanoscale

Published on 12 March 2014. Downloaded by University of Alberta on 26/10/2014 22:17:38.

demonstrate that these issues can be easily overcome by controlling the doping concentration to modulate the electrical properties of Si NWs, and that the threshold voltages of n-type Si FETs can be easily shied toward a positive region, making them more suitable for advanced digital circuit operations. Our inverter devices exhibit excellent performance characteristics, a low operation voltage, and static power dissipation, making them suitable for both analog and digital applications.

2.

Experimental

The n- and p-type Si NWs used in this study were grown on (100) Si substrates with Au catalysts using a vapor–liquid–solid method, as reported in detail by T. Koo et al.19 Single crystalline Si NWs with a typical diameter of 50–70 nm were rst dispersed via ultra-sonication in isopropanol, and then transferred onto a silicon substrate by dropping a liquid suspension of Si NWs from a pipette. A heavily doped p-type Si substrate was employed as a back gate with a 100 nm thick, thermally oxidized top layer as a gate oxide layer. Source and drain electrodes were patterned using standard photolithography, followed by electron-beam evaporation of 80 nm thick Ti and 50 nm thick Au electrodes on an n-type Si NW (80 nm thick Ni and 50 nm thick Au electrodes on a p-type Si NW) to form Ohmic contacts between NWs and electrodes, and a li-off process. The NWs were etched in a buffered 1% hydrouoric acid solution for 15 s to remove the native oxide layer that formed on the surface of the NWs prior to the electrode deposition.19 The electrical characteristics of the devices were measured in air using a probe station with a Keithley SCS-4200 system.

3.

Results and discussion

Operational mechanism of the NWCMOS inverter The schematic diagram of the back gated n- and p-type NWCMOS-based inverter devices and the corresponding circuit

Paper

diagram are shown in Fig. 1a and b. The operational principle of the NWCMOS inverter is proposed and shown schematically in Fig. 1c and d. Unlike conventional thin-lm-based MOSFETs that operate in either inversion or enhancement channel mode, our NWFETs work in a depletion–accumulation mode. For example, in the depletion–accumulation mode, at a gate voltage of +5 V, the positive electrostatic gate potential bends the Si NW conducting channel band downward, bringing the conduction band of n-type Si NWs close to the Fermi level and causing accumulation of electrons in the NWs. This accumulation of electrons increases conductivity and allows n-type Si NWFETs to operate at an ON (low resistance) state, while bringing the ptype Si NW valence band away from the Fermi level, causing hole depletion in the NWs and decreasing the conductivity of the p-type Si NWFETs. In this particular case, p-type Si NWFETs operate at an OFF (high resistance) state; therefore, an inverter read-out state of 0 V will be observed due to the grounding of the output and Vss through the ON state of n-type Si NWs. Conversely, the negative electrostatic potential at a gate voltage of 5 V will bend the Si NW conducting channel band upward, bringing the n-type Si NW conduction band away from the Fermi level, and deplete electrons in the NWs, causing the ntype Si NWFET to operate at an OFF state. At the same time, bringing the p-type Si NW valence band close to the Fermi level causes accumulation of holes in the NWs, and the operation of p-type Si NWFETs is in an ON state. Thus, the inverter output of 1 V will be observed due to the connection of output and Vdd through an ON state in the p-type Si NW. Fig. 1e shows the Ids–Vg transfer characteristics of p- and ntype Si NWFETs. We can assume that the inverter output is the combination of resistance states or current through single nand p-type Si NWFETs. At a gate voltage (Vg) of 5 V, a large current gap difference in n- and p-type Si NWs with an ION/IOFF ratio of more than 4 orders of magnitude was observed. Fig. 1f shows the inverter input–output characteristic for input pulses of 5 V. Inverter output voltages were observed at the 0 and 1 V

Fig. 1 Inverter device and working mechanisms. (a) A schematic view of a back gate inverter device based on n- and p-type Si NWFETs. (b) The circuit of a CMOS inverter. The working mechanism of a NWFET CMOS inverter device with a back-gate voltage of +5 V (c) and 5 V (d). (e) Ids–Vg transfer characteristics of p- and n-type Si NWFETs and (f) the dynamic response of the inverter to square wave input pulses of 5 V, with Vdd set at 1 V.

5480 | Nanoscale, 2014, 6, 5479–5483

This journal is © The Royal Society of Chemistry 2014

View Article Online

Published on 12 March 2014. Downloaded by University of Alberta on 26/10/2014 22:17:38.

Paper

states, for input pulses of 5 V; this result implies that our inverter can function with a 5 V input. When the input pulse voltage was reduced to 1 V, the output voltage was measured at approximately 0.3 V for input voltage pulses of +1 V (see Fig. S2a in the ESI†). When the input voltage was set to 0 V, the output was approximately 0.15 V (see Fig. S2b in the ESI†). These output voltages result from the combination of minimum current through single n- or p-type Si NWFETs, and resistance states at certain gate voltages. The operation of NWCMOS inverters at tri-state input voltages (negative, zero and positive) has been demonstrated;21–23 however, as we described above for digital inverter applications, the inverter output is expected to be equal to 1 V at an input gate voltage of 0 V. In our inverter device, the output voltage is between 0 and 1 V due to the combination of minimum current through single n- or p-type Si NWFETs, and resistance states at 0 V gate voltage. The main drawback when using the NWFET as the digital inverter is that an n-type NWFET is not at an OFF state when the gate voltage is equal to 0 V, due to the depletion–accumulation mode of NWFETs. In addition, a larger negative threshold voltage requires a larger negative gate voltage for the device to function as an inverter. To utilize the NWFET as a digital inverter, we need to convert the working mode of either n-type NWFETs from depletion to enhancement mode for digital positive operation voltages, as in TTL and CMOS standards, or convert ptype NWFETs from depletion to enhancement mode for digital negative operation voltage, as in the ECL standard. Several schemes have been proposed to make n-type ZnO NWFETs operate in an enhancement mode by tuning the diameter and surface conditions of the ZnO NWs,24–26 electrode work functions,27 or proton irradiation.28 In this study, we attempted to shi the threshold voltage of n-type Si NWFETs to the positive region by changing the doping concentration. Phosphine (PH3) was used as the n-type dopant. The effect of the doping concentration on the conductance and threshold voltage of n-type Si NWFETs is shown in Fig. 2a. The transfer characteristics of the drain current versus gate-source voltage (Ids–Vg) curves were measured by sweeping the gate voltage of several n-type Si NWFETs, at various doping concentrations (silane (SiH4)–phosphine (PH3) gas ratios from 4000 : 1 to 10 000 : 1) continuously from 5 to 5 V. By reducing the doping concentration, the threshold voltage could be shifted from 4 V to approximately 0 V. Moreover, we can estimate the carrier concentrations from the transfer characteristics (i.e. by varying the doping concentrations). For instance, the electron carrier concentrations were estimated to be 91.6  1017 and 2.4  1017 e cm3 for 4000 : 1 and 10 000 : 1 SiH4–(PH3) gas ratios respectively. Additionally, the reduction of ON current from 107 A to 109 A was observed when the electron carrier concentrations were lowered with decreasing doping concentrations as shown in Fig. S3 of the ESI,† the output characteristics (Ids–Vds) of n-type Si NWFETs at different doping concentrations. Fig. 2b shows a schematic view of a simplied depletion model for n-type Si NWFETs, with different doping concentrations at a constant negative gate voltage. The dark yellow gradient shows the electric eld distribution at certain back gate voltages, resulting in the depletion of the electron

This journal is © The Royal Society of Chemistry 2014

Nanoscale

Fig. 2 Positive shift of threshold voltage of the n-type Si NWFET. (a) Ids–Vg transfer characteristics of n-type Si NWFETs at different doping concentrations and silane (SiH4)–phosphine (PH3) ratios of 4000 : 1 to 10 000 : 1. (b) Schematic view of a simplified depletion model for ntype Si NWFETs at different doping concentrations and a constant negative gate voltage.

carriers of n-type Si NWs. Less dense electron carriers can easily induce complete depletion at the same negative gate voltage; therefore, the reduction in doping concentration leads to less electron carriers in the conducting channel of Si NWs, resulting in reduced conductance and a positive threshold voltage shi of Si NWFETs. To investigate the electrical properties of n-type and p-type Si NWs, we prepared typical NWFETs on a 100 nm SiO2/Si substrate with a back gate electrode. Fig. 3a shows the drain current versus drain-source voltage (Ids–Vds) curves for a single n-type Si NWFET. The conductance of the NW increases monotonically as the gate potential increases from 5 to +5 V, exhibiting a typical n-type Si NWFET behavior. Fig. 3b shows the drain current versus gate-source voltage (Ids–Vg) curves obtained by sweeping the gate voltage continuously from 2 to 5 V at drain voltages ranging from 0 to 1 V. The transconductance (gm) and eld effect electron mobility (me) of the back gate NWFETs were determined from the Ids–Vg curves using the following equations: gm ¼ dIds/dVg and me ¼ gmL2/CoxVds.20 The gate oxide capacitance (Cox) of a cylindrical wire on a planar substrate can be estimated by Cox ¼ 2p3r30L/cosh1(1 + tox/r) using a relative dielectric constant (3r) of 3.9, a SiO2 gate dielectric layer thickness (tox) of 100 nm, a nanowire conducting channel length (L) of approximately 5 mm, and a nanowire radius (r) of approximately 27.5 nm. For n-type Si NWFETs on a SiO2/Si substrate, a

Nanoscale, 2014, 6, 5479–5483 | 5481

View Article Online

Published on 12 March 2014. Downloaded by University of Alberta on 26/10/2014 22:17:38.

Nanoscale

Electrical transport properties of single n- and p-type Si NWFET devices under ambient conditions. (a and c) Ids–Vds output characteristics and (b and d) Ids–Vg transfer characteristics of n- and p-type Si NWFETs, respectively. Fig. 3

threshold voltage (Vth) of 1 V and a transconductance (gm) of 116 nS were extrapolated from the linear region of the Ids–Vg curve at a value of 1 V for the Vds. The eld effect electron mobility (me) and resistivity (r) for the Si NW were calculated from four probe measurements, and found to be 59.3 cm2 V1 s1 and 0.22 U cm, respectively (Fig. S1c in the ESI†). The electron carrier concentration (ne) was calculated to be 4.8  1017 e cm3 using the equation ne ¼ 1/rqme. The sub-threshold swing given as S ¼ log[dVg/d(log Ids)] was estimated to be 125 mV dec1. The same calculation method is applicable for p-type Si NWFETs. A Vth of 2 V, a gm of 90.5 nS, and a eld effect hole mobility (mh) of 46.2 cm2 V1 s1 were calculated from Fig. 3c and d, and r was estimated to be 0.48 U cm from four probe measurements (Fig. S1d in the ESI†). The hole carrier concentration (nh) was estimated to be 6.1  1017 h cm3 using the equation 1/rqmh. The sub-threshold swing (S) value was approximately 205 mV dec1. The sub-threshold swing values of n-type and p-type Si NWFETs are small enough for low-power consumption and low operating voltage, thus demonstrating many other signicant device characteristics for high performance FET devices.5,7 We integrated n-type NWFETs, at various doping concentrations of silane (SiH4)–phosphine (PH3) gas ratios from 4000 : 1 to 10 000 : 1, with one p-type Si NWFET, at doping concentration of a silane (SiH4)–diborane (B2H6) gas ratio of 5000 : 1, to make NWCMOS inverters. The transfer characteristics of an inverter supply voltage (Vdd) of 1 V, with an input voltage (Vin) swept from 1 to 1 V, are shown in Fig. 4a. Due to the difference in threshold voltages and conduction states of ntype NWFETs at certain gate voltages (see Fig. S4 in the ESI†), the inverter input–output characteristics is the difference in the range of input voltage from 1 to 1 V. The inverter did not work in this range of input voltage at high and low doping concentrations of n-type due to high and low conducting states compared with the p-type Si NWFET, respectively. For an n-type

5482 | Nanoscale, 2014, 6, 5479–5483

Paper

Fig. 4 Inverter properties. (a) Vin–Vout inverter characteristics at different n-type Si NW doping concentrations of silane (SiH4)–phosphine (PH3) gas ratios of 4000 : 1 to 10 000 : 1. (b) Ids–Vg transfer characteristics of p- and n-type Si NWFETs and (c) Vin–Vout inverter characteristics. The inset is inverter gain; (d) the dynamic response of the inverter to square wave input pulses of 0 and 1 V and a Vdd set at 1 V.

Si NWFET at threshold voltage close to 0 V and n-type doping concentrations of silane–phosphine gas ratios of 6000 : 1, we see sharp switching output swings at an approximate input voltage of 0.5 V. We pickup n-type Si NWFETs at this doping concentration to do further inverter characteristics. Fig. 4b shows the Ids–Vg transfer characteristics of p- and ntype Si NWFETs at n-type doping concentrations of silane– phosphine gas ratios of 6000 : 1. The inset images of Fig. 4b are the SEM images of the completed p- and n-type Si NWFET devices. Fig. 4c shows the transfer characteristics when Vdd is set to 1 V and Vin is swept from 0 to 1 V. We see sharp switching output swings at approximately 0.5 V, which correspond to large inverter gains (dVout/dVin) of approximately 10.3 (inset of Fig. 4c), and a complete switch to 0 and 1 V at a Vdd of 1 and 0 V, respectively. The key advantage of our NWCMOS inverter is the low consumption of static power, due to a small current ow from the Vdd to the ground. This is irrespective of whether the input is low and the n-type transistor is OFF, or high and the p-type transistor is OFF. We observed static currents that are less than 3 pA at a Vdd of 1 V, and when Vin is 0 V or 1 V; thus, the static power dissipation is approximately 3 pW. To the best of our knowledge, this is the lowest power consumption observed in nanowire-based inverters. The dynamic response of the inverter to a square wave input signal at a frequency of 0.02 Hz at different input voltage ranges is shown in Fig. 4d, at 0 and 1 V input voltage pulses with a Vdd of 1 V. The logic NOT function output voltage stays close to 0 and 1 V when input pulse voltages were xed at 1 and 0 V, respectively; this result represents a high digital inverter matching a low operation voltage of approximately 1 V. Based on this approach, we may further reduce the operating voltage of inverter devices to less than 1 V. However, lowering

This journal is © The Royal Society of Chemistry 2014

View Article Online

Published on 12 March 2014. Downloaded by University of Alberta on 26/10/2014 22:17:38.

Paper

the doping concentration of NWs may lead to reducing the ON state current or ION/IOFF ratio of NWFETs further, which results in a reduced inverter device gain. Our results imply that NWFETs show promise for high-performance analog inverters, as well as for logic circuits such as NOT, NOR and NAND for digital applications. For logic assembling, however, functional digital circuits such as very-large-scale-integration (VLSI) chips, a top omega-shaped gate may be the ideal building block candidate.29,30 This provides a more effective electric eld with respect to the NWFET than the planar-gate. Reducing the nanowire diameter is expected to reduce the operating voltage. Additionally, when the diameter of the nanowire reaches the Bohr radius of the material (typically

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire fie...
552KB Sizes 0 Downloads 3 Views