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Contact properties of field-effect transistors based on indium arsenide nanowires thinner than 16 nm
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2015 Nanotechnology 26 175202 (http://iopscience.iop.org/0957-4484/26/17/175202) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 157.182.150.22 This content was downloaded on 17/04/2015 at 07:53
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Nanotechnology Nanotechnology 26 (2015) 175202 (7pp)
doi:10.1088/0957-4484/26/17/175202
Contact properties of field-effect transistors based on indium arsenide nanowires thinner than 16nm Tuanwei Shi1, Mengqi Fu1, Dong Pan2, Yao Guo1, Jianhua Zhao2 and Qing Chen1 1
Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, People’s Republic of China 2 State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People’s Republic of China E-mail: [email protected] Received 6 February 2015, revised 10 March 2015 Accepted for publication 16 March 2015 Published 9 April 2015 Abstract
With the scaling down of field effect transistors (FETs) to improve performance, the contact between the electrodes and the channel becomes more and more important. Contact properties of FETs based on ultrathin InAs NWs (with the diameter ranging from sub-7 nm to 16 nm) are investigated here. Chromium (Cr) and nickel (Ni) are proven to form ohmic contact with the ultrathin InAs NWs, in contrast to a recent report (Razavieh A et al ACS Nano 8 6281). Furthermore, the contact resistance is found to depend on the NW diameter and the contact metals, which between Cr and InAs NWs increases more rapidly than that between Ni and InAs NWs when the NW diameter decreases. The origins of the contact resistance difference for the two kinds of metals are studied and NixInAs is believed to play an important role. Based on our results, it is advantageous to use Ni as contact metal for ultrathin NWs. We also observe that the FETs are still working in the diffusive regime even when the channel length is scaled down to 50 nm. S Online supplementary data available from stacks.iop.org/NANO/26/175202/mmedia Keywords: InAs nanowire, FET, contact properties, scaling down (Some figures may appear in colour only in the online journal) As the scaling down of metal–oxide–semiconductor (MOS) field effect transistor (FET) continues, device performance, especially gate control efficiency, begins to decline due to short-channel effect (SCE). As a result, nanowires (NWs) draw wide research interest due to their natural advantages in fabricating wrap gate transistors, which have the highest gate control efficiency and therefore avoid SCE. In addition, it is possible for NWs to combine materials with large lattice mismatch because of efficient strain relaxation [1–6]. Of all the NWs, InAs NW in particular is considered to be one of the most promising materials, due to its high electron mobility, high injection velocity, small band gap, and ease of forming ohmic contact with metals because of the surface Fermi-level pinning in the conduction band. So far, InAs NWs have been 0957-4484/15/175202+07$33.00
demonstrated to have great potential in NMOS, RF-transistors, tunnel FET, photodetectors, etc [3, 7–14]. To further enhance device performance, scaling down the InAs NW transistors is strongly needed. Shorter channels bring in higher on-state current and transconductance, due to less scattering for the carriers [15]. At the same time, to keep a constant gate efficiency, the NW diameter should be scaled down with the channel-length scaling. However, so far, most of the InAs NW transistors being studied are based on thick NWs with diameters larger than 15 nm [1, 12, 15–19]. Recently, we have reported enhancement-mode FETs with up to 108 on-off ratio based on InAs NWs thinner than 10 nm, demonstrating the potential for scaling down InAs NW FETs [20]. However, although bulk InAs is well known to form 1
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Nanotechnology 26 (2015) 175202
ohmic contact with metals, a recent work has reported a Schottky barrier between Ni and InAs NWs independent of the NW diameter down to 10 nm [21]. Considering the vital importance of the contact resistance in short-channel FETs, we here study the contact properties of the FETs based on ultrathin InAs NWs with diameters ranging from sub-7 nm to 16 nm. Nickel (Ni), chromium (Cr), and titanium (Ti) are investigated here as contact metals; these are normally used as S/D electrodes in InAs NW transistors [10, 14, 15]. We prove that it is still ohmic contact between ultrathin InAs NWs and metal Ni or Cr by temperature-dependent measurement. By studying the transistors with varied channel lengths on the same individual InAs NWs, we show that the contact resistances have a dependence on the NW diameters and the contact metals. We also observe that the devices are still working in the diffusive regime even when the channel length is scaled down to 50 nm. The InAs NWs used in this study were grown on n-type Si (111) wafer by molecular-beam epitaxy (MBE) using Ag as the catalyst with the conventional one-step catalyst annealing process without intentional doping [22]. The ultrathin NWs (with diameter ranging from sub-7 nm to 16 nm) were selected for device fabrication and they have a wurtzite crystal structure, with their axis along 〈0001〉, free of stacking faults and twins (as shown in supporting information S1). The NWs were first transferred onto a 300 nm-thick SiO2-covered Si substrate through ethanol solution and then located by scanning electron microscopy (SEM). The source and drain (S/D) electrodes, Cr/Au (20/20 nm) or Ni (30 nm) with the width of 200 nm, were defined by electron beam lithography (EBL) and deposited by electron beam evaporation (EBE). The 1.5 nm thick native oxide outside the NWs was removed by the NH4Sx solution just before the S/D metal deposition, so that the metal could contact the NW directly at the electrode area. Besides Cr/Au and Ni, we also studied Ti/ Au (20/50 nm) as S/D electrodes, but found that the S/D current is about the same level as the noise as detected by Keithley 4200 when the InAs NW was thinner than 10 nm. We therefore conclude that Ti/Au cannot form good electrical contact with the InAs NWs thinner than 10 nm. The gate dielectric is a 10 nm thick HfO2 layer grown by atomic layer deposition (ALD) at 90 °C using tetrakis(dimethylamido) hafnium (Hf[(CH3)2N]4) and H2O as precursors. Metal film Ti/Au (20/50 nm) deposited by EBE is used as the gate electrode. The diameters of the NWs were measured by atomic force microscopy (AFM) (as shown in supporting information S2), subtracting the thickness of the oxide, while the channel length was measured by SEM. Multiple S/D contact electrodes were defined with varied spacing on the same individual NWs to fabricate FETs with varied channel length, Lch, as shown in figures 1(a) and (b). The top-gate electrode and the dielectric layer overlap the whole channels and the contact electrodes to obtain effective gate control over the channels and to avoid parasitic resistances of the ungated region. To avoid Ni diffusing into the InAs NW channel, the devices have not been intentionally annealed except keeping at 90 °C for 4 h in N2 during the growth of HfO2 by ALD.
Figures 1(c) and (d) show the output and transfer curves of a typical short-channel InAs NW transistor, with Cr/Au as S/D electrode. The channel length of this transistor is 50 nm and the NW diameter is 12 nm. The normalized on-state current at Vg = 0.8 V of this transistor is over 100 μA μm−1 (normalized by perimeter), which could be further promoted by doping the NWs, considering that the present NWs were grown by MBE without doping, which causes low density of carriers, and as a result large contact and channel resistances. The transfer curves in figure 1(d) show that the Ion/Ioff ratio of the device is over 103 at both Vds = 0.01 V and 0.5 V, which is comparable to the long-channel transistors reported previously [1, 12]. It is well known that InAs easily forms ohmic contact with metals because of the surface Fermi-level pinning near the bottom of the conduction band, which has been confirmed by many works in which the on-state current keeps constant or decreases as the temperature increases [15, 17, 19]. However, a recent work reported a Schottky barrier between Ni and InAs NWs grown by metal–organic chemical vapor deposition (MOCVD) independent of the NW diameter down to 10 nm [21]. Here, we study the properties of the contact between metals (both Cr and Ni) and the ultrathin InAs NWs grown by MBE, through measurements at different temperature similar to what has been reported in the literature [21, 23–25]. FETs with relatively long channels are used here to avoid the SCE on the potential profile and possible contact barrier, and so to get an accurate contact barrier height, if one exists. Figures 2(a)–(d) show the results of a representative device with Cr as S/D electrodes. In this device, the diameter of the NW is 12 nm and the channel length is 330 nm. The transfer curves measured at varied temperatures show that in the subthreshold region (Vg < Vth), the current increases with the temperature, as shown in figure 2(a). The conduction band of the InAs NW in the channel region is lifted by applying a negative gate voltage, which brings a barrier between the source and the channel. The primary conduction mechanism for electrons is thermionic emission over the barrier, so that more electrons will overcome the barrier as the temperature increases. On the other hand, in the on-state region (Vg > Vth), as shown in figure 2(b), the current keeps roughly the same first and then decreases as the temperature increases to 260 K, which excludes the existence of a barrier. The reason for the decreasing current at 260 K is probably due to the increased scattering at higher temperature. To quantitatively investigate the contact, the corresponding Arrhenius plots are drawn for various Vg in figure 2(c). The barrier height between source and channel ΦB can be extracted from the conventional thermionic equation [21, 23–25]: Ids = A*T 2 exp −( qΦB ) / ( k B T ) ⎡⎣ 1 − exp −( qVds ) / ( k B T ) ⎤⎦
(
)
(
)
(1)
where A* is the Richardson's constant, kB is the Boltzmann constant, q is the charge of an electron, and T is the temperature. As Vds here is 0.5 V, the part in the square 2
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Nanotechnology 26 (2015) 175202
Figure 1. (a) Cross-sectional schematic of the top-gate MOSFETs with varied channel length based on the same individual InAs NW. (b)
Top-view SEM image of a typical device. (c) The output curves of a typical short channel MOSFET with the NW diameter of 12 nm and the channel length of 50 nm, Cr/Au as S/D electrode. (d) The transfer curves of the same transistor in (c) measured at Vds = 0.01 V and 0.5 V.
Figure 2. (a) Transfer curves of a typical Cr-contacted MOSFET measured at varied temperatures from 120 K to 260 K in an exponential
coordinate. (b) The same curves as (a) in a linear coordinate. (c) Arrhenius plots of (a) for various gate voltages. (d) Barrier height of the Crcontacted device extracted from (c) showing ohmic contact at the on-state. (e) Barrier height of a Ni-contacted device.
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brackets, 1 − exp(−(qVds)/(kBT), is approximately equal to 1 and the barrier at the drain side is cleared. The barrier height ΦB can then be extracted from the linear relationship between ln(Ids/T2) and 1/T at high-temperature region (T > 160 K), the results of which are shown in figure 2(d). In the subthreshold region (Vg < Vth), the effective barrier height ΦB linearly responds to the gate voltage Vg when near Vth. This is because the thermionic emission is the main conduction mechanism. Flat band voltage VFB is extracted from the end of the linear relationship [23]. In the case shown in figure 2(d), VFB is very close to Vth, and ΦB is near and smaller than zero. As the gate voltage increases further to the on-state region, the barrier height remains negative, indicating there is no barrier between the metal electrodes and the channel, i.e. ohmic contact between Cr and the ultrathin InAs NWs. The same results are obtained for the transistors with Ni contact, as shown in figure 2(e), where the NW diameter is 13.5 nm and the channel length is 410 nm. All the transistors we measured at varied temperature, including four with Cr contact electrodes and four with Ni contact electrodes, show the same results, proving that the contact between the Ni or Cr metal electrodes and the ultrathin InAs NWs grown by MBE is still ohmic contact in contrast to the recent report [21]. The different contact properties could be caused by two reasons. First, the present nanowires were grown by MBE instead of the MOCVD used in the previous report. Second, we use NH4Sx solution to remove the native oxide and passivate the surface of the nanowires, while BOE was used in [21]. To study the contact resistance Rc, the transistors with varied channel lengths on the same individual NWs are fabricated and studied. Figure 3(a) shows the low-field (Vds = 0.01 V) transfer characteristics of a 12 nm thick InAs NW device with Cr as the contact metal, measured at room temperature. With the scaling down of the channel length from 330 nm to 50 nm, the on-state current at the same gate voltage increases, showing the advantage of the scaling down of the channel length. The normalized on-state resistance Ron (normalized by perimeter) is obtained by dividing the drain voltage (Vds = 0.01 V) by the normalized drain current (the fitted values) at Vg − Vth = 1 V, where the transconductance gm is near the peak value. As shown in figures 3(b) and (c), the onstate resistance of the same NW depends roughly linearly on the channel length, indicating that the transistors are still operating in the diffusive regime even when the channel length is scaled down to 50 nm, which means that the lowfield mean-free path λ is smaller than 50 nm. The relatively small λ is probably due to the large surface scattering, considering the large surface/volume ratio for the ultrathin NWs. Also shown in figures 3(b) and (c), the normalized on-state resistance is larger for thinner NW when the channel length is the same, which is consistent with our previous report on the long-channel transistors [20]. The on-state resistance is mainly composed of the contact resistance and the channel resistance. The normalized contact resistance Rc is extracted by transmission line method (TLM) [26], and the value is the half of the y intercept of the normalized on-state resistance versus channel length plots. The
obtained Rc both for Cr and Ni as contact metals is plotted in figure 3(d) as a function of the NW diameter. For the Crcontacted transistors, Rc increases fast with the scaling down of the diameter, increasing about 6 times when the diameter decreases from 16 nm to 6 nm. However, for the Ni-contacted transistors, Rc changes slowly, just increasing around two times when the NWs diameter decreases from 16 nm to 7 nm. Therefore, for NWs of diameters smaller than 15 nm, the contact resistance between Cr and InAs NWs is higher than that between Ni and InAs NWs. The smaller of the NW diameter, the larger differences of Rc. However, for 15 nm to 16 nm thick NWs, Rc is about the same for the two contact metals. Based on our results, it is advantageous to use Ni as contact metal for NWs with diameters smaller than 15 nm. For the NWs with diameter 15–16 nm, the choice of contact metals is not so important. The contact resistance Rc between metal and InAs NW is the sum of two parts: Ruc which is the resistance of the metal and the NW under the metal, and the quantum resistance RQ [15, 27]. Considering that the low-field mean-free path λ is relatively short, Ruc could be described by conventional metal–semiconductor contact model, as shown in figure 4(a) [28–30]. The quantum resistance RQ is a function of the number of the conduction modes in the channel M [30, 31]. The normalized total resistance Rc could be expressed as 2R c = 2R uc + R Q πD = 2 ρc Rsh +
h πD 2e2 M
(2)
where ρc is the contact resistivity between the metal and the NW contacting it (the unit is Ω·μm2), Rsh is the resistance of the NW under the metal, D is the NW diameter, e is electron charge, and h is the Planck’s constant. The effect of the contact electrode length is not discussed here, considering that the present contact length is relatively long (200 nm). Previous calculation and experimental results have shown that as the diameter of InAs NWs decreases in the range of sub-25 nm, the band gap and subband separation increases due to quantum confinement effect, which brings a reduction in the number of transport modes [19, 26, 32]. This explains the rising of the contact resistance when the NW diameter decreases both for Ni and Cr as the contact metal, as shown in figure 3(d). The slow increase of Ni contact resistance indicates that M of InAs NW does not change enormously in the diameter range of 7 nm to 16 nm. Considering M should not change with the contact metal, the difference of the contact resistances between the Cr contact and Ni contact cases should mainly come from the difference of ρc and Rsh between the two cases. When Ni is used as the contact metal, it would diffuse into the InAs NW contacting it, and part of the NW under the metal would transform into NixInAs through an alloying reaction during annealing [33, 34]. In the present case, to avoid Ni diffusing into the channel, we do not intentionally anneal the devices except keeping them at 90 °C for 4 h during the ALD process; therefore, the NW under the Ni electrodes could only partially transform into NixInAs. Nevertheless, such interaction between Ni and InAs could cause the difference of ρc and Rsh between the Ni-contact and 4
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Figure 3. (a) Transfer curves of transistors based on the same individual NW with varied channel length of 50, 110, 180, and 330 nm. Cr is used as contact metal. The dots are measured data while lines are fitted values. (b) The dependence of the on-state resistances on the channel length of Cr-contacted transistors. The values for the 12 nm-thick NW are obtained from (a). (c) The dependence of the on-state resistances on the channel length of Ni-contacted transistors for two NWs. (d) The contact resistances change with the NW diameters for both Cr and Ni as contact metals.
Figure 4. (a) Schematic view of the metal–InAs NW contact. (b) The normalized resistances of InAs and NixInAs NWs as a function of NW
diameter.
such obtained channel resistances are the resistances of the InAs NWs themselves, excluding the effect of the contact resistance. To obtain Rch of NixInAs NWs, we intentionally fabricate the NixInAs NWs channel by further annealing some Ni-contacted InAs NW FETs at 250 °C for 6 min. After annealing, the S/D current shows no gate voltage dependence (supporting information S3), which indicates that all of the InAs NWs have transformed into NixInAs NWs according to a previous publication [33]. Rch of NixInAs NW is then deduced by the same method as that of InAs NW. As shown
Cr-contact cases. To evaluate the difference between InAs and NixInAs, the resistances of the two NWs are obtained. The normalized channel resistances of InAs NW, Rch, are extracted from figures 3(b) or (c), as the slope of the normalized on-state resistance versus channel length lines, i.e. Rch is normalized by dividing the absolute resistance by the channel length L and also multiplying it with the perimeter of the NWs, considering that the current transports in the surface layer of the NWs. The results for the Cr contact and Ni contact are roughly the same, as shown in figure 4(b), because 5
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in figure 4(b), the resistances of NixInAs NWs are much smaller than those of InAs NWs with the same diameter. Therefore, it is understandable that Rsh of the NW under the Ni electrode is smaller than that of the NW under the Cr electrode. This could explain why Ni has a smaller contact resistance with the ultrathin InAs NW than Cr, based on equation (2). A previous report has shown that the alloying speed between silicon NW and Ni is slower for thicker NWs [35]. We also observe similar phenomena for InAs NWs. Therefore, for thick NWs, the difference between Rsh of the NWs under Ni and that under Cr is small. As a result, the difference of the contact resistances for thick NWs is small, thus explaining our results in figure 3(d). In conclusion, we have investigated the contact properties of Ni and Cr with ultrathin wurtzite-structured InAs NWs with diameter ranging from 16 nm to sub-7 nm. Both metals are proven to form ohmic contact with the ultrathin InAs NWs. Contact resistances obtained by TLM show a strong dependence on contact metals and the NW diameter. Although Cr and Ni show roughly the same contact resistance for the NWs with diameter 15–16 nm, the contact resistance between Cr and InAs NWs increases more rapidly than that between Ni and InAs NWs when the NWs diameter decreases. The origins of the contact resistance difference for the two kinds of metals are investigated and NixInAs alloy is believed to play an important role. Based on our results, it is advantageous to use Ni as a contact metal for ultrathin NWs. We also observe that the FETs are still working in the diffusive regime even when the channel length is scaled down to 50 nm.
[6] Lu W, Xiang J, Timko B P, Wu Y and Lieber C M 2005 Onedimensional hole gas in germanium/silicon nanowire heterostructures Proc. Natl Acad. Sci. USA 102 10046–51 [7] Tomioka K, Yoshimura M and Fukui T 2012 A III-V nanowire channel on silicon for high-performance vertical transistors Nature 488 189–92 [8] Moselund K E, Schmid H, Bessire C, Björk M T, Ghoneim H and Riel H 2012 InAs–Si nanowire heterojunction tunnel FETs IEEE Electron Device Lett. 33 1453–5 [9] Tomioka K and Fukui T 2011 Tunnel field-effect transistor using InAs nanowire/si heterojunction Appl. Phys. Lett. 98 083114 [10] Egard M, Johansson S, Johansson A C, Persson K M, Dey A W, Borg B M, Thelander C, Wernersson L E and Lind E 2010 Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz Nano Lett. 10 809–12 [11] Johansson S, Memisevic E, Wernersson L E and Lind E 2014 High-Frequency gate-all-around vertical InAs nanowire MOSFETs on Si substrates IEEE Electron Device Lett. 35 518–20 [12] Dey A W, Thelander C, Lind E, Dick K A, Borg B M, Borgström M, Nilsson P and Wernersson L E 2012 Highperformance InAs nanowire MOSFETs IEEE Electron Device Lett. 33 791–3 [13] Liu Z, Luo T, Liang B, Chen G, Yu G, Xie X M, Chen D and Shen G Z 2013 High-detectivity InAs nanowire photodetectors with spectral response from ultraviolet to near-infrared Nano Res. 6 775–83 [14] Miao J S et al 2014 Single InAs nanowire room temperature near-infrared photodetectors ACS Nano 8 3628–35 [15] Chuang S, Gao Q, Kapadia R, Ford A C, Guo J and Javey A 2013 Ballistic InAs nanowire transistors Nano Lett. 13 555–8 [16] Scheffler M, Nadj-Perge S, Kouwenhoven L P, Borgström M T and Bakkers E P A M 2009 Diameterdependent conductance of InAs nanowires J. Appl. Phys. 106 124303 [17] Ford A C, Ho J C, Chueh Y L, Tseng Y C, Fan Z Y, Guo J, Bokor J and Javey A 2009 Diameter-dependent electron mobility of InAs nanowires Nano Lett. 9 360–5 [18] Dayeh S A, Susac D, Kavanagh K L, Yu E T and Wang D 2008 Field dependent transport properties in InAs nanowire field effect transistors Nano Lett. 8 3114–9 [19] Ford A C, Kumar S B, Kapadia R, Guo J and Javey A 2012 Observation of degenerate one-dimensional sub-bands in cylindrical InAs nanowires Nano Lett. 12 1340–3 [20] Fu M Q, Pan D, Yang Y J, Shi T W, Zhang Z Y, Zhao J H, Xu H Q and Chen Q 2014 Electrical characteristics of fieldeffect transistors based on indium arsenide nanowire thinner than 10 nm Appl. Phys. Lett. 105 143101 [21] Razavieh A, Mohseni P K, Jung K, Mehrotra S, Das S, Suslov S, Li X, Klimeck G, Janes D B and Appenzeller J 2014 Effect of diameter variation on electrical characteristics of schottky barrier indium arsenide nanowire field-effect transistors ACS Nano 8 6281–7 [22] Pan D et al 2014 Controlled synthesis of phase-pure InAs nanowires on Si(111) by diminishing the diameter to 10 nm Nano Lett. 14 1214–20 [23] Das S, Chen H Y, Penumatcha A V and Appenzeller J 2013 High performance multilayer MoS2 transistors with scandium contacts Nano Lett. 13 100–5 [24] Appenzeller J, Radosavljević M, Knoch J and Avouris P 2004 Tunneling versus thermionic emission in one-dimensional semiconductors Phys. Rev. Lett. 92 048301 [25] Sarker B K and Khondaker S I 2012 Thermionic emission and tunneling at carbon nanotube-organic semiconductor interface ACS Nano 6 4993–9
Acknowledgments We thank Dr S Gao for his assistance with AFM measurements. This work was supported by the MOST (Nos. 2012CB932702 and 2012CB932701) and NSF (Nos. 11374022 and 61321001) of China.
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[32] Lind E, Persson M P, Niquet Y M and Wernersson L E 2009 Band Structure Effects on the Scaling Properties of [111] InAs Nanowire MOSFETs IEEE Trans. Electron Devices 56 201–5 [33] Chueh Y L, Ford A C, Ho J C, Jacobson Z A, Fan Z Y, Chen C Y, Chou L J and Javey A 2008 Formation and characterization of NixInAs/InAs nanowire heterostructures by solid source reaction Nano Lett. 8 4528–33 [34] Oxland R et al 2012 An ultralow-resistance ultrashallow metallic source/drain contact scheme for III–V NMOS IEEE Electron Device Lett. 33 501–3 [35] Appenzeller J, Knoch J, Tutuc E, Reuter M and Guha S 2006 Dual-gate silicon nanowire transistors with nickel silicide contacts 2006 IEEE Int. Electron Devices Meeting vol 1-2 pp 302–5
[26] Takei K et al 2011 Quantum confinement effects in nanoscalethickness InAs membranes Nano Lett. 11 5008–12 [27] Franklin A D and Chen Z H 2010 Length scaling of carbon nanotube transistors Nat. Nanotechnology 5 858–62 [28] Schroder D K 1998 Semiconductor Material and Device Characterization (New York: Wiley) [29] Guo Y, Han Y X, Li J P, Xiang A, Wei X L, Gao S and Chen Q 2014 Study on the resistance distribution at the contact between molybdenum disulfide and metals ACS Nano 8 7771–9 [30] Xia F N, Perebeinos V, Lin Y M, Wu Y Q and Avouris P 2011 The origins and limits of metal-graphene junction resistance Nat. Nanotechnology 6 179–84 [31] Datta S 2001 Electronic Transport in Mesoscopic Systems (Cambridge: Cambridge University Press)
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Contact properties of field-effect transistors based on indium arsenide nanowires thinner than 16 nm
This content has been downloaded from IOPscience. Please scroll down to see the full text. 2015 Nanotechnology 26 175202 (http://iopscience.iop.org/0957-4484/26/17/175202) View the table of contents for this issue, or go to the journal homepage for more
Download details: IP Address: 157.182.150.22 This content was downloaded on 17/04/2015 at 07:53
Please note that terms and conditions apply.
Nanotechnology Nanotechnology 26 (2015) 175202 (7pp)
doi:10.1088/0957-4484/26/17/175202
Contact properties of field-effect transistors based on indium arsenide nanowires thinner than 16nm Tuanwei Shi1, Mengqi Fu1, Dong Pan2, Yao Guo1, Jianhua Zhao2 and Qing Chen1 1
Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, Beijing 100871, People’s Republic of China 2 State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, People’s Republic of China E-mail: [email protected] Received 6 February 2015, revised 10 March 2015 Accepted for publication 16 March 2015 Published 9 April 2015 Abstract
With the scaling down of field effect transistors (FETs) to improve performance, the contact between the electrodes and the channel becomes more and more important. Contact properties of FETs based on ultrathin InAs NWs (with the diameter ranging from sub-7 nm to 16 nm) are investigated here. Chromium (Cr) and nickel (Ni) are proven to form ohmic contact with the ultrathin InAs NWs, in contrast to a recent report (Razavieh A et al ACS Nano 8 6281). Furthermore, the contact resistance is found to depend on the NW diameter and the contact metals, which between Cr and InAs NWs increases more rapidly than that between Ni and InAs NWs when the NW diameter decreases. The origins of the contact resistance difference for the two kinds of metals are studied and NixInAs is believed to play an important role. Based on our results, it is advantageous to use Ni as contact metal for ultrathin NWs. We also observe that the FETs are still working in the diffusive regime even when the channel length is scaled down to 50 nm. S Online supplementary data available from stacks.iop.org/NANO/26/175202/mmedia Keywords: InAs nanowire, FET, contact properties, scaling down (Some figures may appear in colour only in the online journal) As the scaling down of metal–oxide–semiconductor (MOS) field effect transistor (FET) continues, device performance, especially gate control efficiency, begins to decline due to short-channel effect (SCE). As a result, nanowires (NWs) draw wide research interest due to their natural advantages in fabricating wrap gate transistors, which have the highest gate control efficiency and therefore avoid SCE. In addition, it is possible for NWs to combine materials with large lattice mismatch because of efficient strain relaxation [1–6]. Of all the NWs, InAs NW in particular is considered to be one of the most promising materials, due to its high electron mobility, high injection velocity, small band gap, and ease of forming ohmic contact with metals because of the surface Fermi-level pinning in the conduction band. So far, InAs NWs have been 0957-4484/15/175202+07$33.00
demonstrated to have great potential in NMOS, RF-transistors, tunnel FET, photodetectors, etc [3, 7–14]. To further enhance device performance, scaling down the InAs NW transistors is strongly needed. Shorter channels bring in higher on-state current and transconductance, due to less scattering for the carriers [15]. At the same time, to keep a constant gate efficiency, the NW diameter should be scaled down with the channel-length scaling. However, so far, most of the InAs NW transistors being studied are based on thick NWs with diameters larger than 15 nm [1, 12, 15–19]. Recently, we have reported enhancement-mode FETs with up to 108 on-off ratio based on InAs NWs thinner than 10 nm, demonstrating the potential for scaling down InAs NW FETs [20]. However, although bulk InAs is well known to form 1
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ohmic contact with metals, a recent work has reported a Schottky barrier between Ni and InAs NWs independent of the NW diameter down to 10 nm [21]. Considering the vital importance of the contact resistance in short-channel FETs, we here study the contact properties of the FETs based on ultrathin InAs NWs with diameters ranging from sub-7 nm to 16 nm. Nickel (Ni), chromium (Cr), and titanium (Ti) are investigated here as contact metals; these are normally used as S/D electrodes in InAs NW transistors [10, 14, 15]. We prove that it is still ohmic contact between ultrathin InAs NWs and metal Ni or Cr by temperature-dependent measurement. By studying the transistors with varied channel lengths on the same individual InAs NWs, we show that the contact resistances have a dependence on the NW diameters and the contact metals. We also observe that the devices are still working in the diffusive regime even when the channel length is scaled down to 50 nm. The InAs NWs used in this study were grown on n-type Si (111) wafer by molecular-beam epitaxy (MBE) using Ag as the catalyst with the conventional one-step catalyst annealing process without intentional doping [22]. The ultrathin NWs (with diameter ranging from sub-7 nm to 16 nm) were selected for device fabrication and they have a wurtzite crystal structure, with their axis along 〈0001〉, free of stacking faults and twins (as shown in supporting information S1). The NWs were first transferred onto a 300 nm-thick SiO2-covered Si substrate through ethanol solution and then located by scanning electron microscopy (SEM). The source and drain (S/D) electrodes, Cr/Au (20/20 nm) or Ni (30 nm) with the width of 200 nm, were defined by electron beam lithography (EBL) and deposited by electron beam evaporation (EBE). The 1.5 nm thick native oxide outside the NWs was removed by the NH4Sx solution just before the S/D metal deposition, so that the metal could contact the NW directly at the electrode area. Besides Cr/Au and Ni, we also studied Ti/ Au (20/50 nm) as S/D electrodes, but found that the S/D current is about the same level as the noise as detected by Keithley 4200 when the InAs NW was thinner than 10 nm. We therefore conclude that Ti/Au cannot form good electrical contact with the InAs NWs thinner than 10 nm. The gate dielectric is a 10 nm thick HfO2 layer grown by atomic layer deposition (ALD) at 90 °C using tetrakis(dimethylamido) hafnium (Hf[(CH3)2N]4) and H2O as precursors. Metal film Ti/Au (20/50 nm) deposited by EBE is used as the gate electrode. The diameters of the NWs were measured by atomic force microscopy (AFM) (as shown in supporting information S2), subtracting the thickness of the oxide, while the channel length was measured by SEM. Multiple S/D contact electrodes were defined with varied spacing on the same individual NWs to fabricate FETs with varied channel length, Lch, as shown in figures 1(a) and (b). The top-gate electrode and the dielectric layer overlap the whole channels and the contact electrodes to obtain effective gate control over the channels and to avoid parasitic resistances of the ungated region. To avoid Ni diffusing into the InAs NW channel, the devices have not been intentionally annealed except keeping at 90 °C for 4 h in N2 during the growth of HfO2 by ALD.
Figures 1(c) and (d) show the output and transfer curves of a typical short-channel InAs NW transistor, with Cr/Au as S/D electrode. The channel length of this transistor is 50 nm and the NW diameter is 12 nm. The normalized on-state current at Vg = 0.8 V of this transistor is over 100 μA μm−1 (normalized by perimeter), which could be further promoted by doping the NWs, considering that the present NWs were grown by MBE without doping, which causes low density of carriers, and as a result large contact and channel resistances. The transfer curves in figure 1(d) show that the Ion/Ioff ratio of the device is over 103 at both Vds = 0.01 V and 0.5 V, which is comparable to the long-channel transistors reported previously [1, 12]. It is well known that InAs easily forms ohmic contact with metals because of the surface Fermi-level pinning near the bottom of the conduction band, which has been confirmed by many works in which the on-state current keeps constant or decreases as the temperature increases [15, 17, 19]. However, a recent work reported a Schottky barrier between Ni and InAs NWs grown by metal–organic chemical vapor deposition (MOCVD) independent of the NW diameter down to 10 nm [21]. Here, we study the properties of the contact between metals (both Cr and Ni) and the ultrathin InAs NWs grown by MBE, through measurements at different temperature similar to what has been reported in the literature [21, 23–25]. FETs with relatively long channels are used here to avoid the SCE on the potential profile and possible contact barrier, and so to get an accurate contact barrier height, if one exists. Figures 2(a)–(d) show the results of a representative device with Cr as S/D electrodes. In this device, the diameter of the NW is 12 nm and the channel length is 330 nm. The transfer curves measured at varied temperatures show that in the subthreshold region (Vg < Vth), the current increases with the temperature, as shown in figure 2(a). The conduction band of the InAs NW in the channel region is lifted by applying a negative gate voltage, which brings a barrier between the source and the channel. The primary conduction mechanism for electrons is thermionic emission over the barrier, so that more electrons will overcome the barrier as the temperature increases. On the other hand, in the on-state region (Vg > Vth), as shown in figure 2(b), the current keeps roughly the same first and then decreases as the temperature increases to 260 K, which excludes the existence of a barrier. The reason for the decreasing current at 260 K is probably due to the increased scattering at higher temperature. To quantitatively investigate the contact, the corresponding Arrhenius plots are drawn for various Vg in figure 2(c). The barrier height between source and channel ΦB can be extracted from the conventional thermionic equation [21, 23–25]: Ids = A*T 2 exp −( qΦB ) / ( k B T ) ⎡⎣ 1 − exp −( qVds ) / ( k B T ) ⎤⎦
(
)
(
)
(1)
where A* is the Richardson's constant, kB is the Boltzmann constant, q is the charge of an electron, and T is the temperature. As Vds here is 0.5 V, the part in the square 2
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Figure 1. (a) Cross-sectional schematic of the top-gate MOSFETs with varied channel length based on the same individual InAs NW. (b)
Top-view SEM image of a typical device. (c) The output curves of a typical short channel MOSFET with the NW diameter of 12 nm and the channel length of 50 nm, Cr/Au as S/D electrode. (d) The transfer curves of the same transistor in (c) measured at Vds = 0.01 V and 0.5 V.
Figure 2. (a) Transfer curves of a typical Cr-contacted MOSFET measured at varied temperatures from 120 K to 260 K in an exponential
coordinate. (b) The same curves as (a) in a linear coordinate. (c) Arrhenius plots of (a) for various gate voltages. (d) Barrier height of the Crcontacted device extracted from (c) showing ohmic contact at the on-state. (e) Barrier height of a Ni-contacted device.
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brackets, 1 − exp(−(qVds)/(kBT), is approximately equal to 1 and the barrier at the drain side is cleared. The barrier height ΦB can then be extracted from the linear relationship between ln(Ids/T2) and 1/T at high-temperature region (T > 160 K), the results of which are shown in figure 2(d). In the subthreshold region (Vg < Vth), the effective barrier height ΦB linearly responds to the gate voltage Vg when near Vth. This is because the thermionic emission is the main conduction mechanism. Flat band voltage VFB is extracted from the end of the linear relationship [23]. In the case shown in figure 2(d), VFB is very close to Vth, and ΦB is near and smaller than zero. As the gate voltage increases further to the on-state region, the barrier height remains negative, indicating there is no barrier between the metal electrodes and the channel, i.e. ohmic contact between Cr and the ultrathin InAs NWs. The same results are obtained for the transistors with Ni contact, as shown in figure 2(e), where the NW diameter is 13.5 nm and the channel length is 410 nm. All the transistors we measured at varied temperature, including four with Cr contact electrodes and four with Ni contact electrodes, show the same results, proving that the contact between the Ni or Cr metal electrodes and the ultrathin InAs NWs grown by MBE is still ohmic contact in contrast to the recent report [21]. The different contact properties could be caused by two reasons. First, the present nanowires were grown by MBE instead of the MOCVD used in the previous report. Second, we use NH4Sx solution to remove the native oxide and passivate the surface of the nanowires, while BOE was used in [21]. To study the contact resistance Rc, the transistors with varied channel lengths on the same individual NWs are fabricated and studied. Figure 3(a) shows the low-field (Vds = 0.01 V) transfer characteristics of a 12 nm thick InAs NW device with Cr as the contact metal, measured at room temperature. With the scaling down of the channel length from 330 nm to 50 nm, the on-state current at the same gate voltage increases, showing the advantage of the scaling down of the channel length. The normalized on-state resistance Ron (normalized by perimeter) is obtained by dividing the drain voltage (Vds = 0.01 V) by the normalized drain current (the fitted values) at Vg − Vth = 1 V, where the transconductance gm is near the peak value. As shown in figures 3(b) and (c), the onstate resistance of the same NW depends roughly linearly on the channel length, indicating that the transistors are still operating in the diffusive regime even when the channel length is scaled down to 50 nm, which means that the lowfield mean-free path λ is smaller than 50 nm. The relatively small λ is probably due to the large surface scattering, considering the large surface/volume ratio for the ultrathin NWs. Also shown in figures 3(b) and (c), the normalized on-state resistance is larger for thinner NW when the channel length is the same, which is consistent with our previous report on the long-channel transistors [20]. The on-state resistance is mainly composed of the contact resistance and the channel resistance. The normalized contact resistance Rc is extracted by transmission line method (TLM) [26], and the value is the half of the y intercept of the normalized on-state resistance versus channel length plots. The
obtained Rc both for Cr and Ni as contact metals is plotted in figure 3(d) as a function of the NW diameter. For the Crcontacted transistors, Rc increases fast with the scaling down of the diameter, increasing about 6 times when the diameter decreases from 16 nm to 6 nm. However, for the Ni-contacted transistors, Rc changes slowly, just increasing around two times when the NWs diameter decreases from 16 nm to 7 nm. Therefore, for NWs of diameters smaller than 15 nm, the contact resistance between Cr and InAs NWs is higher than that between Ni and InAs NWs. The smaller of the NW diameter, the larger differences of Rc. However, for 15 nm to 16 nm thick NWs, Rc is about the same for the two contact metals. Based on our results, it is advantageous to use Ni as contact metal for NWs with diameters smaller than 15 nm. For the NWs with diameter 15–16 nm, the choice of contact metals is not so important. The contact resistance Rc between metal and InAs NW is the sum of two parts: Ruc which is the resistance of the metal and the NW under the metal, and the quantum resistance RQ [15, 27]. Considering that the low-field mean-free path λ is relatively short, Ruc could be described by conventional metal–semiconductor contact model, as shown in figure 4(a) [28–30]. The quantum resistance RQ is a function of the number of the conduction modes in the channel M [30, 31]. The normalized total resistance Rc could be expressed as 2R c = 2R uc + R Q πD = 2 ρc Rsh +
h πD 2e2 M
(2)
where ρc is the contact resistivity between the metal and the NW contacting it (the unit is Ω·μm2), Rsh is the resistance of the NW under the metal, D is the NW diameter, e is electron charge, and h is the Planck’s constant. The effect of the contact electrode length is not discussed here, considering that the present contact length is relatively long (200 nm). Previous calculation and experimental results have shown that as the diameter of InAs NWs decreases in the range of sub-25 nm, the band gap and subband separation increases due to quantum confinement effect, which brings a reduction in the number of transport modes [19, 26, 32]. This explains the rising of the contact resistance when the NW diameter decreases both for Ni and Cr as the contact metal, as shown in figure 3(d). The slow increase of Ni contact resistance indicates that M of InAs NW does not change enormously in the diameter range of 7 nm to 16 nm. Considering M should not change with the contact metal, the difference of the contact resistances between the Cr contact and Ni contact cases should mainly come from the difference of ρc and Rsh between the two cases. When Ni is used as the contact metal, it would diffuse into the InAs NW contacting it, and part of the NW under the metal would transform into NixInAs through an alloying reaction during annealing [33, 34]. In the present case, to avoid Ni diffusing into the channel, we do not intentionally anneal the devices except keeping them at 90 °C for 4 h during the ALD process; therefore, the NW under the Ni electrodes could only partially transform into NixInAs. Nevertheless, such interaction between Ni and InAs could cause the difference of ρc and Rsh between the Ni-contact and 4
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Figure 3. (a) Transfer curves of transistors based on the same individual NW with varied channel length of 50, 110, 180, and 330 nm. Cr is used as contact metal. The dots are measured data while lines are fitted values. (b) The dependence of the on-state resistances on the channel length of Cr-contacted transistors. The values for the 12 nm-thick NW are obtained from (a). (c) The dependence of the on-state resistances on the channel length of Ni-contacted transistors for two NWs. (d) The contact resistances change with the NW diameters for both Cr and Ni as contact metals.
Figure 4. (a) Schematic view of the metal–InAs NW contact. (b) The normalized resistances of InAs and NixInAs NWs as a function of NW
diameter.
such obtained channel resistances are the resistances of the InAs NWs themselves, excluding the effect of the contact resistance. To obtain Rch of NixInAs NWs, we intentionally fabricate the NixInAs NWs channel by further annealing some Ni-contacted InAs NW FETs at 250 °C for 6 min. After annealing, the S/D current shows no gate voltage dependence (supporting information S3), which indicates that all of the InAs NWs have transformed into NixInAs NWs according to a previous publication [33]. Rch of NixInAs NW is then deduced by the same method as that of InAs NW. As shown
Cr-contact cases. To evaluate the difference between InAs and NixInAs, the resistances of the two NWs are obtained. The normalized channel resistances of InAs NW, Rch, are extracted from figures 3(b) or (c), as the slope of the normalized on-state resistance versus channel length lines, i.e. Rch is normalized by dividing the absolute resistance by the channel length L and also multiplying it with the perimeter of the NWs, considering that the current transports in the surface layer of the NWs. The results for the Cr contact and Ni contact are roughly the same, as shown in figure 4(b), because 5
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in figure 4(b), the resistances of NixInAs NWs are much smaller than those of InAs NWs with the same diameter. Therefore, it is understandable that Rsh of the NW under the Ni electrode is smaller than that of the NW under the Cr electrode. This could explain why Ni has a smaller contact resistance with the ultrathin InAs NW than Cr, based on equation (2). A previous report has shown that the alloying speed between silicon NW and Ni is slower for thicker NWs [35]. We also observe similar phenomena for InAs NWs. Therefore, for thick NWs, the difference between Rsh of the NWs under Ni and that under Cr is small. As a result, the difference of the contact resistances for thick NWs is small, thus explaining our results in figure 3(d). In conclusion, we have investigated the contact properties of Ni and Cr with ultrathin wurtzite-structured InAs NWs with diameter ranging from 16 nm to sub-7 nm. Both metals are proven to form ohmic contact with the ultrathin InAs NWs. Contact resistances obtained by TLM show a strong dependence on contact metals and the NW diameter. Although Cr and Ni show roughly the same contact resistance for the NWs with diameter 15–16 nm, the contact resistance between Cr and InAs NWs increases more rapidly than that between Ni and InAs NWs when the NWs diameter decreases. The origins of the contact resistance difference for the two kinds of metals are investigated and NixInAs alloy is believed to play an important role. Based on our results, it is advantageous to use Ni as a contact metal for ultrathin NWs. We also observe that the FETs are still working in the diffusive regime even when the channel length is scaled down to 50 nm.
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Acknowledgments We thank Dr S Gao for his assistance with AFM measurements. This work was supported by the MOST (Nos. 2012CB932702 and 2012CB932701) and NSF (Nos. 11374022 and 61321001) of China.
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