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Cite this: Nanoscale, 2014, 6, 13446 Received 17th July 2014, Accepted 17th September 2014 DOI: 10.1039/c4nr04047c

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Confinement-modulated junctionless nanowire transistors for logic circuits François Vaurette,* Renaud Leturcq,† Sylvie Lepilliet, Bruno Grandidier and Didier Stiévenard

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We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of the current in the nanowire. The constrictions act as potential barriers and the height of the barriers can be selectively tuned by gates, making the device concept compatible with the crossbar geometry in order to create logic circuits. The functionality of the architecture and the reliability of the fabrication process are demonstrated by designing decoder devices.

The search for improved electrostatic control in field effect transistors (FETs) and higher device densities is driving the exploration of semiconductor nanowire (NW) architectures. Stunning examples of memory and logic circuits have been demonstrated by silicon NW arrays, fabricated either by topdown or bottom-up approaches.1–6 With the advent of junctionless transistors, where the current flows through the whole wire section, the electrical performances of NW-FETs have been further improved.7–9 In contrast to conventional FETs, the junctionless transistor offers the advantage to be turned off when the channel is depleted by the gate-induced electric field. But in order to ensure a large on/off current ratio, full depletion is required. This effect can only be achieved with thin and narrow channels and, when used in a crossbar circuit, such a small channel is likely to be inadvertently switched by parallel crossing gates, making the devices unstable. Here, we adopt a novel strategy to address the silicon channel of junctionless transistors that is compatible with a selective switch of the channel from its respective inputs only. Based on the benefits provided by the structure of the junctionless transistors that avoid junction doping and thus are manufactured with a limited number of technological steps, we built NW-FETs with bulk-like properties, except in nanoscale portions of the wire, where constrictions are obtained by

Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN), CNRS, UMR 8520, Avenue Poincaré - B.P. 60069, 59652 Villeneuve d’Ascq, France. E-mail: [email protected] † Present Address: CRP Gabriel Lippmann, Département Science et Analyse des Matériaux, 41, rue du Brill - 4422 Belvaux – Luxembourg.

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Fig. 1 Electrical impact of a constriction in a highly-doped Si NW. (a) 3D-tapping-mode AFM image of an etched silicon NW. Inset, height profile along the NW. (b) Etching depth vs. etching time for times ranging from 10 to 50 seconds and the corresponding theoretical barrier height estimated from Ref. 10. (c) I(V) curves for different etching times (10 s to 40 s). Inset: drain current displayed on a log scale for a drain voltage between 1 V and 2 V.

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etching. These constrictions act as potential barriers that are used to modulate the NW conductivity when a metallic top gate is deposited on top, after dielectric isolation. Because the rest of the NW has a much wider cross-section, it is electrostatically immune to additional perpendicular interconnect lines, allowing us to address a large number of NWs with a relatively small number of interconnect metallic lines. The samples were fabricated by electron-beam lithography, reactive-ion etching (RIE) and metal evaporation on SOI substrates. The top silicon layer is intentionally n-type As-doped with a concentration of 9 × 1019 cm−3. Its thickness (17.7 ± 1.4 nm) was carefully measured using the ellipsometry technique. Further etching of the silicon top layer by more than 10 nm should result in a thickness range, where quantum confinement leads to a sizable increase of the band-gap energy.10,11 When achieved on a local scale, this local increase

of the band-gap energy acts as a localized potential barrier for the charge carriers.12,13 To demonstrate the formation of such a local potential barrier, the resist layer on top of 23 nm-wide NWs was first opened to locally etch the NWs, as shown in Fig. 1a. Based on the height profiles measured by atomic force microscopy (AFM) over a wide range of etching times, from 10 seconds to 50 seconds, a reproducible etching rate of 3 Å s−1 has been obtained (see Fig. 1b). Thus, such constrictions correspond to potential barriers with a height that varies between 13 meV and 460 meV within the studied range of etching times, as calculated in the theoretical work of ref. 10. From the four contacts fabricated at the end of each wire that are shown in Fig. 1a, I–V characteristics were subsequently measured (Fig. 1c). The characteristic behavior changes from a linear regime to a non-linear regime as the etching time increases, consistent with a NW thickness decrease that involves the creation of a higher and higher potential barrier in the NW. In this figure, the first three curves (10, 20 and 25 s etching time) are linear because the barrier height is smaller or of the order of the thermal fluctuations at room temperature. By decreasing the thickness of the constriction, the barrier height becomes higher than 25 meV and a non-linear curve appears. In order to measure the barrier height, we performed I(V) measurements from 100 K to 300 K, in a four-point probe arrangement that eliminates the contribution of the contact resistance. Fig. 2 shows measurements obtained on a NW,

Fig. 2 Barrier height determination for the constriction. (a) Four-point probe ISD(V4p) measurements acquired for different temperatures ranging from 300 K down to 100 K. (b) Corresponding Arrhenius plot of the conductance. The linear fit yields a slope of 77 ± 2 meV. (c) Roomtemperature drain current versus gate voltage at a drain voltage of 1 V for a Si NW with a gated constriction.

Fig. 3 Selective control of depletion in a dual-gated NW. (a) Schematic of a highly doped Si NW gated with electrodes, one being positioned above a constriction. The corresponding potential variation along the wire. (b) Drain current versus gate voltage at a drain voltage of 1 V. Gate 1 can turn on and off the current, whereas gate 2 has no influence on the current.

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where the thickness of the etched portion was 7 nm (etching time of 35 seconds), corresponding to a predicted potential barrier on the order of 50–60 meV.10 This barrier causes the non-linear characteristics observed in Fig. 2a, the decrease of the temperature affecting the intensity of the current as well as the width of the voltage range for which the current is zero. Given the geometry of the barrier, transport should be dominated by thermionic emission, where the conductance has the following temperature-dependence in the linear regime:14 GTE ¼

  I TE AqT qφBn exp  ¼ ; kB V kB T

ð1Þ

with A is a fitting parameter, q is the carrier charge, T is the absolute temperature, kB is the Boltzmann constant and φBn is the barrier height. To obtain the conductance, we fit the curves over the full range of the applied voltage by a

polynomial equation and take the linear part of it. As shown in Fig. 2b, the analysis of the conductance as a function of the temperature in an Arrhenius plot yields a barrier height of 77 ± 2 meV, which is consistent with the above predicted barrier height. This barrier can be further modulated when a gate is positioned on top of the etched portion and separated with 30 nm of SiO2 from the Si NW. As an example, Fig. 2c shows the drain current versus the gate voltage for a drain voltage of 1 V on another NW. Applying a negative voltage on the gate effectively depletes the NW at the location of the etched portion and allows to reach an on/off current ratio that exceeds 106 when the gate voltage varies between −5 V and 5 V. In order to prove that the rest of the NW is electrostatically immune, an additional gate (gate 2) was fabricated on top of a portion that was not etched, as shown in Fig. 3. The I(V) characteristics definitively show that the second gate has no action on the current intensity when the device is turned ON with 5 V on gate 1, whatever the gate voltage. Therefore, a NW can only be addressed at the position

Fig. 4 Basic logic gates: NAND and NOR gates. (a) AFM image of the NAND structure. Inset, contrast image to highlight the precise alignment between the constrictions and the interconnect line. (b) Output voltage versus time of the NAND function with a supply voltage of 2 V and a load resistance of 10 MΩ and the equivalent circuit schematic. (c) AFM image of the NOR structure: 2 NWs with 1 constriction on each NW connected with two perpendicular interconnect lines. (d) Output voltage versus time for the NOR gate with a supply voltage of 2 V and a load resistance of 10 MΩ and the equivalent circuit schematic. For each logic, the output signal amplitude is indicated in the truth table.

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Fig. 5 2 by 2 (left side) and 4 by 6 (right side) decoders. (a) Layout of the devices and equivalent circuit schematics. (b) 3D AFM and SEM images showing the devices after the local etching step. (c) 3D AFM images of the connected structures. (d) Output voltage versus time with a supply voltage of 2 V and a load resistance of 10 MΩ. Inputs 1 and 2 correspond to the couples of gates which have an electrostatic effect on the conduction of a given NW, the NW being immuned to the other two gates.

of a constriction. Such a localized effect precludes any significant conductance modulation from unmodified regions of the NW. We have extended this approach to fabricate two basic logic gates capable of operating a NAND and a NOR function (Fig. 4). One NW with two constrictions topped with two gates was designed to test the NAND function, whereas the NOR gate required two NWs, each one having one constriction. Since, for this function, the interconnect lines are perpendicular to the NWs, they overlap the NWs in a section that have not been etched and should thus leave the channel unaffected. AFM images of both devices are shown in Fig. 4a and c respectively. The enhanced color contrast of the inset in Fig. 4a shows the very high quality of the alignment between the different process steps. In order to test both functions, a supply voltage of 2 V was used with a load resistance of 10 MΩ. The gate

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voltages at the inputs were set to −5 V for low voltage (logic 0) and +5 V for high voltage (logic 1). In the NAND device, the output is low only when both inputs are high (see the truth table in Fig. 4b). Conversely, for the NOR device (Fig. 4d), the output is low when either one or both of the inputs are high. The output range is the same as that of the input, showing full signal restoration. Finally, we fabricated 2 by 2 and 4 by 6 decoders (Fig. 5). For the 2 by 2 decoder, two top gates are used as inputs and can selectively command the two NWs configured as outputs (the left side of Fig. 5). For the 4 by 6 decoder, two inputs are required to command one NW transistor, i.e. four inputs can command six NWs (the right side of Fig. 5). This is achieved by etching two local constrictions on each NW, as shown in Fig. 5a (right side). It means that two inputs above the local constrictions need to be high to get the corresponding NW low

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(2-hot code), as described by the different process steps shown in Fig. 5. The logic operations were performed with a supply voltage of 2 V and a load resistance of 10 MΩ. The output voltage signals were measured sequentially. As shown in Fig. 5d, the outputs can be selectively turned off by the inputs. These devices thus work as address decoder circuits for multiplexing and demultiplexing signals. We note that the output transitions are slow due to the large area defined by the contact pads (200 μm × 200 μm) and the high density of interfacial defects that could be reduced upon further optimization of the structure geometry.

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this concept fully compatible for more complex crossbar circuits than the 2 by 2 and 4 by 6 decoders achieved in this work.

Acknowledgements This work was partly supported by DGA (Délégation Générale à l’Armement) under contract REI 05 34 048 and partly by the FUPL (Fédération Universitaire et Polytechnique de Lille). We thank J. Gautier (CEA-LETI) for providing us with the SOI wafers and Renatech (the French Network of major Technology Central).

Experimental section Silicon NWs were fabricated by electron-beam lithography (EBPG 5000 Plus, Vistec) with a XR1541 resist (Microchem, Hydrogen Silsesquioxane resist) and by development with a TMAH 25% solution (tetra methyl ammonium hydroxide). The thickness of the resist was 40 nm, which is sufficient to protect the silicon layer during the RIE process with a SF6/N2/O2 plasma. The NWs were then connected with evaporated metallic contacts, consisting of a 50 nm-thick titanium layer covered with 100 nm of gold. The constrictions were obtained by locally etching the silicon NWs. 100 nm of PMMA 4% 950 K was first spin-coated on the sample. Areas were then opened in the PMMA film above the NWs. The RIE process with a CHF3/CF4 plasma was used to reduce the height of the NWs down to 5–7 nm. For logic gate applications, we used NWs with a width of 23 nm and a length of 2 µm. The constrictions were fabricated by opening areas with a width of 50 nm above the NWs at specific locations along the NWs. They were covered with a 30 nm-thick silicon dioxide layer, deposited by a standard plasma enhanced chemical vapor deposition process, before the formation of the interconnect lines.

Conclusions In summary, the formation of small constrictions in highly doped nanowires provides an effective modulation of the current, leading to a large on–off ratio at room temperature. Since the transistor works without any junction, its fabrication is less demanding. It relies on good control over the alignment of the interconnect lines with the constrictions, so that each NW-FET is selectively turned off by its respective inputs. Such an approach allows us to address specific crosspoints, making

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Confinement-modulated junctionless nanowire transistors for logic circuits.

We report the controlled formation of nanoscale constrictions in junctionless nanowire field-effect transistors that efficiently modulate the flow of ...
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