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An On-Chip Multi-Voltage Power Converter With Leakage Current Prevention Using 0.18 m High-Voltage CMOS Process Yi-Kai Lo, Kuanfu Chen, Parag Gad, and Wentai Liu

Abstract—In this paper, we present an on-chip multi-voltage power converter incorporating of a quad-voltage timing-control V and V simultanerectifier and regulators to produce ously through inductive powering. The power converter achieves a PCE of 77.3% with the delivery of more than 100 mW to the implant. The proposed rectifier adopts a two-phase start-up scheme and mixed-voltage gate controller to avoid substrate leakage current. This current cannot be prevented by the conventional dynamic substrate biasing technique when using the high-voltage CMOS process with transistor threshold voltage higher than the turn-on voltage of parasitic diodes. High power conversion efficiency is achieved by 1) substrate leakage current prevention, 2) operating all rectifying transistors as switches with boosted gate control voltages, and 3) compensating the delayed turn-on and preventing reverse leakage current of rectifying switches with the proposed look-ahead comparator. This chip occupies an area of 970 m 4500 m in a 0.18 m 32 V HV CMOS process. The quad-voltage timing-control rectifier alone is able to output a high DC voltage at the range of [2.5 V, 25 V]. With this power converter, both bench-top experiment and in-vivo power link test using a rat model were validated. Index Terms—Bioelectronics, dynamic substrate biasing, implant, inductive power link, power telemetry, prostheses, rectifier, regulators, reverse leakage current, substrate leakage current, wireless power transfer.

I. INTRODUCTION

M

IXED-MODE signal and mixed-voltage integrated circuits are widely used in modern biomedical implants to optimize performance and to achieve better power efficiency. Low DC voltages are used to power the implant’s digital controller and data telemetry circuits. High DC voltages with dual polarities are typically adopted by a stimulator which must maintain charge neutrality via biphasic stimulation and accommodate the high electrode-tissue impedance [1]–[5]. For example, applying a biphasic current stimulus of A on an electrode with an electrode-tissue impedance of 50 k necessitates a minimal compliance voltage of V, but the rest Manuscript received May 19, 2014; revised August 31, 2014; accepted November 10, 2014. The project was supported in part by grants from NSF ERC BMES, UC Lab Fee Program, and California Capital Equity LLC. This paper was recommended by Associate Editor T. Denison. The authors are with the University of California, Los Angeles, CA 90095 USA (e-mail: [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TBCAS.2014.2371695

Fig. 1. General architecture of power converter system.

of the implant, including digital control circuitry, uses low DC voltages of V, [1], [2], [5], [6]. Currently, transcutaneous inductive-powering schemes have been shown as a viable approach for power-demanding implants [1]–[5], [7]–[10]. It is thus essential to produce multiple DC voltages from a single external AC power source with high power conversion efficiency (PCE) for size-restricted implants. On the other hand, in order to reduce surgical invasiveness, the number of discrete components in the implant must be minimized. This further necessitates the design of a highly integrated power converter for the implant. To date, many inductive-power recovery circuits for implants have been proposed and investigated [9], [11]–[24]. One previous method includes a power amplifier driving an external coil to transmit power signals to the coil in the implant. An on-chip active rectifier and a low-drop-out (LDO) voltage regulator receive the power signal and produce a stable DC voltage for the implant [9], [11]–[15], [25], [26] (Fig. 1). Although a high PCE is achievable by using this configuration, one of the limitations is that only a single DC output is available. A buck DC-DC converter may be applicable to generate a low DC voltage from a high DC voltage, but this approach is not suitable for implants with size-restriction since a large inductor is required at the operating frequency of several megahertz. Charge pumps (CPs) or step-down converters (SDCs) can also be used to produce multiple DC voltages, but these require a tradeoff between output power, capacitor size, and clock frequency [18], [22]. A high frequency clock reduces the size of the capacitors and increases efficiency, but is usually not available for implants. Multiple chip solutions and off-chip diodes have also been adopted to provide multiple DC voltages at the cost of increased complexity and expense in packaging [3], [4], [19], [20]. Recently, multiple power receiving coils for the generation of low and high DC voltages were presented in [17]. Nonetheless, the size

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of the implant is inherently increased. Two regulators following a single rectifier have also been used to generate both high and low voltages for a implant, but extra power is lost during the conversion of a induced high voltage to a low-DC voltage [10]. The high-voltage (HV) CMOS process has been popularly adopted to build the electronics of implants [1]–[5]. However, a major challenge existing in the generation of high DC voltage using the HV CMOS process is the substrate leakage current [21]. In addition, the power converter must be self-contained and operate autonomously by only receiving the AC power signal from the coil as no pre-existing DC voltage is available in the implant for start-up. Once the substrate leakage current cannot be avoided during start-up, the power link of the implant suffers malfunction. Thus, a novel approach to avoid substrate leakage for the HV process is required. Implemented in a 0.18 m 32 V 1P6M HV CMOS process, the proposed multi-voltage power converter contains a quadvoltage timing-control rectifier and regulators. It can simultaneously produce both V for the implant’s digital controller and data telemetry circuits, as well as V for stimulators. The proposed mixed-voltage gate controller and start-up scheme prevents the substrate leakage current and secures the start-up of the power converter. The PCE of the power converter is further enhanced by 1) compensating the delayed turn-on and reverse leakage current of the rectifying transistors through the look-ahead comparator (LAC) in the rectifier; and 2) by operating the rectifying transistors as switches with boosted control voltages. The proposed power converter is capable of providing a wide range of power ([10 mW, 100 mW]) with high efficiency for the implant. Even at high load, the proposed quad-voltage rectifier achieves PCE larger than 80% and 77.3% for the overall converter. Both a bench-top system test as well as an in-vivo power link test for a rat model with an implanted coil were performed. The remainder of this paper is organized as follows. Section II describes the design considerations, while Section III presents an overview of the quad-voltage power converter system. Sections IV and V respectively describe the quad-voltage rectifier and regulators with reference generator. Measurement results are given in Section VI, and conclusions are drawn in Section VII. II. DESIGN CONSIDERATION Design considerations for the power telemetry of implantable devices have been intensively discussed in [25]. However, design issues regarding using the HV process for the implant have not been thoroughly discussed. Additional complications for the HV process include a higher threshold voltage ( V for the HV NMOS and V for the HV PMOS) and low electron mobility. A -cancelled technique has been proposed to mitigate the drawback of high in HV transistors. Nonetheless, it suffers increased reverse leakage current since the rectifying PMOS transistor is turned on before the induced voltage is higher than its output voltage [14], [17]. Moreover, to deliver tens of mW to the implant, a large-size rectifying transistor is needed in order to source a large current from the coil with small drain-to-source voltage drop. Large-size transistors inevitably limit the operation/switching

Fig. 2. (a) Simplified cross-section view of the layout of a half-wave rectifier. (b) Conventional dynamic biasing circuit to set voltages for the substrate . Note that this substrate biasing technique (VSUB) and PMOS bulk fails to prevent substrate leakage current in HV CMOS process.

speed of the rectifier. An unbalanced-biased comparator with non-zero turning-off trigger voltage is proposed to shut off the rectifying transistors when the induced voltage is smaller than the rectifier’s output voltage [9], but the turn-on delay of the rectifying transistor is not compensated, leading to power loss. High-speed and compensated biasing comparators are also reported to control rectifying switches, but extra current is consumed [24], [26]. More critically, if those circuit techniques were directly applied to the HV rectifier, more power would be dissipated due to the much higher supply voltage used by the rectifier control circuitry. No triple-well process available for HV transistors and passive HV diodes is another design challenge for the rectifier design. Fig. 2(a) demonstrates the simplified cross-section view of the layout of a half-wave rectifier implemented in HV transistors. The half-wave rectifier can be implemented as either simple diode-connector transistors or active switches with proper gate control voltages. The branch made of PMOS is used to generate a positive DC voltage and the branch made of NMOS is used to generate negative DC voltage. Note that PMOS might also be used to generate the negative voltage. However, its gate-source voltage is limited in its diode-connected configuration and thus VCE. Moreover, when configuring this PMOS as a switch a large gate-source voltage

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Fig. 3. The system diagram of the proposed multi-voltage power telemetry. are of the LV rectifier.

is also difficult to achieve, as its gate control voltage must be lowered than its input/output negative voltage. When the parasitic BJT, , is turned on, the substrate leakage current is created. This usually occurs after turning on the external power source while the DC output voltages of the implant are still zero. distracts the current, which is supposed to flow from the coil to and charges the chip substrate. The substrate potential is raised up accordingly. On the other hand, is on when the induced voltage is one diode-voltage drop lower than the substrate potential. Amplitude of is then clamped due to the leakage current during its positive phase and activation of during its negative phase, while negative DC is limited by . Therefore, DC cannot reach the expected levels and the implant’s PCE is greatly diminished. A common approach to preventing utilizes an adaptive substrate biasing circuitry to set the bulk and the substrate voltages of the rectifying transistors, as shown in Fig. 2(b) [4], [13]–[16], [23], [25], [26]. and are used as switches controlled by the voltage difference between and DC. The difference must be greater than of the HV

and

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are the rectifying transistors of the HV rectifier while

and

of the HV trantransistor to fully turn it on. However, sistor is higher than the parasitic diode’s turn-on voltage. Consequently, during the start-up phase, the leakage current appears earlier than the operation of adaptive biasing circuitry; thus the desired output voltage levels cannot be reached, leading to a large power loss. In order to prevent the substrate leakage current and reverse leakage current to achieve high PCE, we have proposed a novel scheme that will be explained in Section IV. III. SYSTEM OVERVIEW Fig. 3 (upper panel) illustrates the system architecture of an implantable multi-channel stimulator to explain the context of the proposed quad-voltage power converter. The system includes two parts: the external transmitter and the internal receiving device (the implant). The transmitter sends the power and the data signals inductively to the implant’s receiving coils. On the implant side, the quad-voltage power converter rectifies the power signal and regulates it to multiple DC voltages in order to power the implant. The data receiver acquires the transmitted data, using it to set up the stimulus parameters accordingly.

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Fig. 4. Schematic of the HV rectifier to generate

, modified from [2].

Fig. 3 (lower panel) shows the block diagram of the proposed power converter, consisting of a quad-voltage timing-control rectifier, four regulators, a supply-insensitive reference voltage generator, and four external storage capacitors, , at rectifier outputs. Through inductive powering, two AC voltages, and , are induced by the center-tapped coil from the transmitter coil . Taking the induced voltages, the rectifier simultaneously produces both low positive and negative voltages, and , as well as high positive and negative voltages and . Four DC-voltages, , and are generated by the regulators, after taking the rectifier outputs. Reference voltages for the regulators, , and , are given by the supply-insensitive reference generator and in our application of epi-retinal prostheses, they are set at V and V, respectively. The proposed multi-voltage power converter for biomedical implants is self-contained, and requires no external or pre-existing power source. IV. QUAD-VOLTAGE TIMING CONTROL RECTIFIER A. Principle of Operation The proposed quad-voltage timing-control rectifier is composed of both HV and LV half-wave rectifiers. Fig. 4 shows the schematic of the HV rectifier that generates [2]. The gate controller of the rectifying PMOS transistor, , includes a look-ahead comparator (LAC), a pulse generator (PG), and a

level shifter (LS). The LAC first senses the difference between and and then triggers the PG to produce a short pulse, defining the conduction time of . The conduction time can be adjustable by modifying the divider ratio between in Fig. 4 with 2-bit control. The LS then magnifies the amplitude of the PG output from to , and drives the gate of the . The gate controller in the HV rectifier not only governs the switching timing of , but is also a part of the start-up circuit and substrate leakage prevention scheme in the HV rectifier. A small diode-connected transistor, , provides a path to initially charge to the minimal required operating voltage of LS. Both are used to validate our start-up scheme only. Note that with and alone the designated output voltage cannot be produced because of the substrate leakage current. and its switch controller are thus essential in this rectifier. The rectifier is operated at two supply voltages and thus can be divided into two parts: 1) the LV LAC and PG, and 2) the HV rectifying switch , LS, and dynamic biasing circuitry . The dynamic biasing here is to test its effectiveness in the HV process and validate our hypothesis that with dynamic substrate bias circuits alone the substrate leakage current cannot be prevented The supply voltage arrangement is crucial for autonomous circuit start-up and the prevention of the substrate leakage current, which will be explained in Section IV (C, D). A complementary HV rectifier circuitry is used to generate . The same functional blocks of the HV rectifier are also applied on the LV rectifier but using only 5 V devices.

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B. Mixed-Voltage Gate Controller One important aspect of maximizing the power transfer from the coil to is turning on immediately when and turning it off when . However, there is an inevitable delay from sensing the difference between and to the realistic on-and-off action of . To compensate the delay for enhancing PCE, we proposed an LAC to sense and and to trigger the LS output before . The look-ahead time interval is set by the voltage divider in the LAC. The LAC consists of a comparator and resistor voltage dividers. The comparator is a complementary self-bias operational amplifier with low minimum operating voltage, which is merely the sum of the threshold voltages of its tail current source transistors [27]. The ratios of voltage dividers at both inputs of the comparator are chosen to advance the ideal turn-on timing of , and to ensure the derived signals of the induced voltages and the rectifier output are compatible with the common-mode voltage range of the comparator. Common centroid layout style and extra dummy resistors are adopted to improve the matching between the divider resistors and mitigate the influence of process variation since the resistors’ ratio is more important than the actual values. The ratio is decided as follows: suppose that the expected output voltage of the rectifier is , the triggering voltage of the control logic is , the amplitude of the induced voltage is , and the signal propagation time from the LAC input to the LS output is t, as shown in Fig. 4 (top right panel). We assume the induced voltage is a sine wave and is set to the voltage which happens t time ahead the induced voltage reaches . can thus be derived as

(1) The ratios of the voltage dividers at the two inputs of the comparator are thus respectively determined as and . On the other hand, there is a power loss as a result of the reverse leakage current flowing from the storage capacitor to the coil. This leakage current happens when and is still on. might be quickly turned-off by using a HV high-speed comparator or HV level shifter. However, is a HV transistor that is implemented with a large device area (hence a large parasitic capacitance) in order to pass high transient current to the storage capacitor. A large gate control signal is also desired to reduce its turn-on resistance for better PCE. A high-slew rate HV comparator or HV gate driver might be usable to activate/deactivate quickly. However, more power would be consumed in the rectifier control circuits. Consequently, as a tradeoff, the PG is designed to deliver a short pulse to control . The pulse width (PW) is chosen as , in which the first term is the half cycle time of the sinusoidal power signal; the second term is twice the time required for the power signal to rise from 0 V to targeted output voltage. This pulse width is set by the

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“Delay” in Fig. 4 to turn off such that reverse current is prevented. Fig. 4 (bottom right panel) shows the simulated operation waveform of the HV rectifier, with the proposed control scheme operating the rectifying transistors ( and ) to enhance the power transfer and prevent reverse leakage current. C. Substrate Leakage Prevention Through Mixed-Voltage Gate Controller From the description in Section II, we know that conventional substrate leakage current prevention is not applicable to the HV CMOS process. To prevent the substrate leakage current during the start-up and steady state of the rectifier, we propose to turn on the rectifying switches to charge/discharge the storage capacitor before the parasitic BJT is on via the mixed-voltage gate controller. Once is immediately turned on prior to the conduction of the vertical parasitic BJT (the BJT is on when is larger than by and are zero initially). Thus, the current from the coil charges to raise first instead of charging the chip substrate to boost the substrate potential. is then off when . It is important to note is also increasing since there are PN junctions between , and . Through the periodic activation of during start-up, both and are gradually increased. Note that increasing reduces/prevents the substrate leakage current. With the operation of the mixed-voltage controller in the HV rectifier, and can then be gradually pulled to the desired levels. Thus, the induced amplitude of is not limited by the substrate leakage current in its positive phase as well as the turn-on of the parasitic diode formed by the substrate and in its negative phase. D. Two-Phase Start-Up Scheme A start-up methodology is proposed by incorporating the operation of the LV rectifier as part of the start-up circuitry in the HV rectifier. This configuration provides the advantages of a) an early-stabilized low DC voltage that ensures the proper function of the data telemetry and digital circuits before stimulus is fired to avoid false stimulation; b) enabling the switch control circuits of the HV rectifier to be implemented in the LV transistors, reducing both chip area and power consumption; c) preventing substrate leakage current. The start-up scheme can be broken down into two phases, as shown in Fig. 5(a). In phase I, LV diodes in the LV rectifier initially set and to enable the operation of the LAC and PG. Note that in the LV rectifier, since the of the LV transistor ( V) is smaller than the , substrate leakage current would not impede its start-up. In phase II, HV diodes and its switch controllers powered by the LV rectifier serve as the start-up circuitry for the HV rectifier. HV diodes set the initial and for the LS while the switch controller provides the on-off signal for the and to further increase and . The proposed arrangement of start-up sequence prevents substantial substrate leakage current. Fig. 5(b) shows the start-up waveform of the rectifier, in

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Fig. 5. (a) Start-up sequence and (b) start-up waveform of the quad-voltage rectifier.

Fig. 6. (a) Schematic of HV and LV regulators and reference generation circuits for

which four outputs gradually stabilize after receiving inductive power. It is worth noting that and reach their stable values earlier than and as desired. Note that the mixed-voltage gate controller is working during both the start-up and steady state of the HV rectifier. V. REGULATORS AND REFERENCE CIRCUITS Fig. 6 shows the schematic of the regulators and supply-insensitive reference generator to generate and . The supply-insensitive reference generator adopts the self-biasing technique to reduce the power supply sensitivity [28]. We separate the HV and LV reference generator such that and can be used for other applications that do not require high DC voltages. Moreover, the start-up of the reference generator is achieved by connecting the rectifiers output to the supply voltage of the generator. Thus, during the start-up of the rectifier, the reference generator is also powered up. A complementary circuitry is used to generate and . The reference voltages of and are chosen to be V, V, V, V, respectively. A MOS capacitor is placed at the output of each regulator to maintain its stability. The regulators provide output voltages of V, V, V, and V for the implant. Fig. 6(a) shows the post-layout simulation results of the start-up of HV regulators. In this simulation, increasing

and

. (b) Post-layout simulation of regulators.

and are fed to the regulator input in order to mimic the input from the regulator. A constant current of 3 mA is drained from the outputs to emulate the circuit load. It can be seen that once and exceeds V, and are stabilized and are less sensitive to the change of input. An output drop-out voltage of 0.9 V occurs when reaches 25 V. Note that there are two voltage dips at ms, caused by the fact that the differential amplifier pulls the output voltage to twice the reference voltage (input voltages are larger than twice of reference voltages then). However, when regulator input voltage falls to be less than twice of its reference voltage, the regulator output voltages just follows its input voltage. As shown in Fig. 6(b), for the LV regulators, and are stabilized when and pass V. With a constant current load of 10 mA, an output drop-out voltage of 0.6 V occurs after the LV outputs are stabilized. There are no voltages dips in the LV regulator outputs as no voltage divider is used to sense its output voltages in the feedback loop. VI. EXPERIMENTAL RESULTS AND DISCUSSION The proposed quad-voltage power converter is fabricated in the TSMC 0.18 m 32 V HV 1P6M CMOS process. The chip micrograph is shown in Fig. 7 with an area of 970 m 4500 m. A large portion of the chip area is occupied by MOS

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Fig. 7. Micrograph of the proposed quad-voltage power converter.

Fig. 8. (a) Measured waveform of the LV rectifier with a 30 k loading and are the bulks of and , resistance. respectively. (b) Measured waveform of the HV rectifier with a 12 k loading and are bulk voltages of and . resistance.

capacitors of the regulators due to the small oxide capacitance of HV and 5 V transistors. Experiments in both 1) bench-top test using the retinal demo system developed in our lab [29] and 2) an in-vivo rat model with implanted coils were performed. In the bench-top test, the power converter was powered via an inductive link for performance evaluation. External resistors were placed at rectifier outputs or regulator outputs to emulate the loading. Four external storage capacitors of 100 nF were

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placed at four rectifier outputs. A primary class-E power transmitter drove the external coil and the power converter received power via a center-tapped coil. The separation of these two coils was 1.7 cm and the coil was made by litz-wire (AWG-48, 100 strands) with the specification similar to [29]. Fig. 8(a) shows the measured waveforms of the LV rectifier. is the input of the LV rectifier; and are bulk potentials of the LV rectifying transistors; and are the rectifier outputs. At a amplitude of 3 V, is 5.4 V with a loading resistance of 30 k . High voltage conversion efficiency (VCE) of 90% is achieved. As seen in the top-right inset of Fig. 8(a), we also observe a voltage dip of with a duration of 20 ns. This is likely due to the conduction of , such that is pulled to approach . A similar phenomenon can also be seen in the bottom-right inset of Fig. 8(a) where a voltage dip occurs when is conducting. Fig. 8(b) shows the measured waveform of the HV rectifier. is the input voltage of the HV rectifier; and are the bulk voltages of and , respectively, and and are HV rectifier outputs. Note that is also the substrate voltage of the entire circuit. With a amplitude of V and a loading resistance of 12 k is 24.5 V and achieves a VCE of 87.5%. The measured conduction periods of and are 15 ns and 18 ns, respectively. The conduction periods of and deviate from the designated period of 40 ns; this is probably due to process variation that leads to the deviation of the ratio of the resistor voltage divider and delay-time set by the Delay block in the rectifier control logic. The shorter turn-on time results in incomplete utilization of each charge/discharge cycle, lowering PCE. Moreover, the practical waveform of the induced voltage is not a perfect sine wave as used in the derivation of the turn-on periods, leading to additional power loss. Fig. 8(b) shows a voltage ripple in . The ripple is a scaled-down superimposed on through capacitive coupling. The same phenomenon also appears in , but with a smaller ripple due to the large substrate parasitic capacitance. Similarly, the same observation applies to and . Fig. 9(a) shows the VCE of the rectifiers, with the definition of , where is the amplitude of induced voltage at the rectifier input and is the rectifier output voltage. The LV rectifier has a VCE of 82% at a load of 10 mW while the HV rectifier maintains a VCE greater than 80% at a load of 127 mW. With the increasing load power, VCE drops accordingly: a larger for the rectifying transistor is required to allow more current to the storage capacitor. Fig. 9(b) shows the PCE of the rectifier based on [see (2) at the bottom of the page], where and respectively represent measured rectifier output voltages of and

(2)

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Fig. 10. Measured versus induced peak-to-peak voltage of and VCE of the HV rectifier at a current load of 2 mA. Note that and are gradually operating in deeper with increasing triode region during their conduction period such that increasing speed of VCE is reaching a plateau progressively.

Fig. 9. (a) Measured VCE of the LV and HV rectifiers. For the HV rectifiers, is with a of 28 . For the LV rectifier, is with a of 6 [1], [2]. (b) Measured PCE of the quad-voltage rectifier. A constant load of 10 mW is applied to the LVrecV, kohm) while tifier outputs ( an increasing load is applied to the HV rectifier to mimic real operation of the implant. (c) Power distribution of the main components in the quad-voltage recV, load resistor between and is tifier ( 18.2 kohm).

and are the measured loading currents from load resistors, are the measured currents consumed by the control logics, and and are the calculated power losses caused by the dynamic switching power and the measured voltage-drop of the rectifying transistors. A constant load of 10 mW ( V, k ) is applied on the LV rectifier outputs to emulate the practical operation in which the LV circuits of the implant are always turned on to control the stimulators. It can be seen that the proposed power converter can provide a wide range of deliverable power with a high efficiency for various applications. Even if more than 100 mW is consumed for stimulation, PCE is still higher than 80%. A critical issue for implantable devices is the tissue damage as a result of thermal elevation. The temperature elevation is due to the power dissipation of the implant and should be kept below 1 C to prevent tissue damage [2]. However, the allowable power consumption of the implant depends on the location

of the device. For brain stimulation, the power consumption of the implant should be lower than 35 mW [30]. Nonetheless, for epi-retinal prostheses, the implant can be placed inside the vitreous cavity that serves as a heat sink for better power dissipation. The temperature increase of the retina with an implant consuming mW power can be projected to be C based on [31], which is within the limit. A pie-chart illustrating the power consumption of the main component of the rectifier is shown in Fig. 9(c). It can be seen that the major power loss, and , together is 6.01%. Note that the control logic in the HV rectifier is implemented in LV devices and powered by a LV rectifier such that its power consumption can be dramatically reduced compared to being powered by the HV rectifier outputs directly. The power consumption of control logics in the HV or LV rectifiers only occupies 0.42% (0.197 mW). To demonstrate the flexibility of the proposed rectifier, we measured and VCE of the HV rectifier with a constant loading current of 2 mA under different induced amplitudes of (Fig. 10). can be varied from 2.5 V to 24.5 V for a wide range of applications requiring HV compliance voltages. Smaller results in lower VCE since the LS is also powered by low and . It is also observed that VCE increases slowly when V. This is due to the fact that with increasing and are gradually operated in the deep triode region when they are conducting. A measurement of the power efficiency of the power telemetry system versus the separation between two coils was conducted. In the test, the distance between the primary coil driven by a class-E power amplifier and the receiving coil connecting to the rectifier was varied. The rectifier outputs were connected to resistors to emulate the load. The power delivered from the primary power transmitter was adjusted to ensure the load resistors consumed a power of 100 mW. We define the power efficiency of the power telemetry system as

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Fig. 12. Experiment setup for in-vivo power link test.

Fig. 11. Measured system power efficiency versus coil separation. The power efficiency is defined by the power consumed by the rectifier load resistors divided by the power consumed by the primary class-E power amplifier.

the power consumed by loading resistors divided by the power consumed in the class-E power transmitter. It can be found that there is an optimal distance between two coaxial coils (Fig. 11). According to [32], Terman demonstrated the best coupling coefficient for coaxial coil pair appears when

(3) where and are the diameters of the transmitter coil and the receiver coil, respectively, and D is the distance between each coil. Based on the diameters of the transmitting coil (3.9 cm) and the receiving coil (1.9 cm), the optimal separation is 1.7 cm, close to the measured results (1.6 cm). Deviation from the optimal separation leads to the efficiency drop. As explained in Section II, conventional dynamic substrate biasing technique is not applicable in the HV process. Once the substrate leakage emerges, not only is the PCE of the power link seriously degraded, but the operation of the implant would also fail. An in-vivo power-link experiment was thus conducted using a rat model. The purpose of this test is two-fold: 1) to verify the proposed start-up and substrate leakage prevention scheme, and 2) to test the longevity of the implanted coil. An adult female Sprague Dawley rat (270–300 g body weight) was used in the in-vivo experiment. All procedures complied with the National Institute of Health Guide for the Care and Use of Laboratory Animals and were approved by the Animal Research Committee at UCLA. Details of the pre- and post-surgical animal care can be found in [33]. The coil was completely coated with medical grade silicone (Sylgard 184, Dow Corning, Midland, MI) and cured in an oven at 120 C for 20 minutes. The litz wires were connected to stainless steel wires (AS632, Cooner Wire, Chatsworth, CA) and routed subcutaneously to a head mounted connector (Omnetics, Minneapolis, MN). The coil was placed subcutaneously in the back of the animal for 9 weeks and

Fig. 13. Measured waveform of the HV rectifier with conventional dynamic substrate biasing scheme only during (a) start-up and (b) steady-state. The start-up of the HV rectifier fails due to the substrate leakage current.

kept intact while the rat remained in healthy condition without infections and the coil is intact. The setup of the in-vivo experiment is shown in Fig. 12. The external power coil was placed on top of the implanted receiver coil. Induced voltages of the receiver coil were taken from the headplug to power the multi-voltage power converter.

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TABLE I PERFORMANCE COMPARISONS WITH PRIOR ARTS

The mixed-voltage gate controller of the HV rectifier was enabled and the power transmitter was first turned on to produce the similar results shown in Fig. 8 and then turned off. Subsequently, in the first experiment, the HV rectifier was tested with conventional dynamic substrate biasing only while its mixedvoltage gate controller was off. In this configuration, no load was placed at the rectifier and the start-up diode was used to charge/discharge the storage capacitors. As shown in Fig. 13(a), after the primary power transmitter is on, and initially increase. However, after grows larger than by drops immediately due to the emergence of substrate leakage current. The leakage current then charges the substrate to increase and causes the start-up to fail. The steady state of the HV rectifier is shown in Fig. 13(b). The measurement results show and are limited to below V even with increasing transmitted power. As expected, the leakage current raises the and limits the magnitude of , and . Ripples at and are due to the charge transferring between the coil and . Note that with the presence of substrate leakage current, outputs of the power converter would never reach the desired values. In the following test, the mixed-voltage controller of the HV rectifier was enabled. With the proposed start-up scheme, all rectifier outputs can reach the designated level, respectively, and the leakage current can be prevented, as shown in Fig. 14. To further illustrate the operation of the start-up scheme of the rectifier, a zoom-in waveform captured right after the turn-on of the primary transmitter is shown in the inset of Fig. 14. We can separate the operation of the start-up circuit into two phases. In phase I, and to power the LAC are not large enough such that the operation speed and driving capability of the LAC are limited. However, we can infer

Fig. 14. Start-up waveform with mixed-voltage gate controller on.

from the results that discharging/charging current to the storage capacitors is still larger than the substrate leakage current since rectifier outputs are still being pulled slowly toward the desired values. Subsequently, in phase II, with enough and to enable the normal function of the LAC, rectifier outputs increase/decrease rapidly. Notably, starts to decrease again, which is probably due to the diminishing substrate leakage current. It can be also observed there is a voltage dip when is larger than 2 V. This voltage dip is caused by the activation of a functional block fabricated with the power converter and this functional block is internally connected and powered by .

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. LO et al.: AN ON-CHIP MULTI-VOLTAGE POWER CONVERTER WITH LEAKAGE CURRENT PREVENTION

TABLE II SUMMARY OF SUBSTRATE LEAKAGE CURRENT PREVENTION SCHEMES

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a high-speed rectifying switching control circuit is not required, further saving power consumption. A PCE of 82.8% and 77.3% for the quad-voltage rectifier and the power converter, respectively, are achieved at the load of 108 mW. The quad-voltage power converter allows for the integration and miniaturization of implants operating at multiple DC voltages. ACKNOWLEDGMENT

Table I compares and summarizes the performance of the proposed quad-voltage power telemetry with previously reported work. It should be noted that [30] adopts a charge-pump to generate high-voltage output with a relatively small area and a delivered power of 2.8 mW (0.3 mW for the high voltage stimulator and 2.5 mW for the rest of the system). Though using charge pump circuits following a rectifier reduces chip area, its overall power efficiency in the generation of high DC voltage is only 36-60% (the product of the efficiency of the rectifier (84.5%) and the charge pump (43–72%)). If the charge-pump circuit in [30] is used to provide larger load current, then larger storage capacitance is required to achieve a high efficiency and its advantage of small area may be lost. By using the proposed power converter, when 108 mW is delivered to HV stimulators (98 mW), LV digital control and telemetry circuits of the implant (e.g., retinal prostheses including hundreds of stimulation channels or implant for high-density wireless neural recordings and stimulation), the quad-voltage rectifier achieves a high PCE of 82.8%. More importantly, the proposed substrate leakage current prevention scheme has been proven effective in the HV process. Table II shows a comparison between the conventional scheme and ours. Rectifiers using conventional dynamic biasing circuits only are not applicable to the HV process unless a method, such as the proposed mixed-voltage gate controller, is first implemented to improve the efficiency of the rectifier. VII. CONCLUSION An integrated quad-voltage power converter for biomedical implants was designed and implemented in a 0.18 m 32 V HV CMOS process. The power converter circuit was able to simultaneously provide both V and V for the implant, which is usually a mixed-voltage, and mixed-mode design. Our scheme is particularly suitable for those implantable applications which require high compliance voltage. For example, this scheme has been used in the SoC of a retinal implant with high-density stimulation channel [1] and the proposed power converter occupied 12% of the chip area. The HV rectifier also supports a wide range of dual high DC voltages that are often required by various biomedical applications. We reported and verified a novel scheme using the mixed-voltage gate controller to effectively enable the start-up of the rectifier and prevent the substrate leakage current in the HV process. This substrate leakage current cannot be solved by the conventional dynamic biasing technique when the threshold voltage of a transistor is higher than the turn-on voltage of a parasitic diode. PCE is further improved by compensating the delayed on/off timing of rectifying transistors by the switch controller. With the LAC,

The authors would like to thank Dr. F. L. Hsueh and Dr. M. H. Tsai of TSMC for their technical support. They would also like to thank the chip fabrication and packaging support provided by TSMC. REFERENCES [1] K. Chen, Y.-K. Lo, and W. Liu, “A 37.6 mm 1024-channel highcompliance-voltage SoC for epiretinal prostheses,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2013, pp. 294–295. [2] Y. K. Lo, K. Chen, P. Gad, and W. Liu, “A fully-integrated high-compliance voltage SoC for epi-retinal and neural prostheses,” IEEE Trans. Biomed. Circuits Syst., vol. 7, no. 6, pp. 761–772, Dec. 2013. [3] M. Ortmanns, N. Linger, A. Rocke, S. Rackow, M. Gehrke, and H. J. Tiedtke, “A 232-channel visual prosthesis ASIC with productioncompliant safety and testability,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2007, pp. 152–593. [4] E. Noorsal, K. Sooksood, X. Hongcheng, R. Hornig, J. Becker, and M. Ortmanns, “A neural stimulator frontend with high-voltage compliance and programmable pulse shape for epiretinal implants,” IEEE J. SolidState Circuits, vol. 47, pp. 244–256, 2012. [5] K. F. Chen, Z. Yang, L. Hoang, J. Weiland, M. Humayun, and W. Liu, “An integrated 256-channel epiretinal prosthesis,” IEEE J. Solid-State Circuits, vol. 45, pp. 1946–1956, Sept. 2010. [6] S. Shah, A. Hines, D. Zhou, R. J. Greenberg, M. S. Humayun, and J. D. Weiland, “Electrical properties of retinal-electrode interface,” J. Neural. Eng., vol. 4, pp. S24–S29, Mar. 2007. [7] F.-G. Zeng, R. S. , H. W. , X. Sun, and H. Feng, “Cochlear implants: System design, integration, and evaluation,” IEEE Rev. Biomed. Eng., vol. 1, pp. 115–142, 2008. [8] J. Coulombe, M. Sawan, and J. F. Gervais, “A highly flexible system for microstimulation of the visual cortex: Design and implementation,” IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 4, pp. 258–269, Dec. 2007. [9] S. Guo and H. Lee, “An efficiency-enhanced CMOS rectifier with unbalanced-biased comparators for transcutaneous-powered high-current implants,” IEEE J. Solid-State Circuits, vol. 44, pp. 1796–1804, Jun. 2009. [10] N. Tran et al., “A complete 256-electrode retinal prosthesis chip,” IEEE J. Solid-State Circuits, vol. PP, pp. 1–16, 2014. [11] Y. H. Lam, W. H. Ki, and C. Y. Tsui, “Integrated low-loss CMOS active rectifier for wirelessly powered devices,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, pp. 1378–1382, Dec. 2006. [12] K. F. E. Lee, “A timing controlled AC-DC converter for biomedical implants,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2010, pp. 128–129. [13] L. Hyung-Min and M. Ghovanloo, “An integrated power-efficient active rectifier with offset-controlled high speed comparators for inductively powered applications,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, pp. 1749–1760, 2011. [14] S. Lange et al., “An AC-powered optical receiver consuming 270μW for transcutaneous 2 Mb/s data transfer,” in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, 2011, pp. 304–306. [15] C. Hyouk-Kyu, P. Woo-Tae, and J. Minkyu, “A CMOS rectifier with a cross-coupled latched comparator for wireless power transfer in biomedical applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 59, pp. 409–413, 2012. [16] S. S. Hashemi, M. Sawan, and Y. Savaria, “A high-efficiency lowvoltage CMOS rectifier for harvesting energy in implantable devices,” IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 4, pp. 326–335, Aug. 2012. [17] X. Hongcheng, E. Noorsal, K. Sooksood, J. Becker, and M. Ortmanns, “A multichannel nurostimulator with transcutaneous closed-loop power control and self-adaptive supply,” in Proc. Eur. Solid-State Circuits Conf., 2012, pp. 309–312.

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS

[18] Y. C. Huang, M. D. Ker, and C. Y. Lin, “Design of negative high voltage generator for biphasic stimulator with SoC integration consideration,” in Proc. IEEE Biomed. Circuits Syst. Conf., 2012, pp. 29–32. [19] E. Lee et al., “A biomedical implantable FES battery-powered microstimulator,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, pp. 2583–2596, Dec. 2009. [20] F. Mounaim and M. Sawan, “Toward a fully integrated neurostimulator with inductive power recovery front-end,” IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 4, pp. 309–318, Aug. 2012. [21] F. Mounaim and M. Sawan, “Integrated high-voltage inductive power and data-recovery front end dedicated to implantable devices,” IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 3, pp. 283–291, Jun. 2011. [22] Z. Jianming, Y. Lei, X. Rui-Feng, P. Li, J. Minkyu, and X. Y. Ping, “A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications,” in Proc. IEEE Asian Solid-State Circuits Conf., 2013, pp. 253–256. [23] S. Y. Lee, J. H. Hong, C. H. Hsieh, M. C. Liang, and J. Y. Kung, “A low-power 13.56 MHz RF front-end circuit for implantable biomedical devices,” IEEE Trans. Biomed. Circuits Syst., vol. 7, no. 3, pp. 256–265, Jun. 2013. [24] Y. Lu and W. H. Ki, “A 13.56 MHz CMOS active rectifier with switched-offset and compensated biasing for biomedical wireless power transfer systems,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 3, pp. 334–344, Jun. 2014. [25] G. Bawa and M. Ghovanloo, “Analysis, design, and implementation of a high-efficiency full-wave rectifier in standard CMOS technology,” Analog Integr. Circ. Signal Process, vol. 60, pp. 71–81, Aug. 2009. [26] L. Hyung-Min and M. Ghovanloo, “A high frequency active voltage doubler in standard CMOS using offset-controlled comparators for inductive power transmission,” IEEE Trans. Biomed. Circuits Syst., vol. 7, no. 3, pp. 213–224, Jun. 2013. [27] M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. Solid-State Circuits, vol. 26, pp. 165–168, 1991. [28] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. Hoboken, NJ, USA: Wiley, 2001. [29] K. F. Chen, Y. K. Lo, Z. Yang, J. D. Weiland, M. S. Humayun, and W. T. Liu, “A system verification platform for high-density epiretinal prostheses,” IEEE Trans. Biomed. Circuits Syst., vol. 7, no. 3, pp. 326–337, Jun. 2013. [30] W. M. Chen et al., “A fully integrated 8-channel closed-loop neuralprosthetic CMOS SoC for real-time epileptic seizure control,” IEEE J. Solid-State Circuits, vol. 49, pp. 232–247, Jan. 2014. [31] K. Gosalia, J. Weiland, M. Humayun, and G. Lazzi, “Thermal elevation in the human eye and head due to the operation of a retinal prosthesis,” IEEE Trans. Biomed. Eng., vol. 51, pp. 1469–1477, Aug. 2004. [32] F. E. Terman, Radio Engineering. New York, NY, USA: McGrawHill, 1947. [33] R. R. Roy, D. L. Hutchison, D. J. Pierotti, J. A. Hodgson, and V. R. Edgerton, “EMG patterns of rat ankle extensors and flexors during treadmill locomotion and swimming,” J. Appl. Phys., vol. 70, pp. 2522–2529, Jun. 1991. Yi-Kai Lo received the B.S. and M.S. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, and the Ph.D. degree in bioengineering from the University of California, Los Angeles (UCLA), Los Angeles, CA, USA, in 2004, 2006, and 2014, respectively. His research interests include bioelectronic circuits and system design, neural interface, chronic medical device, and neuroprosthetic devices. He received the Outstanding Ph.D. Award from the UCLA Bioengineering Department in 2014.

Kuanfu Chen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, and the Ph.D. degree in electrical engineering from the University of California, Santa Cruz, Santa Cruz, CA, USA, in 1999, 2001, and 2011, respectively. Since 2013, he has been an Engineer at Qualcomm Inc., San Diego, CA, USA. Before starting his professional career, he was a post-doctor scholar at the University of California, Los Angeles, Los Angeles, CA, USA. His research interests include system-on-a-chip design and system development for retinal prosthesis, electrical neuron/muscle stimulation, image/video processing, and compression

Parag Gad received the B.Eng. degree in biomedical engineering from the University of Mumbai, Mumbai, India, and the M.S. and Ph.D. degrees in neural engineering from the University of California, Los Angeles, Los Angeles, CA, USA, in 2008, 2010, and 2013, respectively. As a student, he focused on spinal cord injury and locomotion rehabilitation after spinal cord injury. His current area of research includes developing hardware, software tools, and stimulation strategies to facilitate locomotion after paralysis.

Wentai Liu received the B.S. degree from National Chiao-Tung University, Hsinchu, Taiwan, the M.S. degree from National Taiwan University, Taipei, Taiwan, and the Ph.D. degree from the University of Michigan, Ann Arbor, MI, USA. In 1983, he joined North Carolina State University, Raleigh, NC, USA, where he held the Alcoa Chair Professorship in electrical and computer engineering and was the founder of the Analog/Mixed-Mode Design Consortium. Since 2003, he has been a Professor in the Electrical Engineering Department at the University of California, Santa Cruz, Santa Cruz, CA, USA, where he is the Campus Director of the NSF Engineering Research Center on Biomimetic Microelectronic Systems. Since 2012, he has been a Distinguished Professor in the Bioengineering Department, University of California, Los Angeles, Los Angeles, CA, USA. His research interests includevisual prosthesis, implantable electronics, high-speed transceiver design (wired and wireless), molecular electronics, microelectronic sensors, timing/clock optimization, on-chip interconnects and computer vision/image processing. Since its early stages, he has been leading the engineering efforts of the retinal prosthesis to restore vision, finally leading to successful preliminary implant tests in blind patients. He has authored more than 180 technical papers and is a coauthor of Wave Pipelining: Theory and CMOS Implementation (Kluwer Academic, 1994) and Emerging Technologies: Designing Low Power Digital Systems (IEEE Press, 1996). Dr. Liu has received an IEEE Outstanding Paper Award, Alcoa Foundation’s Distinguished Engineering Research Award, and the Outstanding Alumnus Award from National Chiao-Tung University, where he is a University System of Taiwan Master Lecturer and Chair Professor.