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17. N O 5. XI A Y I Y Y O

A Package Design Technique for Size Reduction of Implantable Bioelectronic Systems CMOS signal processor chip, and two digital-to-analog converter chips. It should be mentioned at this time that the digital-to-analog conversion relies on capacitive charge sharing scheme [6], which turned out to be a major problem in system packaging as will be described below. These integrated circuits are the essential components of the stimulator, whose overall part list is given in Table I . From the packaging standpoint, it is immediately obvious that the capacitors are the dominant factor in system size. These capacitors provide various functions: power supply smoothing, clock timing, digital-to-analog conversion, and output dc blocking. The electronic system design calls for these capacitors to meet two important design considerations in cochlear prostheses: 1) Various studies of cochlear stimulations show that the most effective stimulation is achieved by injecting a specified amount of charge into the eighth nerve. The most accurate way to store a precise amount of charge at each output electrode is to use one capacitor per electrode in the digital-to-analog conversion. This accounts for nine capacitors: eight for the electrodes and one to store the charge during the conversion process. 2) Nerve cells are damaged by dc currents, thus dc blocking at the output is an absolute requirement. This requirement accounts for eight capacitors. Since these two physiological considerations dictate the use of the capacitors, any change in electronic design will not affect the packaging problem posed by the presence of these capacitors.

Abstract-This paper presents several substrate and package design techniques to minimize the overall size of bioelectronic systems, especially those that will be implanted for in vivo studies. The emphasis is on a new capacitor attachment and a new double-substrate design that have been successfully applied to the packaging of an implantable auditory prosthesis. The entire procedure for this case is described and compared with standard techniques to illustrate the advantages of this new approach in packaging.

I . INTRODUCTION HE PACKAGING of electronic systems to minimize the final product size has always been a difficult problem to solve. This problem is even more severe in implantable electronic devices since the specification for size is particularly stringent. For the implantable auditory prosthesis to be discussed in this paper as an example, the specification calls for the overall size not exceeding 1 .OOO inches in width and length, and 0.250 inches in height since this is the size of the mastoid cavity where the prosthesis will be implanted. A simple implant, e.g., electrodes or sensors, fits quite easily into this cavity; however, a more complicated system, with signal processing and stimulation control capability, is typically much larger. This paper presents a new substrate and package design technique that meets the challenge of packaging a complex auditory prosthesis into the size specified above, and compares this technique with standard procedures in use in the biomedical industry.

T

11. REVIEWOF ELECTRONIC SYSTEM DESIGN The electronic system to be packaged is a speech signal processor. The block diagram is shown in Fig. 1. The processor receives both power and data from an external transmitter (not shown in the figure), and decodes the data into appropriate charge quantities to be delivered to the auditory nerve via the electrode array. The signal processing algorithm and stimulation protocols are described in more detail in [ 11. The system is implemented by four custom integrated circuits (IC): a bipolar receiver chip, a

111. F U N D A M E N TPACKAGE AL DESIGNCONSIDERATIONS The sizes of the components given in Table I do not truly reflect the areas they occupy on a substrate. Bonding rules, component placement, and interconnects play a major role in substrate design. This section will review these fundamental considerations and provide a preliminary estimate of the surface area that would be needed in the conventional substrate design. A . Iiitegrutecl Circuit Bonding An empirical rule for bonding from a pad on an integrated circuit to a pad on a substrate, based on bond strength and experimental bond pull test, states that to descend a vertical height of 15 mil (the average thickness of

Manuscript received December 31, 1988; revised May 23, 1989. This work was supported by the National Institute of Health Grant NOI-NS-52306. The author is with the Department of Electrical Engineering. University of Washington. Seattle, WA 98195. IEEE Log Number 9034249.

0018-9294/90/0500-0482$01.OO @ 1990 tEEE

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S O M A : SIZE REDUCTION OF I M P L A N T A B L E BIOELECTRONIC SYSTEMS

ALUMINUM PADS

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SIGNAL

~ AMCLICIER u o*T* T

DAC

MTA

m PROCESIOl

OUTPUT

~

-

CONTROLS U

MCtlVER

~

INTERFACE

-

1

\

ELECTRODE ARRAY ~

,

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Fig. 1 . Block diagram of stimulator.

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k - 4 0 mils

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mils

40 m i l s 4

Fig. 2 . IC bonding area.

TABLE 1 SYSTEhl P 4 R T

Component

LIST

n

Quantity

Size (mil)

FunctioniValue

4 5

20 x 20 x IS 20 x 20 x 15 SO x 40 x 40 50 x 40 x 40 SO x 40 x 40 IS0 x 50 x so 80 x 70 x 15 174 x 136 x 15 130 x 122 x IS

Rectifier Tim i ng Timing. 100 pF. 470 pF DAC. 0.01 p F Output. 0.01 pF Power supply. 0. I pF active device active device active device

Diode Resistor Capacitor Capacitor Capacitor Capacitor Receiver Processor DAC chip

7

9 8 1 1

I 2

bond vire (40mils)

U Diode or resistor die (20x20 mils)

substrate pads (10x10 mils)

Fig. 3. Bonding of diode or resistor die.

an IC chip), the substrate pad should be at least 40 mil away from the chip, corresponding to a bond angle of 20". The real area occupied by each IC chip of size X x Y mil is thus ( X 80) X ( Y 80) mil (Fig. 2). The space around the IC of course can be used for conductors on the substrate, but this extra area must be considered in IC attachment and bonding. The four diodes and five resistors do not occupy as much space since these chips have more flexible pad arrangements (Fig. 3 ) . Each diode requires only one bond, with the substrate serving as the second terminal already electrically connected to a bond pad. The pad arrangement of the resistors permits bonding on one side of the chip. Each of these diode or resistor chip thus needs only an area of 60 X 30 mil on the substrate.

+

+

B. Capacitor Attachment The capacitor size most often used in the system design is 50 X 40 X 40 mil. Fig. 4 depicts the conventional attachment of a capacitor on a substrate with bonding pads designed to accommodate wire bonds and allow for epoxy flow during attachment. The real surface area occupied by the capacitor is now 80 x 50 mil. We note again that this area is twice as large as that given in Table I. The total surface area for all components, calculated based on these rules is Area (capacitors) = 86 800 mil'

( la)

Area (signal processing IC's)

=

163 704 mil'

(Ib)

Area (diodes and resistors)

=

16 200 mil'

( IC)

Assuming an average packing density of 30%, the allocated area should be on the order of 889 013 mil', cor-

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CA PAC ITOR TERM1 NATION (PALLADIUM -SILVER)

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3

50 mils

mi$

Fig. 4. Conventional capacitor attachment.

responding to a 1.064 in-diameter substrate. A final package, coated with biocompatible materials and containing this substrate, would measure approximately 1.2 inches in diameter, which clearly exceeds the maximum size specification by almost 2 0 % . These simple calculations show that the standard single-sided single-substrate assembly fails to meet the size restriction. We are thus led to consider two alternatives to increase surface area without increasing the package size: a double-sided single-substrate design and a singlesided double-substrate design. Both of these schemes double the available surface area given a fixed diameter. IV . DOUBLE-SIDED SINGLE-SUBSTRATE DESIGN The double-sided single-substrate design, illustrated in Fig. 5 , achieves size reduction by a natural separation of components: all the IC's are attached on one side, and all the capacitors are attached on the other. The two sides communicate with each other by feedthrough conductors. The feedthrough conductors are fabricated by using stan-

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ponents, and the only remaining problem is the inter-substrate connections. Depending on the distance between the Integrayd circuits. two substrates, there are two possible designs: one with spacers between the substrates and the other without. The design with spacers, illustrated in Fig. 6(a), uses gold posts to connect the substrates and also to support the upper one. The size of each substrate needs to be increased to take into account the areas of the posts, and the I I distance between the two substrates should be large Fig. 5 . A double-sided single-substrate design. enough to facilitate circuit probing during debugging and testing. The size calculation is similar to that presented dard photoresists with wet etchants (e.g., gold etchant [ 5 ] ) above: to define 5-mil pads to cover the hire1 thru-holes. The new Area (signal processing IC’s) = 163 704 mil’ diameter size is calculated as follows: (3a) Area (single processing IC’s) = 163 704 mil’

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Area (diodes and resistors)

(2a)

=

16 200 mil’ (3b)

Area (diodes and resistors) = 16 200 mil2 Area (40 10-mil diameter posts)

(2b) Area (40 holes with 5-mil pads)

=

=

3142 mil’ (3c)

IO00 mil’ (2c)

Total area (with 30% packing density) = 610 153 mil’ (3d)

Total area (with 30% packing density) = 603 013 mil’ Diameter = 0.881 in

(2d)

(3e)

Diameter = 0.876 in

The height calculation assumes 10-mil thick substrates, a 50-mil clearance required for component height, a 50-mil thick package wall, and a 15-mil thick package lid. The estimated height, estimated by going from top to bottom, is

(2e) This figure is quite promising and the design was adopted until we encountered further problems in substrate assembly and testing: 1) After the components have been attached on one side, how can the other side be assembled? For example, if the IC’s have been bonded, it would take not only a skillful operator but also special mechanical jigs to flip the substrate and attach the capacitors without disturbing the other side. 2) Testing each side of the substrate during assembly is reasonably straightforward but the overall system test is quite difficult since a special test jig is required to probe the bottom side. The probe contacts must be reliably made, especially during high-temperature bum-in and other reliability tests conducted according to the standard MIL-STD-883B [4]. 3) The components on the bottom side complicate the package design. Spacers must be provided so that these components do not touch the package surface. It is not impossible to fabricate handling tools and special packages, but given these difficulties, other designs should be considered.

Height ( 2 substrates)

=

20 mil

Clearance ( 2 substrates) = 100 mil

(4a) (4b)

+ IC’s)

=

65 mil

(4c)

Package wall and lid

=

65 mil

(4d)

Height (capacitors

which adds up to 0.250 in, and does not leave sufficient height for the connections of the radio-frequency coil, the acoustic transducer acting as the signal receiver, and the biocompatible package coat. These components add approximately 0.050 in to the package height, thus the final package would exceed the height specification of 0.250 in by almost 2 0 % . The design with no spacers, illustrated in Fig. 6(b), does not look promising at all since the upper substrate takes up surface area of the lower one, thus negating the area gained in using two substrates. It is almost certain that neither of these two designs would meet the size specification, and we are led to consider an unconvenV . DOUBLE-SUBSTRATE DESIGNCONSIDERATIONS tional scheme in package One valuable fact gleaned from the experiments with VI. DOUBLE-SUBSTRATE DESIGNSOLUTION the double-sided design discussed above is the advantage The separation of the IC’s and the capacitors, despite of separating the IC’s from the capacitors. The doublesubstrate design assigns one substrate to each set of com- the failures of the above techniques, seems to be a step in

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SOMA: SIZE REDUCTION OF IMPLANTABLE BIOELECTRONIC SYSTEMS INTEGRATE0 CIRCUITS

UPPER

Fig. 6 . Two possible double-substrate configurations: (a) with apacera. (b) without spacers.

GOLD BOND CAPACITOR TERM I NATION

6 lnllri7; -

CAPACITOR TERM1 NAT IO

50 mils -mi$

( a ) HORIZONTAL ATTACHMENT ( SURFACE AREA = 80 x 50 mils)

(b) VERTICAL ATTACHMENT (SURFACE AREA = 50 x 50 mil$)

-

Fig. 7. Capacitor attachment comparison

the right direction, and the critical question now is the component attachment procedure which would avoid the problems mentioned. There is no flexibility in IC attachment on a substrate, except where the placement is concerned. However, a closer inspection shows that a capacitor may be attached in two different ways: the standard horizontal attachment and the unconventional vertical attachments. Fig. 7 illustrates the obvious and drastic difference in surface area between the two methods of attachments: 2500 mil2 for vertical versus 4000 mil’ for horizontal. Not so obvious is the bonding of a standing capacitor to other circuit components. Optimal bonding, defined under the criterion of minimum wasted surface area, is accomplished by making the center IC substrate thicker (40mil thick) to compensate for the capacitor height (Fig. 8). A bond length of 40 mil requires only a 20-mil separation between the capacitor edge and the substrate pad, a 50% reduction compared to the standard 40-mil distance. The vertical capacitor attachment, together with the thicker center substrate, appears to provide a new doublesubstrate configuration as a solution to our problem. The tradeoffs between the different substrate designs (see Table 11) show that the new double-substrate design meets the size requirements without the difficulties in testing and assembly associated with other schemes discussed above. Package design, which was a major issue with the single-

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40 mils

LOWER ~UBSTRATE

(CAPACITORS)

*

2 0 mil8

INTEGRATED

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Fig. 8. A new double-substrate configuration

substrate double-sided scheme, turns out to be a straightforward process to be explained after we specify the capacitor attachments. A . Capacitor Attachment Techniques 1 ) The power supply capacitor, too tall to be stood up without exceeding the package height restriction, is the only one attached horizontally. Two gold-plated Kovar posts (to be referred to simply as “gold” post hereafter) serve as bonding points for the capacitor terminals. Since one terminal is ground, this connection also establishes a ground bus line on the capacitor substrate without any additional bond. 2) The two timing capacitors are vertically attached and connected as follows: one wire is bonded to the gold tab

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on top of each capacitor, and the other wire te the gold post in electrical contact with the bottom terminal. 3 ) The nine DAC capacitors are vertically attached and connected to the IC substrate via gold tabs and bonds. The bottom terminals, sitting on the ground bus line. require no bond. 4) Eight output capacitors. whose tops are bonded via the usual tab. stand on the output Tantalum pins connecting with the electrode array outside the package (Fig. 9 ) . Thanks to this attachment technique. these 8 large capacitors consume zero actual surface area. All the 20 capacitors listed in Table I have been accounted for, and a photograph of the actual attachments of the DAC and output capacitors is shown in Fig. 10. This figure also shows part of the lower substrate design. which will be discussed in the next section.

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TOP SUBSTRATE

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B. Substrate Desigil aria' Fahrictitioti With the burden of the capacitors disposed of bj' vertical attachment, the design of the double ceramic substrates is straightforward. The major goal is to partition the components between the two substrates to facilitate assembly and reliability testing. The difTerence in methods to test active and passive components suggests a natural partition: one substrate containing all the active c o n ponents and the other all the passive components. This partition is adopted in the layout of the two substrates and results in an active center substrate (0.570 in diameter x 0.040 in thick) and a passive lower substrate (0.780 in diameter X 0.010 in thick). The fabrication process is a thin-film process that features a two-metal system: aluminum for connection from the IC pad to bond wire to substrate pad. and gold for the substrate conductors. T o provide continuity between the aluminum pads and the gold conductor lines, large overlapping areas ( 10 x 15 mil minimum) are defined on the center IC substrate. which guarantee good conduction despite metallic difference, and long lifetime since the effective current density is very low in these areas and is not likely to create interface problems between the two metals. The substrate fabrication incorporates the two-metal system in a five-mask process. The center IC substrate requires three masks: aluminum pad definition. gold conductor, and passivation. The capacitor substrate. which does not require any aluminum pad. needs only two masks: gold conductor and passivation. The substrates. after assembly and bonding, are shown in Fig. 1 1 . I t should be noted that the notch at the edge of the center IC

substrate (near the top of the figure) and the pins sticking through the capacitor substrate are the results of the mechanical considerations in the design of the containing case to be discussed below. V I I . P.\CK.AGIYG DFsicix The preceding description of the capacitor attachments and substrate fabrications has also revealed a few features of the package: feedthrough pins at the bottom and a metal can. In this section. these features are integrated into a comprehensive design to satisfy the size constraint as well as the requirements of hermeticit! and reliability. In general. the package consists of four components: a titanium can (0.880 in outer diameter x 0.190 in total height ). a titanium lid for top sealing, 12 tantalum feedthrough pins (0.037 in diameter). and glass for sealing the pins to the bottom of the can. All these components

PIEZOELECTRIC

CRYSTAL

-RADIO-FREQUENCY COIL

c TITANIUM

g -CUSTOM

€2

INTEGRATED CIRCUIT CHIPS

UPPER SUBSTRATE

r T A N T A L U M PINS GLASS HERMETIC TITANIUM CASE

F i f . 1 1 . Final u\scniblq before lid waling

have been proven to be biocompatible 131. Tantalum. in particular, also develops a self-passivating oxide Ta,05. which acts as an added protection for the input/output connections. The design of the tantalum pins is purely mechanical. The four input pins-two for the radio-frequency (RF) coils and two for the ultrasonic transducer-are 0.131 in long, protrude 5 mil above the center IC substrate, and are bonded to the substrate conductor lines by gold bonds and tabs as in the case for the capacitor. One input pin. which fits into the notch at the edge of the center substrate, acts as a guide post and defines the orientation of the center substrate relative to the capacitor substrate. Two other input pins are situated tangentially to the center substrate to facilitate its attachment. The eight output pins are shorter (0.088 i n ) and protrude 5 mi! above the capacitor substrate. The top of each pin serves as the attachment pad for one dc-blocking output capacitor. thus simultaneously accomplishes the electrical connection and, as described above, reduces the surface area required for capacitor bonding. All 12 pins emerge unifornily 0.020 in below the can to allow ample space for connections to the electrode array. These feedthrough pins are sealed to the bottom of the titanium can by glass seal chosen to iniprove the package lifetime and reliability. The top of the can is welded to the titanium lid by seam welding in a nitrogen atmosphere. Besides mechanical pcilishing, both sealing surfaces are further smoothed by chemical etching and cleaning. The substrate and package design technique presented so far has incorporated several unconventional features, which must be thoroughly tested during manufacturing to guarantee functionality and reliability. The assembly procedure and manufacturing tests are described in the next section.

VIII. SYSTEM A S S E M B LA~N.D PRODUCIION TESTS The assembly of the electronic stimulator, shown in the schematic drawing (Fig. 12), is a straightforward proce-

Fl:.

12. As\embl) whenlatic

dure. The capacitor substrate is assembled first and checked for the mechanical stability of the capacitor connection by a vibration test 141. The IC substrate is assembled and undergoes bond pull test and electrical functional test. Both substrates are then positioned in the package, guided by the 110 pins as described above. Additional bond pull test and overall system electrical functional test follow before the final lid sealing. Reliability tests (burn in, leak test. thermal shock, etc) according to MIL-STD883B [4) are carried out before lifetime test in a saline environment. The entire assembly before lid sealing is shown in Fig. 1 1 . The results of the lifetime study and reliability of this package have been reported [2] and it should also be clear that the final package size is well within the size limit of 1.000 in diameter by 0.250 in height imposed on the stimulator.

I X . CoNcr.usro~ This paper has presented a package design technique to reduce the size of an electronic system for a medical application. The severe constraint on system size makes it impossible for the conventional packaging schemes (based on horizontal capacitor attachment and described in Sections IV and V ) to succeed, and the new design technique relies on several innovations: vertical capacitor attachment, a thick substrate to compensate for this added height and simultaneously reduce area loss due to bonding requirements, and an inputloutput pin design to exploit the advantage of standing capacitors. These unusual features are extensively tested to guarantee functionality and reliability, and can be extended to other electronic package designs wherever size constraint is a critical requirement. ACKYOWLEDGMENT Vitare] Incorporated (San Diego. California) provided facilities for production tests and package sealing. Work performed at the Stanford Electronics Laboratories (Stanford. California). The constructive criticism of the re-

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viewers has been very helpful in the presentation of this work.

161 R. E. Suarez cf al.. “An all-MOS charge-redistribution AID conversion technique-Pan 11.” lEEE J . Solid Sfare Circ., vol. SC-IO. no. 6 , pp. 379-385, 1975.

REFERENCES [ I ] M . Soma, “Design and fabrication of an implantable multichannel neural stimulator,’’ Tech. Rep. G 908-1, Dep. Elect. Eng., Stanford Univ. Stanford, CA, June 1980. [2] -, “Reliability of implantable electronic devices: Two case studies.” lEEE Trans. R e / . , vol. R-35, no. 5 . pp. 483-487, Dec. 1986. [3] P. J. Parks and D . F. Gibbons. “Biocompatibility evaluation of implant materials,’’ presented at Workshop on Implantable Transducers and Syst., Stanford Univ. Stanford, CA. June 1979. [4] U.S. Dep. Defense, “Test methods and procedures for microelectronics MIL-STD-883B.” Govern. Print. Office. Washington. DC. Aug. 1977. [SI S . K. Ghandi. VLSl Fubrirutiori Principles: Silicori aiid Gallium Arsenide. New York: Wiley. 1983. p. 525.

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Mani Soma (S‘74-M’86) received the B S E.E degree from Calitornia State University. Fresno. in 1975, and the M S and Ph D degrees from Stantord University, Stanford, CA, in 1977 and 1980. re\pectively Atter two years at the General Electric Re\earth and Development Center at Schenectady, N Y . he I \ now Associate Professor of Electrical Engineering at the University ot Washington His re\earch intere\t\ include the design. te\t. and reliability characterization of integrated circuit5 and \y\terns