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A frequency response model matching method for PID controller design for processes with dead-time Md Nishat Anwar n, Somnath Pan Department of Electrical Engineering, Indian School of Mines, Dhanbad 826004, India
art ic l e i nf o
a b s t r a c t
Article history: Received 15 May 2013 Received in revised form 23 August 2014 Accepted 30 August 2014 This paper was recommended for publication by Prof. A.B. Rad
In this paper, a PID controller design method for the integrating processes based on frequency response matching is presented. Two approaches are proposed for the controller design. In the first approach, a double feedback loop configuration is considered where the inner loop is designed with a stabilizing gain. In the outer loop, the parameters of the PID controller are obtained by frequency response matching between the closed-loop system with the PID controller and a reference model with desired specifications. In the second approach, the design is directly carried out considering a desired loaddisturbance rejection model of the system. In both the approaches, two low frequency points are considered for matching the frequency response, which yield linear algebraic equations, solution of which gives the controller parameters. Several examples are taken from the literature to demonstrate the effectiveness and to compare with some well known design methods. & 2014 ISA. Published by Elsevier Ltd. All rights reserved.
Keywords: PID controller Integrating process Dead-time Frequency response matching Double feedback loops Load-disturbance rejection
1. Introduction The proportional-integral-derivative (PID) controller has its widespread acceptance in the industrial processes due to its simplicity in understanding and its applicability to a large class of processes having different dynamics. Numerous PID controller tuning methods and rules may be found in [1]. The integrating process is a special class of unstable processes and it attracts special attention of the researchers resulting a different type of PID controller design methods. Chidambaram and Sree [2] have presented an analytical tuning method which is based on finding the parameters of overall transfer function in a transformed domain to have desired set-point response. The PID controller design based on the direct synthesis design (DS) is given by Chen and Seborg [3]. The tuning rule for PI/PID controllers based on the maximum resonance specification is proposed by Poulin and Pomerleau [4]. Visioli [5] has proposed a design method based on an error minimization criteria using the genetic algorithm. Ali and Majhi [6] has presented a design method based on minimization of integral square error (ISE) performance criteria with a constraint on the slope of the Nyquist curve at the gain cross over frequency. Rivera et al. [7] have provided a PID controller tuning method
n
Corresponding author. E-mail addresses:
[email protected] (M.N. Anwar),
[email protected] (S. Pan).
(IMC-PID) based on the internal model control (IMC) principle in which the design parameter is the speed of the closed-loop response. Skogestad [8] has proposed a simple analytic tuning rule for model reduction and a PID tuning rule (SIMC) based on the IMC principle. An extension of the IMC tuning method for the integrating processes may be found in [9]. Shamsuzzoha and Lee [10,11], Chia and Lefkowitz [12] have modeled the integrating processes as stable processes with considerably very large time constants and applied the IMC principle to design PID controllers with improved load-disturbance rejection. An analytical method for PID controller tuning with specified gain and phase margins has been derived in [13]. The PID controller design methods for the integrating processes with inverse response and time-delay may be found in [14–16]. Gu et al. [14] have presented a PI/PID controller design method based on the H1 optimization and the IMC theory. Pai et al. [15] have proposed a PI/PID controller design method using the direct synthesis method for disturbance rejection (DS-d) where speed of the closed-loop response has been optimized via the goldensection searching technique. Jeng and Lin [16] have designed a controller in Smith-type configuration which is then converted into a PID controller in the classical feedback configuration using the Maclaurin series. The methods of Luyben [17], Tyrus and Luyben [18] along with the most accepted PID tuning rule given by Ziegler and Nichols (Z–N) [19] use the frequency response information in tuning the PID controller. These simple and attractive methods use only the critical
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frequency point of the process for tuning the PID controller. However, these methods do not always provide satisfactory controllers for wide variety of processes. Wang and Cluett [20] have presented a method for PID controller design by matching the frequency response of the desired and actual closed-loop responses at two specified frequency points. Vijayan and Panda [21] have designed the PID controllers for low order processes in double feedback loops to achieve stability and improved performance in such a way that the inner feedback loop stabilizes the process using the Z–N tuning rule and the outer loop (tuned by the IMC-PID rule) improves the setpoint response. They [22] have also shown reduction of the overshoot for various types of processes by using suitable set-point filters. In this paper, a PID controller design technique is proposed for the integrating processes, which is based on frequency response matching of the actual and the desired closed-loop systems at two low frequency points. Two approaches are proposed. In the first approach, with a double feedback loop configuration, the inner loop contains a stabilizing gain. In the outer loop, the parameters of the PID controller are obtained by the frequency response matching of the actual model and a desired reference model at two low frequency points. In the second approach, a reference model is chosen for a desired load-disturbance rejection and then the frequency response of the control system is matched with that of the reference model to achieve the desired load-disturbance rejection. The desired closed-loop reference model is chosen considering the design requirement and the process dynamics. The method gives a set of linear algebraic equations, solution of which gives the controller parameters. Though, the frequency response matching is carried at two low frequency points only, a good set-point response as well as load disturbance rejection are achieved. Both the proposed approaches are applicable to a wide range of integrating processes with low or high order that may have dead-time and/or inverse response dynamics. Effectiveness of the proposed method is demonstrated through examples taken from the literature and favorably compared with some of the methods prevalent in the literature. The rest of the paper is organized as follows. In Section 2, the proposed design method is presented in detail. In Section 3, the method is demonstrated through examples. Conclusion is shown in Section 4.
2. The design method An integrating process is considered as shown in Fig. 1 with the following transfer function. GP ðsÞ ¼
N p ðsÞ Ls e sDp ðsÞ
ð1Þ
where, N p ðsÞ=sDp ðsÞ is a rational transfer function and L is the time delay of the system. The zeros of Dp(s) are all in the LHS of the s-plane. The PID controller with the following form is used to d
i
F(s)
e
r –
C(s)
u
x
GP(s)
y
C ðsÞ ¼ K P þ
KI þ KDs s
ð2Þ
where, Kp, K1, and KD are the proportional, the integral and the derivative constants of the controller that are to be determined. In Fig. 1, i is the input, y is the process output, r is the output of the set-point filter F(S), e is the error, u is the controller output, d is the disturbance, n is the measurement noise and x is the excitation to the process. From Fig. 1, the transfer functions from r to y and d to y may be written as, respectively, Gr;y ðsÞ ¼
C ðsÞGP ðsÞ 1 þ C ðsÞGP ðsÞ
ð3Þ
Gd;y ðsÞ ¼
GP ðsÞ 1 þ C ðsÞGP ðsÞ
ð4Þ
The first step of the design procedure is to choose or construct a suitable reference model M r;y ðsÞ which incorporates the desired specifications of the overall control system from r to y. The dynamics of the reference model should be such that it can be achievable by the process dynamics with an implementable controller. For example, dead-time of a process cannot be eliminated in the closed-loop response by any controller. Hence, the reference model is required to contain the dead-time term of the process. Similarly, the inverse response of the process is to be included in the reference model. The proposed method offers the advantage to consider the industrial specifications such as settling time, peak overshoot, etc. in time domain or gain margin, phase margin, band width, etc. in frequency domain or damping factor, undamped natural frequency in complex domain. A good number of procedures for choosing a feasible reference transfer function may be found in [23]. However, from such industrial specifications, we can always analytically construct a reference model of order up to 2 and it works well for the most of the industrial processes. The reference model is constructed as M r;y ðsÞ ¼
N mr ðsÞ Ls e Dmr ðsÞ
ð5Þ
where, Nmr ðsÞ=Dmr ðsÞ is in the form of a rational polynomial. It is obvious that M r;y ðsÞ is required to have a minimum time-delay as that of the process and the non-minimum phase zero of the process, if any. For achieving the desired set-point response of the closed-loop system, the frequency responses of Gr;y ðsÞ and M r;y ðsÞ are matched and may be written as C ðsÞGP ðsÞ Gr;y ðsÞ ¼ ffi M r;y ðsÞs ¼ jω ð6Þ 1 þ C ðsÞGP ðsÞs ¼ jω where, the LHS expression is equivalent with the RHS expression in terms of frequency response and the unknown parameters of the controller C(s)are to be evaluated. The relation (6) may be written as M r;y ðsÞ C ðsÞGP ðsÞs ¼ jω ffi ffi M o ðsÞs ¼ jω ð7Þ 1 M r;y ðsÞs ¼ jω where, M o ðsÞ may be called as equivalent open-loop reference model. Eq. (7) gives sDp ðsÞN mr ðsÞ M o ðsÞ C ðsÞs ¼ jω ffi ¼ ¼ HðsÞs ¼ jω GP ðsÞ s ¼ jω ½Dmr ðsÞ Nmr ðsÞe Ls N p ðsÞs ¼ jω ð8Þ
n
Fig. 1. Unity negative output feedback configuration.
control the integrating processes.
If H(s) could be implemented ideally, it would give the response of Gr;y ðsÞ exactly same as that of the desired model M r;y ðsÞ. But the term e Ls in the expression of H(s) is not suitable for practical implementation. The Pade approximation of e Ls in terms of a rational polynomial gives rise to a rational expression for H(s),
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however, then the increased order of the controller would not be preferred for practical implementation. Moreover, a particular structure, such as PID, may be sought for controlling the process. Hence, C(s), a low-order controller with a particular structure is required to approximate the behavior of H(s). However, Eq. (8) may be written as, C R ðωÞ þ jC I ðωÞ ffi H R ðωÞ þjH I ðωÞ
C R ðωÞ ffi H R ðωÞ and C I ð ωÞ ffi H I ð ωÞ
ð10Þ
In order to force equivalence of two real functions, C R ðωÞ and C I ðωÞ with H R ðωÞ and H I ðωÞ, respectively, one may equate an appropriate number of initial terms of the corresponding Taylor series expansion around ω ¼ 0. Thus, to accomplish matching of the LHS functions in Eq. (10) with the corresponding functions on the RHS, initial N derivatives of the corresponding functions are equated at ω ¼0 to give k k d d ½ ½ C ð ω Þ ¼ H ð ω Þ ; k A ½0; N 1 ð11Þ R R d ωk dωk
ω¼0
ω¼0
; k A ½0; N 1
ð12Þ
ω¼0
It can be shown by using the divided difference calculus as in [24] that the derivative relations in Eq. (11) holds good approximately, if the functions C R ðωÞ and H R ðωÞ are directly matched at around ω ¼ 0; i.e., C R ðωÞ ¼ H R ðωÞ ð13Þ ω ¼ ωk
ω ¼ ωk
where ωk is the small positive values around C I ðωÞω ¼ ω ¼ H I ðωÞω ¼ ω k
ω ¼0. Similarly, ð14Þ
k
It is clear from Eqs. (13) and (14) that N values of ω give 2N linear algebraic equations with the unknown parameters. For 3 numbers of unknowns of the PID controller N is at least equal to 2 and for two frequency points ω0 and ω1 the following expression is obtained as shown in Appendix A. Ax ¼ b where, 2 1 60 6 A¼6 61 4 0
ð15Þ
0 ω10 0 ω11
0
3
2
3
2
H R ð ω0 Þ
Directly from Eq. (15), we get two values of Kp as: K P1 ¼ H R ðω0 Þ; K P2 ¼ H R ðω1 Þ It is observed from various examples, that K P1 K P2 and we may consider the value of Kp as any one of K P1 or K P2 or an average of these. Then, to evaluate the remaining parameters, KI and KD, Eq. (15) may be simplified as A1 x1 ¼ b1
A1 ¼ 4
ω10 ω11
e
r
u C(s)
x
K
G (s)
–
y n
ð16Þ
3
"
#
"
#
ω0 H I ð ω0 Þ KI 5; x1 ¼ ; ; and ; b1 ¼ H KD ω1 I ð ω1 Þ
Then, solution of Eq. (16) determines KI and KD. Thus, the parameters of the PID controller are evaluated. For the integrating processes, the proposed design method gives the integral constant KI ¼0 leading to a PD controller (Appendix B). With this PD controller, the set-point response may be good but it fails to reject the load-disturbance. Thus, to design a PID controller for the integrating processes which would achieve good set-point response as well as load-disturbance rejection, the following two approaches are proposed. 1. Use of double feedback loops as shown in Fig. 2, in which inner loop stabilizes the system with a simple gain K and then the outer loop is designed by following the proposed design method. 2. Instead of designing the closed-loop system Gr;y ðsÞ directly, one may design the control system Gd;y ðsÞ for achieving the desired load-disturbance rejection. This approach requires a suitable reference model M d;y ðsÞ (from d to y) satisfying the loaddisturbance rejection specifications. First approach: A double feedback loop configuration is considered as shown in Fig. 2, with K as the stabilizing gain and its range is 0 oK oK u , where, Ku is the ultimate gain [25] for the integrating process. While designing the outer loop, the parameters of the PID controller are obtained by following the proposed design method, as discussed in Eq. (5)–(16), applied for the system GIN ðsÞ, where GIN ðsÞ is given by: GIN ðsÞ ¼
KGP ðsÞ 1 þ KGP ðsÞ
ð17Þ
Second Approach: In this approach, the reference model (from d to y) M d;y ðsÞ is constructed for a desired load-disturbance rejection as follows. M d;y ðsÞ ¼
3
KP 6 7 6 H I ð ω0 Þ 7 7 6 7 7; x ¼ 6 K ; and ; b ¼ I 4 5 6 H R ð ω1 Þ 7 0 7 4 5 5 KD ω1 H I ð ω1 Þ
ω0 7 7
F(s)
–
where, 2
and C R ðωÞ; C I ðωÞ; H R ðωÞ and H I ðωÞ are the real functions of ω. Separating the real and the imaginary parts, Eq. (9) may be written as:
k d ½H I ðωÞ ¼ k dω
i
Fig. 2. Control system configuration with double feedback loops.
s ¼ jω
ω¼0
d
ð9Þ
where, C ðsÞs ¼ jω ¼ C R ðωÞ þ jC I ðωÞ ¼ H R ðωÞ þ jH I ðωÞ HðsÞ
k d ½C I ðωÞ k dω
3
Nmd ðsÞ Ls e Dmd ðsÞ
ð18Þ
where N md ðsÞ=Dmd ðsÞ is a rational transfer function and the reference model M d;y ðsÞ must have one zero at origin so as to achieve load-disturbance rejection. The numerator of M d;y ðsÞ is required to contain a minimum time-delay as e Ls and nonminimum phase zeros of the process, if any. Following the proposed design method, Eq. (6) is to be modified as GP ðsÞ Gd;y ðsÞ ¼ ffi M d;y ðsÞs ¼ jω ð19Þ 1 þ C ðsÞGP ðsÞs ¼ jω and Eq. (19) may be simplified as 1 1 C ðsÞs ¼ jω ffi M d;y ðsÞ GP ðsÞ s ¼ jω
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ffi
N p ðsÞDmd ðsÞ Dp ðsÞN md ðsÞ ¼ HðsÞs ¼ jω N p ðsÞN md ðsÞe Ls s ¼ jω
ð20Þ
The rest of the design procedure is as per Eqs. (9)–(16) to determine the values of K P ; K I and K D .
2.1. Selection of frequency points Generally, the industrial processes show dominantly low-pass dynamics in terms of the frequency response. For such cases, the low frequency region is more important and frequency response matching at ω-0 ensures the desired steady-state response. As per Eqs. (13) and (14) the frequency points for matching purpose are required to be sufficiently small. With this consideration both the frequency points are selected very small values. The theoretical range of the frequency for the frequency response is from 0 to 1 and it is meaningless to find a ‘small’ number with respect to this infinite range. Here, the small values of frequency points are proposed to choose with respect to the bandwidth frequency (ωb) of the desired reference model, where the bandwidth may be treated as an indication to the effective range of frequency response. This has been further elaborated in the illustration of Example 1 in Section 3.
3. Simulation results Software simulation has been carried for various examples of the processes taken from the literature. Set-point responses are shown for unit-step input. Load-disturbance rejections are shown for unit-step disturbance applied at the process input after the setpoint responses attain the steady-state. Controller outputs are shown for similar conditions. The performances in terms of peak overshoot (OS), settling time (ts), integral square error (ISE) for the set-point responses; maximum process output (yp), settling time (ts) and ISE for the load-disturbance responses; gain margin (GM), phase margin (PM) and maximum sensitivity (Ms, which is a measure of the robust ness and is defined as M s ¼ max ½1 þ CðjωÞGðjωÞ 1 ) are com0rωr1
puted. A lower value of the maximum sensitivity is preferred in the range of 1.2–2.0 [1]. Further, to show the robustness of the proposed control systems þ10% changes in the gain and the time-delay of the processes are simultaneously considered and the corresponding responses for the perturbed processes are shown. To study the effect of the measurement noise the Gaussian noise with a variance of 0.005 is introduced after the set-point response attains the steady-state and the corresponding responses are plotted. All the results are compared with some of the methods prevalent in the literature.
2.2. Set-point filter 3.1. Example 1 In the process industries, load-disturbance rejection is more important than the set-point tracking and a high load-disturbance rejection sometime results into a highly oscillatory set-point response associated with large peak overshoot. In such case, a set-point filter, F(s) may be incorporated in the control system, as shown in Figs. 1 and 2, to reduce the peak overshoot as well as the oscillation in the set-point response. This gives rise to a twodegree-of-freedom controller, where F(s) works as a set-point weighting without degrading the load-disturbance rejection control. The most simple structure of the set-point filter may be taken as FðsÞ ¼ 1=ðλs þ 1Þ, where the time constant λ is to be chosen judiciously. A large value of λ reduces the peak overshoot and oscillation at the cost of the speed of the set-point response. For the integrating processes, it is observed that improved result occurs for 0 o λ o t s =4, where ts is the settling time of the closed-loop control system without the filter. The peak overshoot (OS) and the settling time (ts) of the closedloop control system without the filter and λ of the filter for each example are shown in Table 1. The value of λ is adjusted through simulation to have improved set-point response. It is observed from Table 1 that the values of λ have been obtained within ts/4 of the corresponding examples.
Method
Example 1 Proposed Proposed Example 2 Proposed Proposed Example 3 Proposed Proposed Example 4 Proposed Proposed Example 5 Proposed Proposed
Set-point response before employing the filter
C1 C2 C1 C2 C1 C2 C1 C2 C1 C2
GP ðsÞ ¼
e 4s sðs þ 1Þ
First approach: The gain K is taken as 0.15 with the peak overshoot as 23.9% and the settling time as 37.2 s for the inner closed-loop response. For the design of the PID controller in the outer loop the reference model M r;y ðsÞ is chosen as given by M r;y ðsÞ ¼
e 4s 2s þ1
The frequency points are chosen as ω0 ¼0.01 rad/s and ω1 ¼ 0.02 rad/s and the proposed design method yields the PID controller C1 as C1ðsÞ ¼ 0:6661 þ
0:1666 þ 3:037s s
The set-point filter has been found as FðsÞ ¼
1 2:2s þ 1
Second approach: For the purpose of design, the reference model M d;y ðsÞ for load-disturbance rejection is chosen as
Table 1 Set-point filter selection. Example
An integrating second order plus dead-time (ISOPDT) process is taken from Ali and Majhi [6] as given by
OS (%)
ts (s)
ts/4 (s)
35 43.4 7.3 89.2 34.5 74 17.5 63.0 18.1 75.9
33.7 59.5 40.5 57.8 59.5 81.4 11.2 8.5 14.2 24.8
8.4 14.9 10.1 14.5 14.9 20.4 2.8 2.1 3.6 6.2
λ of Filter 1/(λsþ 1)
2.2 12 1.5 11.5 2.5 17 1.5 2 12 5
M d;y ðsÞ ¼
120se 4s ð5s þ 1Þð15s þ 1Þ
which gives the peak amplitude of the process output as 4.53 and the settling time as 78.6 s for unit step load-disturbance. The frequency points are chosen as ω0 ¼0.01 rad/s and ω1 ¼0.02 rad/s for frequency response matching and the proposed design method yields the PID controller C2 as follows. C2ðsÞ ¼ 0:20 þ
0:0083 þ 0:357s s
The set-point filter has been found as FðsÞ ¼
1 12s þ1
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1.4
5
10
1.2
Proposed C1 Proposed C2 Ali and Majhi SIMC
8
1
0.6
Amplitude
Amplitude
6
Proposed C1 Proposed C2 Ali and Majhi SIMC
0.8
2
0.4
0
0.2 0
4
0
-2
50
150
100
Time (sec)
200
Time (sec)
Fig. 3. Process output for Example 1; (a) Set-point response, (b) Load-disturbance response.
0.3
Proposed C1 Proposed C2 Ali and Majhi SIMC
0
Amplitude
0.2
Amplitude
0.5
Proposed C1 Proposed C2 Ali and Majhi SIMC
0.25
0.15 0.1
-0.5
-1
0.05 -1.5
0 -0.05
0
-2
50
100
150
Time (sec)
200
Time (sec)
Fig. 4. Controller output for Example 1; (a) During set-point response, (b) During load-disturbance response.
1.5
10 Proposed C1 Proposed C2 Ali and Majhi SIMC
6
1
Amplitude
Amplitude
8
4 2
0.5
Proposed C1 Noise Signal Proposed C2 Ali and Majhi SIMC
0 0
-2
0
50
100
150
200
Time Fig. 5. Process output for perturbed system in Example 1.
The proposed methods have been compared with the methods of Ali and Majhi [6] and SIMC [8] and the various simulation results are shown in Figs. 3–6 and Table 2. Proposed controller C1 gives the best set-point as well as disturbance rejection responses whereas proposed C2 gives the best controller output. Controller output for proposed C1 is comparable to the other methods for set-point response. For perturbed process, C1 gives the best set-point response whereas C2 gives the best disturbance-rejection response. Overall response in terms of ISE is the best by C1. The effect of the measurement noise is found to be negligible in the process output.
-0.5
0
20
40
60
80
100
120
140
Time Fig. 6. Process output for Example 1 with the measurement noise.
3.1.1. Choice of frequency points selected Various pairs of frequency points are chosen for the design procedure and the obtained PID controller parameters are tabulated in Table 3. t is observed from this table that as long as the values of the frequency points are within a small percentage say, 0.1–10%, of the bandwidth frequency the parameter variation of the obtained controllers is insignificant, which gives negligible differences in the responses. With such observation from this example along with the other examples followed a common pair
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Table 2 Performance comparison for Example 1. Method
Controller parameters
Proposed C1 (double loop) Proposed C2 (single loop) Ali and Majhi [6] (single loop) SIMC [8] (single loop)
KP
KI
KD
0.6661 0.20 0.19 0.13
0.1666 0.0083 0.0084 0.0039
3.037 0.357 0.53 0.126
GM (dB)
7.05 5.92 5.10 9.36
PM (deg)
63.4 41.5 51.8 46.8
Ms
Set-point response
1.33 1.40 1.43 1.26
Load-disturbance response
OS (%)
ts (s)
ISE
yp
ts (s)
ISE
2.6 0.5 26 30
25.8 43.9 59.8 81.5
6.818 10.35 7.899 8.87
6.25 6.70 6.32 8.76
44.2 102.5 77.2 155.5
196.2 402.4 400.8 1214
Set-point filter F(s)
1/(2.2s þ 1) 1/(12sþ 1) – –
Table 3 Parameters of the PID controllers designed with various sets of frequency points for Example 1. First approach ωb ¼ 0:49 rad=s rad/s
Second approach ωb ¼ 0:26 rad=s
S. no.
ω0
ω1
KP
KI
KD
S. no.
ω0
ω1
KP
KI
KD
1 2 3 4
0.005 0.01 0.04 0.1
0.01 0.02 0.08 0.2
0.6665 0.6661 0.6578 0.6528
0.1667 0.1666 0.1667 0.1670
3.033 3.037 3.044 3.079
1 2 3 4 5
0.0002 0.002 0.005 0.01 0.04
0.0004 0.004 0.01 0.02 0.08
0.20 0.20 0.20 0.20 0.20
0.0083 0.0083 0.0083 0.0083 0.0084
0.333 0.350 0.366 0.357 0.399
1.6 1.5
1.2
1.4
1
1.3
Amplitude
Amplitude
1.4
0.8 0.6
Proposed C1 Proposed C2 Ali and Majhi Chidambaram and Sree
0.4 0.2 0
0
50
Proposed C1 Proposed C2 Ali and Majhi Chidambaram and Sree
1.2 1.1 1 0.9
100
150
Time (sec)
200
Time (sec)
Fig. 7. Process output for Example 2; (a) Set-point response, (b) Load-disturbance response.
of frequency values, i.e., ω0 ¼0.01 rad/s and ω1 ¼ 0.02 rad/s is taken for all the examples. This means, ω0 is taken in the range of 0.2–7.2% of the bandwidth frequencies of the corresponding reference models. However, in general the choice of frequency points in the range of 0.1–10% of the bandwidth frequency has been observed to give good results for the most of the processes.
An integrating plus dead-time (IPDT) process is considered from the literature [6] as given by 0:0506 6s e s
First approach: The gain K is taken as 1.5 that gives the peak overshoot as 1.5% and the settling time as 24.8 s for the inner closed-loop system. In order to design the outer loop the reference model M r;y ðsÞ with the settling time as 42 s is chosen as M r;y ðsÞ ¼
e 6s 6s þ 1
The obtained PID controller C1 is as given below. C1ðsÞ ¼ 0:7231 þ
FðsÞ ¼
1 1:5s þ 1
Second approach: The reference model M d;y ðsÞ for the loaddisturbance rejection is chosen as M d;y ðsÞ ¼
3.2. Example 2
GP ðsÞ ¼
The set-point filter has been found as
0:0833 þ2:33s s
4s e 6s ð5s þ 1Þð6:3s þ 1Þ
which gives the peak amplitude of the process output as 0.26 and the settling time as 35.5 s for unit step load-disturbance. The design procedure yields the PID controller C2 as C2ðsÞ ¼ 4:32 þ
0:24 þ 9:46s s
The set-point filter has been found as FðsÞ ¼
1 11:5s þ 1
The proposed methods have been compared with the methods of Chidambaram and Sree [2], Ali and Majhi [6] and the various simulation results are shown in Figs. 7–10 and Table 4. The controller C1 gives the best set-point response while C2 gives the best load-disturbance response. Controller outputs of C1 and C2 are equally better than the other methods. The GM–PM
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Proposed C1 Proposed C2 Ali and Majhi Chidambaram and Sree
0 -0.5
Amplitude
2
Amplitude
0.5
Proposed C1 Proposed C2 Ali and Majhi Chidambaram and Sree
4
7
0
-1 -1.5
-2
-4
-2
0
-2.5
50
100
150
Time (sec)
Time (sec)
Fig. 8. Controller output for Example 2; (a) During set-point response, (b) During load-disturbance response.
transfer function as
2
GP ðsÞ ¼
Amplitude
1.5
First approach: The inner loop gain is selected as 0.15 which gives the peak overshoot as 44.5% and the settling time as 87.4 s for the inner closed-loop system. The reference model is chosen as
1 Proposed C1 Proposed C2 Ali and Majhi Chidambaram and Sree
0.5
0
0
50
100
150
M r;y ðsÞ ¼ 200
Time
The design procedure gives the PID controller C1as 0:132 þ 6:16s s
The set-point filter has been found as
2
FðsÞ ¼
1.5
Amplitude
1 e 4s ð0:6s þ 1Þð3s þ1Þ
C1ðsÞ ¼ 0:457 þ
Fig. 9. Process output for perturbed system in Example 2.
1 2:5s þ 1
Second approach: The reference model for load-disturbance rejection is chosen as
1 0.5
Proposed C1 Noise Signla Proposed C2 Ali and Majhi Chidambaram and Sree
0 -0.5
e 4s sð4s þ1Þ
0
20
40
60
M d;y ðsÞ ¼
120s e 4s ð5s þ 1Þð20s þ 1Þ
The PID controller C2 has been obtained as 80
100
120
C2ðsÞ ¼ 0:2348 þ
Time Fig. 10. Process output for Example 2 with the measurement noise.
The set-point filter has been found as FðsÞ ¼
and Ms (the maximum sensitivity) are the best with C1. C2 is giving the minimum ISE for the load-disturbance response while for setpoint response ISE of C2 is comparable with the others. Distinct improvement by the controllers C1 and C2 may be observed for the perturbed process. The effect of measurement noise is reduced considerably in the process output by the proposed methods as well as by the other methods in a similar way.
3.3. Example 3 An example of an integrating second order plus dead-time (ISOPDT) process is taken from [21] where the process has the
0:0083 þ 0:540s s
1 17s þ1
The proposed methods have been compared with the methods of Vijayan and Panda [21] and Shamsuzzoha and Lee [11] and the various simulation results are shown in Figs. 11–14 and Table 5. The controller C1 gives the GM–PM and the Ms comparable with the others and the minimum ISE for the set-point response. C2 gives a comparable load-disturbance response. The controller output by C2 is remarkably good. For the perturbed process, the performance by C1 and C2 are comparable. Here, the method of Shamsuzzoha and Lee [10] gives the best load-disturbance response for the nominal as well as perturbed processes with the help of a PID controller cascaded with a lead compensator. The effect of the measurement noise is found to be negligible in the process output.
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Table 4 Performance comparison for Example 2. Controller parameters GM (dB) PM (deg) Ms
Method
Proposed C1 (double) Proposed C2 (single loop) Ali and Majhi [6] (single loop) Chidambaram and Sree [2] (single loop)
KP
KI
KD
0.7231 4.32 3.39 4.06
0.0833 0.24 0.17 0.15
2.33 9.46 9.96 10.97
Set-point response Load-disturbance response OS (%)
12.16 2.78 4.09 2.72
68.1 26.4 42.5 36.6
1.44 0 1.80 5.15 1.53 51 1.78 59
1.4
ts (s)
ISE
yp
ts (s)
ISE
28.5 43.3 50.6 69.4
10.23 10.24 10.62 10.02
1.42 1.33 1.34 1.32
41.35 39.5 41.4 64.1
2.46 0.9083 1.26 1.15
1/(1.5s þ1) 1/(11.5sþ 1) – –
8
Proposed C1 Proposed C2 Vijayan and Panda Shamsuzzoha and Lee
1.2 6
1
Proposed C1 Proposed C2 Vijayan and Panda Shamsuzzoha and Lee
0.8 0.6
Amplitude
Amplitude
Set-point filter F(s)
4
2
0.4 0
0.2 0
0
-2
50
100
150
Time (sec)
200
Time (sec)
Fig. 11. Process output for Example 3; (a) Set-point response, (b) Load-disturbance response.
0.4
0.2
0.1
0
Proposed C1 Proposed C2 Vijayan and Panda Shamsuzzoha and Lee
0
Amplitude
Amplitude
0.3
-0.1
0.5
Proposed C1 Proposed C2 Vijayan and Panda Shamsuzzoha and Lee
-0.5
-1
-1.5
0
50
-2
100
150
Time (sec)
200
Time (sec)
Fig. 12. Controller output for Example 3; (a) During set-point response, (b) During load-disturbance response.
3.4. Example 4
The design procedure gives the PID controller C1 as
An integrating second order plus dead-time (ISOPDT) process with non-minimum phase zero is taken form [11] as GP ðsÞ ¼
0:547ð 0:418s þ 1Þe sð1:06s þ 1Þ
0:1s
First approach: The inner loop gain K is selected as 0.5 to have the overshoot as 1.6% and the settling time as 7.3 s. The reference model is chosen as M r;y ðsÞ ¼
0:418s þ 1 0:1s e 0:5s þ 1
C1ðsÞ ¼ 3:128 þ
0:9823 þ3:9966s s
The set-point filter has been found as FðsÞ ¼
1 1:5s þ 1
Second approach: The reference model M d;y ðsÞ for loaddisturbance rejection is chosen as M d;y ðsÞ ¼
ð 0:418s þ 1Þs 0:1s e ðs þ1Þð2s þ 1Þ
which gives the peak amplitude of the process output as 0.24 and the settling time as 10.7 s. The design procedure yields the PID
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controller C2 as
8
Proposed C1 Proposed C2 Vijayan and Panda Shamsuzzoha and Lee
Amplitude
6 4
C2ðsÞ ¼ 3:5184 þ
1:000 þ1:950s s
The set-point filter has been found as 1 2s þ 1
2
FðsÞ ¼
0
The proposed methods have been compared with the methods of Shamsuzzoha and Lee [11], Gu et al. [14] and Luyben [17] and the various simulation results are shown in Figs. 15–18 and Table 6. The controller C2 gives the best set-point response while C1 gives the best load-disturbance response. With comparable GM, PM and Ms the controller C1 generates the best controller output during load-disturbance. Favorable response may be observed by the proposed controllers for the perturbed process. The effect of measurement noise is reduced considerably in the process output by the proposed methods as well as by the other methods in a similar way.
-2
0
50
100
150
200
Time Fig. 13. Process output for perturbed system in Example 3.
1.5
1
Amplitude
9
3.5. Example 5
0.5
Proposed C1 Noise Signal Proposed C2 Vijayan and Panda Shamsuzzoha and Lee
0
-0.5
An example of a high order integrating plus dead-time process with non-minimum phase zero is taken from the literature [16] as GP ðsÞ ¼
0
20
40
60
80
100
Time
0:5ð 0:5s þ 1Þe 0:7s sð0:4s þ 1Þð0:1s þ 1Þð0:5s þ 1Þ
First approach: The gain K in the inner loop is selected as 0.5 to have the peak overshoot as 7.2% and the settling time as 13.3 s.
Fig. 14. Process output for Example 3 with the measurement noise.
Table 5 Performance comparison for Example 3. Method
Controller parameters KP
Ms
PM (deg)
KD
29.1
1.67 1.01
23.2
0.029
0.97
3.35
1.4
0.6
Proposed C1 Proposed C2 Shamsuzzoha and Lee Gu et al Luyben 10
Time (sec)
9.905 4.17
31.5
Set-point filter F(s)
ISE
0.359
0.8
0
ts (s)
49.2 7.794 6.05 95.1 264.5 46.4 12.60 6.8 128.2 542.7 18.1 7.977 6.8 125.4 414.3
1.5
-0.2
yp
1.33 5.5 1.66 2.4 1.20 1.01
1
0
ISE
62.6 22.8 62.7
1.6
0.2
ts (s)
Load-disturbance response
0.457 0.132 6.160 7.15 0.2348 0.0083 0.540 4.91 0.49 0.122 4.733 10.52
1.2
0.4
Set-point response
OS (%)
Amplitude
Amplitude
Proposed C1 (double loop) Proposed C2 (single loop) Vijayan and Panda [21] (double loop with K¼ 0.1318) Shamshuzzoha and Lee [11] (single loop; PID with lead compensator)
KI
GM (dB)
1/(2.5s þ1) 1/(17s þ 1) 1/(2.1sþ 1)
74.29 1/ (32.81s2 þ 12.13sþ 1)
Proposed C1 Proposed C2 Shamsuzzoha and Lee Gu et al Luyben
1.3 1.2 1.1 1
20
0.9 20
30
40
50
Time (sec)
Fig. 15. Process output for Example 4; (a) Set-point response, (b) Load-disturbance response.
Please cite this article as: Anwar MN, Pan S. A frequency response model matching method for PID controller design for processes with dead-time. ISA Transactions (2014), http://dx.doi.org/10.1016/j.isatra.2014.08.020i
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2
2
Proposed C1 Proposed C2 Shamsuzzoha and Lee Gu et al Luyben
Amplitude
1
1 Amplitude
1.5
Proposed C1 Proposed C2 Shamsuzzoha and Lee Gu et al Luyben
1.5
0.5
0.5 0 -0.5 -1
0 -1.5 -0.5
0
10
-2 20
30 Time (sec)
Time (sec)
Fig. 16. Controller output for Example 4; (a) During set-point response, (b) During load-disturbance response.
The set-point filter has been found as
2
FðsÞ ¼
Amplitude
1.5
Second approach: The reference model M d;y ðsÞ for loaddisturbance rejection is chosen as
1
Proposed C1 Proposed C2 Shamsuzzoha and Lee Gu et al Luyben
0.5 0 -0.5
0
10
20
30
40
M d;y ðsÞ ¼
50
Fig. 17. Process output for perturbed system in Example 4.
FðsÞ ¼
1 0.8
Amplitude
which gives the peak amplitude of the process output as 0.65 and the settling time as 26.3 s for unit step load-disturbance. The design procedure yields the PID controller C2 as
Proposed C1 Noise Signal Proposed C2 Shamsuzzoha and Lee Gu et al Luyben
0.4 0.2 0 -0.2 0
10
20
30
40
0:16 þ 1:20s s
The set-point filter has been found as
1.2
0.6
6ð 0:5s þ 1Þs 0:7s e ð5s þ 1Þð2s þ 1Þ
C2ðsÞ ¼ 1:36 þ
Time
-0.4
1 2s þ 1
50
1 5s þ 1
The proposed methods have been compared with the methods of Jeng and Lin [16], Pai et al. [15] and Luyben [17] and the various simulation results are shown in Figs. 19–22 and Table 7. The proposed method gives the better set-point and loaddisturbance responses as well as the controller outputs than the other methods. The best GM–PM and Ms are obtained by C1. The minimum set-point-ISE is given by the method of Luyben [17], however, the response is slow. The proposed methods give an improvement over the other methods for perturbed process. The effect of the measurement noise is found to be negligible in the process output.
Time Fig. 18. Process output for Example 4 with the measurement noise.
The reference model is chosen as given by, M r;y ðsÞ ¼
0:5s þ 1 0:7s e 1:5s þ 1
It is to be noted that the reference model includes the nonminimum phase zero of the process. It has the settling time as 6.7 s. The obtained PID controller C1 is as given below. C1ðsÞ ¼ 1:118 þ
0:370 þ 1:926s s
4. Conclusion A simple frequency domain approximate model matching method has been proposed for the design of the PID controller for the integrating processes with time delay. Two approaches have been proposed and compared favorably with some prevalent design methods through examples taken from the literature. In the first approach, a double feedback loop configuration is considered. In the second approach, the design is directly carried out considering the load-disturbance model of the system. The frequency response matching in between the reference model and the control system to be designed is done at two low frequency points to arrive at a set of linear algebraic equations, solution of which gives the controller parameters. For the purpose of matching,
Please cite this article as: Anwar MN, Pan S. A frequency response model matching method for PID controller design for processes with dead-time. ISA Transactions (2014), http://dx.doi.org/10.1016/j.isatra.2014.08.020i
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Table 6 Performance comparison for Example 4. Controller parameters GM (dB) PM (deg) Ms
Method
KP Proposed C1 (double loop) Proposed C2 (single loop) Shamsuzzoha and Lee (single loop) Gu et al. [14] (single loop) Luyben [17] (single loop)
KI
KD
0.541 0.28
Load-disturbance response
OS (%) ts (s)
yp
ISE
1.33 0 1.54 0 1.32 0
10.1 1.409 1.4 6.45 1.289 1.31 8.25 1.603 1.42
10.8 8.5 7.95
0.5734 0.1813 0.3794
1/(1.5s þ 1) 1/(2s þ 1) (1.0963s þ 1)/(2.7528s2 þ 3.6543s þ 1)
1.436 8.77 1.8515 7.08
38.7 60.8
1.27 0 1.29 0
9.2 12.8
8.2 14.6
0.5535 1.236
(1.1599s þ 1)/(2.6597s2 þ3.8664sþ 1) (1.725s þ1)/(6.612 s2 þ 5.75 þ 1)
1.678 1.49 2.407 1.51
2.2
2
2
Proposed C1 Proposed C2 Jeng and Lin Pai et al Luyben
1.8
Amplitude
1.5
Amplitude
ts (s)
59.3 24.9 38.9
2.5
1
1.6 1.4
Proposed C1 Proposed C2 Jeng and Lin Pai et al Luyben
0.5 0 -0.5
ISE
Set-point filter F(s)
6.43 5.53 7.01
3.128 0.9823 3.996 3.5184 1.00 1.95 2.43 0.667 1.786 2.088 1.61
Set-point response
0
10
20
1.2 1 0.8 100
30
150
Time (sec)
Time (sec)
Fig. 19. Process output for Example 5; (a) Set-point response, (b) Load-disturbance response.
2
0.5
Proposed C1 Proposed C2 Jeng and Lin Pai et al Luyben
1.5
0
Amplitude
Amplitude
1
Proposed C1 Proposed C2 Jeng and Lin Pai et al Luyben
0.5
-0.5
-1
0 -1.5
-0.5 -1
0
10
-2 100
20
150
Time (sec)
Time (sec)
Fig. 20. Controller output for Example 5; (a) During set-point response, (b) During load-disturbance response.
2
2.5
1.5
1.5
Amplitude
Amplitude
2
1
Proposed C1 Proposed C2 Jeng and Lin Pai et al Luyben
0.5 0 -0.5
0
10
20
30
40
50
Time Fig. 21. Process output for perturbed system in Example 5.
1
Proposed C1 Noise Signal Proposed C2 Jeeng and Lin Pai et al Luyben
0.5
0
60
-0.5
0
10
20
30
40
Time Fig. 22. Process output for Example 5 with the measurement noise.
50
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Table 7 Performance comparison for Example 5. Method
Controller parameters
Proposed C1 (double loop) Proposed C2 (single loop) Jeng and Lin [16] (single loop) Pai et al. [15] (single loop) Luyben [17] (single loop)
KP
KI
KD
1.118 1.36 0.950 1.267 0.867
0.370 0.16 0.16 0.219 0.0361
1.926 1.20 1.10 1.171 0.963
GM (dB)
6.36 2.51 4.87 3.14 5.50
PM (deg)
65.5 26.5 41.8 28.4 55.2
there is no requirement of elaborate frequency response analysis or any mathematically involved optimization technique. Overall, the method is mathematically simple and computational burden is very small. The method is applicable to wide range of integrating processes that may be of low order or high order and that may have dead-time and non-minimum phase zeros. Various types of examples of the integrating processes such as integrating plus dead-time (IPDT) process, integrating second order plus dead-time (ISOPDT) process, ISOPDT process with non-minimum phase zero, high order integrating plus dead-time process with non-minimum phase zero are taken for design of controllers using the proposed method. It is observed from the examples that the proposed first approach gives better performance than the proposed second approach.
Ms
Set-point response
1.35 1.87 1.45 1.73 1.40
Load-disturbance response
OS (%)
ts (s)
ISE
yp
ts (s)
ISE
0 1.5 45.4 84.5 14
12.2 11.4 14.8 19 48.4
3.485 3.826 3.885 4.251 3.12
2.14 2.07 2.136 2.098 2.195
18.2 55.5 24.2 18 89.6
4.482 3.62 5.171 3.379 17.75
Set-point filter F(s)
1/(2s þ1) 1/(5s þ1) 1/(0.057þ 1) – –
Using the first order Pade approximation of e Ls in the denominator, Eq. (27) may be simplified as K D s2 þ K P s þ K I N p ðsÞe Ls s2 Dp ðsÞ s ¼ jω 2 ½ðωn L=2Þs þ ω2n e Ls i
ffi h ð28Þ nL 2 þ 2ξω s L=2 s2 þ 2ξω þ 1 s þ L ω n n 2 s ¼ jω
Appendix A
In Eq. (28), LHS has two poles at origin (type-2 transfer function) while the RHS has only one pole at origin (type-1 transfer function). Then, for feasible matching, types of both sides of Eq. (28) are to be same. This may be obtained by choosing KI ¼0 which makes LHS as type-1. It is observed, as expected, that even when the Pade approximation is not used in Eq. (27), the proposed method gives K I 0. In a similar way, it can be shown that for any order of the reference model, KI comes out to be 0.
For the two frequency points ω0 and ω1, Eqs. (13) and (14) give the following four equations
References
K P ¼ H R ðω0 Þ
KI
ω0
ð21Þ
þ K D ω0 ¼ H I ðω0 Þ
ð22Þ
K P ¼ H R ðω1 Þ
KI
ω1
ð23Þ
þ K D ω1 ¼ H I ðω1 Þ
ð24Þ
Eqs. (21)–(24) may be rearranged in compact form to have 2 3 2 3 1 0 0 2 H R ð ω0 Þ 3 6 7 6 0 1 ω 7 KP 07 H ðω Þ 7 6 ω0 7 6 6 I 0 7 6 76 K ¼ I 4 5 6 H R ð ω1 Þ 7 61 0 0 7 4 5 4 5 K D 0 ω11 ω1 H I ð ω1 Þ
ð25Þ
which follows Eq. (15).
Appendix B A desired reference model of second order is considered as given by M r;y ðsÞ ¼
ωn 2
s2 þ2ξωn s þ ωn 2
e Ls
ð26Þ
Then, Eq. (7) may be written as
ω2n e Ls KI N p ðsÞ Ls s2 þ 2ξωn s þ ω2n e ffi KP þ þ KDs ω2n sDp ðsÞ s Ls 1 s ¼ jω 2e s2 þ 2ξωn s þ ωn
s ¼ jω
ð27Þ
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Please cite this article as: Anwar MN, Pan S. A frequency response model matching method for PID controller design for processes with dead-time. ISA Transactions (2014), http://dx.doi.org/10.1016/j.isatra.2014.08.020i
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Please cite this article as: Anwar MN, Pan S. A frequency response model matching method for PID controller design for processes with dead-time. ISA Transactions (2014), http://dx.doi.org/10.1016/j.isatra.2014.08.020i