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A facile process to achieve hysteresis-free and fully stabilized graphene field-effect transistors† Yun Ji Kim, Young Gon Lee, Ukjin Jung, Sangchul Lee, Sang Kyung Lee and Byoung Hun Lee* The operation of chemical vapor-deposited (CVD) graphene field-effect transistors (GFETs) is highly sensitive to environmental factors such as the substrate, polymer residues, ambient condition, and other species adsorbed on the graphene surface due to their high defect density. As a result, CVD GFETs often exhibit a large hysteresis and time-dependent instability. These problems become a major roadblock in the systematic study of graphene devices. We report a facile process to alleviate these problems, which
Received 30th October 2014, Accepted 27th January 2015 DOI: 10.1039/c4nr06397j www.rsc.org/nanoscale
1.
can be used to fabricate stable high performance CVD GFETs with symmetrical current–voltage (I–V) characteristics and an effective carrier mobility over 6000 cm2 V−1 s−1. This process combined a few steps of processes in sequence including pre-annealing in a vacuum, depositing a passivation layer, and the final annealing in a vacuum, and eliminated ∼50% of charging sources primarily originating from water reduction reactions.
Introduction
Graphene has attracted great interest due to its extraordinary mechanical, optical, and electrical properties.1,2 Consequently, diverse applications of graphene such as in electrodes, memory devices, various sensors, and channel materials for logic devices have been explored.3–7 Also, graphene growth processes have been significantly improved. Chemical vapordeposited (CVD) graphene larger than 30 inches has been demonstrated, and several approaches to obtain high quality graphene with a larger grain size have been reported.8 Yet the quality of artificially grown graphene has not reached the level of exfoliated graphene. So it is still a great challenge to grow large area and high quality graphene. Moreover, several additional problems, such as high contact resistance, mobility degradation, and poor stability, originating from wrinkles, grain boundaries, and physical defects in CVD graphene are limiting further progress in its application.9–12 Physical defects in particular make CVD graphene vulnerable to the influences of environmental factors such as the ambient condition, molecular adsorbates, and other metallic and organic contaminants.13–16 Thus, tremendous efforts have been focused on achieving high performance and stabilized CVD graphene field-effect
Center for Emerging Electronic Devices and Systems, School of Materials Science and Engineering, Gwangju Institute of Science and Technology, Oryong-dong 1, Buk-gu, Gwangju 500-712, Korea. E-mail: [email protected] † Electronic supplementary information (ESI) available. See DOI: 10.1039/ c4nr06397j
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transistors (GFETs) by adjusting the annealing, cleaning, and chemical doping; changing the substrate; improving the transfer method; depositing a passivation layer; and reducing the defect density.8,15–24 Metal oxides, such as Al2O3, HfO2 and TiO2, were deposited on graphene as the passivation layer and these metal oxides were directly grown on graphene by the atomic layer deposition (ALD) process, or they were formed by oxidation in air after deposition of metals.14,25–28 Also the nonmetal oxide passivation using polymer buffer layers, organic semiconductors and organic compounds has been reported.29–31 Yet, these processes cannot be used directly because the benefits of individual processes are not sustainable, or those processes are not compatible with the high temperatures used. The effects of annealing disappeared when the graphene was exposed to ambient air and the passivation without eliminating pre-existing contaminants was not enough to eliminate the hysteresis. Also, even though each of the above attempts has exhibited a certain degree of success in controlling the hysteresis and improving the mobility, these parameters do not directly provide information on the physical mechanisms involved in the improvement. Thus, we carefully combined a few processes so that the final process can be easily executed, and the effects of such a process can be sustainable and we also analyzed the benefits of each process by quantitatively monitoring the physical mechanisms related to the hysteresis and mobility degradation. This work presents a facile process to fabricate a hysteresisfree GFET with long-term stability, which consists of a few steps of processes in sequence: pre-annealing in a vacuum at
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250 °C for 2 h after keeping the devices in a vacuum for 48 h, depositing a passivation layer (30 nm Al2O3), and the final annealing in a vacuum at 300 °C for 1 h. Using this process, the carrier mobility was improved over 6000 cm2 V−1 s−1, even with CVD graphene, and nearly symmetric drain current–gate voltage (Id–Vg) curves with less than 3.16 × 1010 cm−2 of residual charge carriers were achieved. Also, a mechanism to improve hysteresis was investigated in detail by monitoring the step-by-step changes in the device characteristics using stateof-the-art electrical characterization methods, including the pulsed current–voltage (I–V) and discharging current analysis (DCA) methods.13,32,33 Our process will provide a robust protocol for fabricating high performance and stable GFETs using a combination of relatively simple processes.
2. Experimental A single layer of graphene grown on a Cu foil using a thermal CVD process was transferred to a SiO2 (90 nm)/Si substrate using a PMMA-assisted transfer technique. The PMMA was coated at 500 rpm for 5 s and at 3000 rpm for 50 s followed by a baking step at 80 °C for 5 min. The Cu foil was then etched in the Cu etchant for 15 min at 50 °C, and the PMMA/ graphene was wet-cleaned with a cycle of deionized (DI) water rinse/hydrogen chloride (27.78%) clean/DI water rinse. The SiO2/Si substrate was cleaned with a SC1 clean (NH4OH–H2O2– H2O = 1 : 1 : 5) at 80 °C for 10 min and rinsed with DI water for 5 min. Then, the PMMA/graphene film was transferred to a cleaned SiO2/Si substrate, and the bonded substrate was kept at room temperature over 24 h to improve the bonding strength. Finally, the PMMA layer was removed with acetone at 85 °C for 4 h. When the transfer process was complete, the quality of the graphene was assessed using Raman spectroscopy. The integrated ratio of Raman peaks, ID/IG, representing the quality of graphene was ∼0.12 (see ESI Fig. S1†).34 The presence of the D peak indicates that the quality is reasonably good, but a considerable number of physical defects are still present. To fabricate back-gated GFETs, a Au (20 nm) hard mask layer was deposited on the graphene using e-beam evaporation and then it was patterned using the Au etchant as shown in Fig. 1(a). The Au hard mask was adopted to pattern both the channel and source/drain regions of the graphene while minimizing the impact of photoresist residues on the graphene channel. The graphene layer was etched using O2 plasma (see Fig. 1(b)). Then, a 100 nm Au layer was deposited again using e-beam evaporation and patterned to form source/drain electrodes. The final structure of the back-gated GFETs is shown in Fig. 1(c). The typical device fabrication process for GFETs ends at this point. Then, we added a sequence of steps to stabilize and improve their device characteristics. These steps eliminate the residual water molecules and organic residues as graphically shown in Fig. 1(d)–(f ). The first step was pre-annealing at 250 °C for 2 h after keeping the devices in a vacuum
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(∼10−6 Torr) for 48 h.35 Then, the graphene channel region was passivated with 30 nm Al2O3. The Al2O3 layer was deposited at 130 °C by low temperature ALD. For each ALD cycle, trimethylaluminum (TMA)/N2 purge/H2O/N2 purge steps are repeated for 0.2 s/20 s/0.2 s/20 s, respectively. It has been known that the water related molecules are eliminated from the interface through a chemical reaction with TMA during the ALD process. This process known as the self-cleaning effect of ALD shifts the Dirac voltage of GFETs to the negative side and increases the current at the electron branch, as the hole density is reduced by the lower density of positively charged hydroxyl and oxygen/water related molecules.14,36 In addition, the Al2O3 layer protects the graphene from further exposure to air. Finally, the passivated samples were annealed under high vacuum (∼10−6 Torr) at 300 °C for 1 h to complete the process achieving stable GFETs. So far, the quality of GFETs has been roughly assessed using the mobility and hysteresis extracted from slowly measured Id–Vg characteristics. However, this approach cannot provide an accurate quantitative evaluation of the impact of the stabilization processes. In this work, pulsed Id–Vg characteristics and discharging current characteristics were measured using state-of-the-art electric characterization systems. Details of the electronic set-up for these measurement methods can be found in ref. 13 and 37. Mobility, hysteresis, and time constants of tunneling-induced charge trapping and chemical charge generation reactions can be accurately extracted from pulsed I–V measurements, and the density of charging sites causing the hysteresis can be extracted using the discharging current analysis (DCA) method.13,32,37 The DCA method quantitatively measures the number of carriers released from the defect sites near the surface of graphene or graphene itself by charging the bulk of graphene and nearby defects at different frequencies from 100 kHz to 200 kHz.32,37 All electrical measurements, except for the long term air stability test, were carried out in a vacuum (∼10−6 Torr) to minimize the influence of the atmosphere. The GFETs used for the pulsed I–V measurements were of 3 μm × 5 μm (channel length × width) dimensions. The pulse width was 1 ms, and the rise and fall time was 100 μs. For the DCA measurement, GFETs with a channel length × width of 4 μm × 2 μm were used. The pulse rise and fall times were 10 ns, and the baseline of the pulse was VDirac −5 V. The amplitude of the pulse was −10 V. The discharging current was measured from 1 kHz to 600 kHz. Details of the measurement set-up and further discussion about the principle of the DCA method can be found in ref. 32 and 37.
3. Results and discussion The representative conductivity, σ versus Vg curves measured after each added stabilization process is shown in Fig. 2(a). As stabilization processes were added, the Dirac voltage moved toward 0 V (Fig. 2(b)) and the conductivity of the electron branch increased. The σ–Vg curve in particular became nearly symmetric (inset figure of Fig. 2(a)) after the final annealing,
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Fig. 1 Schematic of the GFET fabrication flow. (a) Patterning of the Au (20 nm) hard mask to avoid photoresist contamination, (b) graphene channel patterning using an O2 plasma reactive ion etching process, (c) depositing an additional Au (100 nm) layer and patterning it to form source and drain regions, (d) pre-annealing in a vacuum at 250 °C for 2 h after keeping the devices in a vacuum for 48 h, (e) depositing a passivation layer (30 nm Al2O3 was atomic layer-deposited at 130 °C), and (f ) final annealing in a vacuum at 300 °C for 1 h.
Fig. 2 (a) Progressive improvement in the conductivity, σ, versus Vg curves with the processes added to stabilize device characteristics. The normalized conductivity versus Vg–VDirac curves are shown in the inset to compare the degree of symmetry. (b) Distribution of the charge density converted from VDirac after the processes are added.
indicating that residual charge trapping was successfully minimized. Average residual charges calculated from the ΔVDirac were reduced from 3.75 × 1012 cm−2 to 7.5 × 1011 cm−2. Mobility values, μFE,C, extracted using the constant mobility model after compensating for the contact resistance38 also improved dramatically in both hole and electron branches as shown in Fig. 3. After the final annealing, the peak μFE,C values of the holes and electrons reached 6146 cm2 V−1 s−1 and 6239 cm2 V−1 s−1, respectively. The average mobility of 20 devices was over ∼4500 cm2 V−1 s−1. While these values are still much lower than that of exfoliated graphene, they are among the best mobility values reported for CVD graphene, which inherently has a much higher defect density than exfoliated graphene.9,23,39,40 Also noteworthy is that the mobility of the electrons and holes is similar after the final annealing. This means that stable and symmetrical I–V characteristics can be
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Fig. 3 Progressive improvement in the field-effect mobility, μFE,C, as the additional processes to minimize the contaminants are applied in sequence. The markers on top of the upper panel indicate the corresponding process step shown in Fig. 1. The mobility values are calculated after compensating for the contact resistance.
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obtained from GFETs with a residual charge density of the order of 1011 cm−2, at least under low drain bias conditions. To understand how this improvement in device characteristics can be achieved by adding a few simple processes, charge trapping characteristics and the interface quality were investigated in detail by tracking the changes in the hysteresis and the number of total charging sites. The hysteresis was monitored using both ΔI and ΔVDirac as defined in Fig. 4(a). ΔI represents a time-dependent current change for a fixed pulse duration (1 ms) at a given gate bias, while ΔVDirac represents the shift in the charge neutrality level due to residual charges generated per cycle of I–V curve measurements. While ΔI gives a more quantitative comparison than ΔVDirac, the information from ΔI is limited to a response for a short period under a given pulse bias condition, i.e., Vg − VDirac = 7 V in this work. On the other hand, as shown in Fig. 4(a), ΔVDirac is defined as a difference in the Dirac voltage after one cycle of pulsed I–V measurements at an electron conduction branch (right side of the Dirac voltage). To compare the characteristics of GFETs with additional stabilization processes under the same overdrive conditions, the height of the pulse was fixed to Vg − VDirac = 7 V. As the stabilization processes were added, both ΔI and ΔVDirac decreased rapidly. After the final annealing, ΔVDirac decreased to nearly zero and the variations of ΔVDirac were reduced as well, indicating that the GFETs became nearly hysteresis-free and stable as shown in Fig. 4(b). Since the constant mobility model becomes inaccurate when the I–V curve is asymmetric, the residual charge density was roughly extracted
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from the simple equation, Q = CV, because I–V curves of less optimized devices were asymmetric.38,41 The total effective residual charge density, Neff = Cox × ΔVDirac/q, decreased by ∼85.6%, (from 2.19 × 1011 cm−2 to 3.16 × 1010 cm−2). The residual charge density, of the order of 1010 cm−2, is extremely low, even comparable to the interface density of well behaving silicon MOSFETs. Once the device is fully stabilized, the hysteresis only increased by 0.45 V even at Vg − VDirac = 35 V compared to 7 V, indicating that the overdrive condition has a very weak influence on the amount of hysteresis. As mentioned above, ΔI provides detailed information on the charge generation, which consists of two charging mechanisms, during a given pulse. So ΔI can be analyzed using a two-trap model, having two different time constants, shown below.13,42 t t þ B exp I ¼ I 0 A exp τA τB
ð1Þ
where I0 is the initial drain current, A and B are the relative ratios of the two mechanisms, and τA and τB are the trap time constants. We can classify these two mechanisms into fast and slow charge generation mechanisms. The fast charge generation is related to the direct charge transfer from the graphene to nearby trap sites through a carrier tunneling process.13 On the other hand, the slow charge generation is related to a chemical reaction-like process, which is primarily an oxygen reduction/oxidation, O2 + 2H2O + 4e ⇔ 4OH−.14 So
Fig. 4 Progressive improvement in (a) pulsed Id versus Vg–VDirac curves, (b) ΔVDirac with the processes added to stabilize device characteristics, (c) representative discharging current versus frequency curves, and (d) density of the charging sites calculated from the slope of the discharge current versus frequency curves.
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τA and τB represent the time constants of tunneling and chemical reactions, respectively. Also A and B are the relative contributions of tunneling and chemical reaction mechanisms, respectively. The averages of τA and τB extracted from the stabilized device were around 40.8 μs and 335.5 μs, respectively. These values match well with previously reported time constants (τA = 36.6 μs, τB = 466 μs) for graphene–SiO2 interfaces, indicating that the intrinsic transient charging mechanisms do not change even though our process drastically reduces the absolute amount of charge trapping.13 Fig. 4(c) shows the gradual change in the discharging current from the graphene channel as a function of the measurement frequency from 10 kHz to 100 kHz. The discharge current analysis method fills up the graphene channel and trap sites with majority carriers and then drains them. After extracting the number of charges drained from the graphene channel itself, charges released from the trap sites can be extracted by analyzing the frequency dependence of the total discharge current. Thus, the slopes of the curves shown in Fig. 4(c), δI/δf, can be converted to the total number of charge sites, Ncharge site, including the charges at the graphene and the graphene–substrate interface using eqn (2), N charge site
# 2 δI=δf C t ¼ ΔN o cm2 k Aq t cm2 C
ð2Þ
where ΔNo is the difference in the bulk carrier concentration in the graphene channel at the pulse peak and pulse baseline, respectively, A is the area of the graphene channel, and 2/k is a proportionality constant representing the charge loss during the measurement. A typical k value for CVD graphene is 1.0–1.5 in the 10 to 100 kHz region for the devices. The value of ΔNo is approximately 1012 cm−2 and can be ignored in eqn (2). The decrease in the slope of the curves means that the total number of charge generation sites is reduced by our stabilization processes.32,37 Fig. 4(c) shows that the final annealing step has a dominant influence on the slope, i.e. trap reduction, in both low and high frequency regions. The tunneling-induced charge trapping sites with a response time of 10–100 μs, analogous to process A in the two-trap model, are primarily detected from 10 kHz to 100 kHz. As the frequency increases from 100 kHz to 200 kHz, charge generation through a slow chemical reaction such as a water redox reaction induces an additional discharge current, not by a direct charge exchange, but by shifting the Dirac voltage. Quantitative analysis more clearly shows the relative contribution of each stabilization process. After the final annealing, both kinds of charge sites were significantly reduced as shown in Fig. 4(d). The average density of the charge sites representing the tunneling-induced charge trapping and chemical reaction-like charge trapping decreased to 0.98 × 1015 cm−2 and 0.24 × 1015 cm−2, respectively. The reduction rates for these two mechanisms are around 50% and 80%, respectively. In this work, the amount of the discharging current and its slope were higher than previously reported values because the discharging current was measured with a bias in a wider range;
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however, the physical meaning of the data is basically the same.32,37 Ncharge site of the order of 1015 cm−2 is several orders of magnitude higher than the residual charge density calculated from ΔVDirac, which is around 1010 cm−2. This difference is due to the difference in the relaxation time for DC I–V curve measurements and the discharge current analysis. Ncharge site accounts for all sites contributing to charge generation in tens of μs with minimal relaxation, but ΔVDirac represents the residual charges after a relatively long relaxation. Various parameters such as ΔVDirac, μFE,C, density, and fitting (A, B, τA, τB) related to the tunneling and chemical reaction measured after each stabilization process are summarized in Table 1 to examine the step-by-step improvement ratio. After the stabilization processes, the relative contributions of fast charging ( parameter A) and slow charging ( parameter B) changed from 65.4% : 34.6% to 88.3% : 11.7%. Among three process steps added to stabilize the GFETs, the effect of the final annealing is most pronounced (see ESI Fig. S2†), indicating that the impact of the stabilization processes is primarily related to the elimination of the residual water molecules from the graphene–Al2O3 interface. The effects of the stabilization processes have been further confirmed by checking the longterm stability of the GFETs. Fig. 5(a) shows the Id–Vg curves of a fully stabilized GFET repetitively measured for 330 hours. For two weeks, device characteristics did not change significantly. On the other hand, when GFETs were not passivated properly, their Dirac point shifted to the positive side and the amount of the shift was almost linearly proportional to the exposure time as shown in Fig. 5(b), which appears to be related to the gradual adsorption of hydroxyl and oxygen/water related molecules on graphene. This result further confirms that graphene devices should be properly passivated and exposure to air should be avoided to promote stable operation. It should be noted that proper annealing to densify the Al2O3 (30 nm) layer is also a crucial step not only because the as-deposited Al2O3 (30 nm) layer is not a good passivation material, but also because there are residual oxygen/water related molecules at the Al2O3–graphene interface which must be driven out by proper post deposition annealing. Therefore, the final annealing should be optimized properly to enhance the passivation. While the stabilization processes add some complexity to device fabrication, the result is noteworthy in that the average μFE,C of graphene reached over 4500 cm2 V−1 s−1 even with defective CVD graphene on the SiO2 substrate. Note that this improvement is achieved with only ∼50% reduction in the charge trapping sites (from 1.95 × 1015 cm−2 to 0.98 × 1015 cm−2). This result corroborates a previous report on the effect of pre-annealing under vacuum yielding excellent electrical characteristics for GFETs.24 We speculate that greater enhancements can be expected by further reducing the total charge trapping through better control of the device fabrication environment in a state-of-the-art semiconductor factory as well as through further improvement in the crystalline quality of the CVD graphene, which is closely related to the fast charging component.31 Also, an alternative substrate which can reduce the adverse effects of the SiO2 substrate might be useful for
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Table 1 ΔVDirac, μFE,C, and Ncharge site are measured from 20 GFETs, before and after the stabilization processes. The fitting parameters A and B representing the relative contribution of tunneling and chemical reactions averaged from 20 GFETs are calculated while fixing τA and τB to 40.8 μs and 335.5 μs, respectively, to minimize the error propagation μFE,C (×103 cm2 V−1 s−1)
Ncharge site (# × 1015 cm−2)
Pulse-fitting parameters
Process
ΔVDirac (V)
Hole
Electron
Fast
Slow
A (fast)
B (slow)
No process Pre-annealing Passivation Final annealing Ratio of improvement
1.83 ± 0.47 1.10 ± 0.34 0.80 ± 0.22 0.26 ± 0.14 0.86
1.79 ± 0.25 1.98 ± 0.31 3.23 ± 0.54 4.61 ± 0.63 1.58
1.18 ± 0.25 1.77 ± 0.36 2.92 ± 0.49 4.46 ± 0.67 2.78
1.95 ± 0.27 (61.1%) 1.59 ± 0.22 (66.9%) 1.44 ± 0.22 (71.6%) 0.98 ± 0.25 (80.3%) 0.50
1.24 ± 0.26 (38.9%) 0.79 ± 0.12 (33.1%) 0.57 ± 0.15 (28.4%) 0.24 ± 0.07 (19.7%) 0.81
0.122 ± 0.043 (65.4%) 0.104 ± 0.042 (71.4%) 0.094 ± 0.036 (78.9%) 0.068 ± 0.031 (88.3%) 0.44
0.064 ± 0.020 (34.6%) 0.042 ± 0.018 (28.6%) 0.025 ± 0.008 (21.1%) 0.009 ± 0.005 (11.7%) 0.86
Fig. 5 (a) Transfer characteristics of GFETs after the stabilization processes over 300 h; the inset indicates characteristics of GFETs fabricated without added processes for the same duration, (b) Dirac voltage change of GFETs fabricated with and without stabilization processes for the same duration as in (a).
further performance improvement. In addition, even though the physical quality of CVD graphene is not yet optimum, the performance and stability of GFETs using CVD graphene should not be a limiting factor in future electronic applications as long as the GFETs are properly fabricated.
4.
Conclusions
The impact of processes to obtain stabilized GFETs has been systematically analyzed using the pulsed I–V method and the discharging current analysis method. Properly sequenced processes consisting of annealing/passivation/annealing successfully eliminated the water-related slow charging mechanism, allowing stable GFETs to be obtained. The highest mobility values, over 6000 cm2 V−1 s−1, and stable device operation with a residual charge hysteresis lower than 1011 cm−2 were achieved. Both the average hole and electron mobility increased by about 158% and 278% respectively compared with the mobility without any treatment. Also the average residual charge was reduced by ∼86%. Finally, the stability of GFETs was drastically enhanced with the stabilization processes which block and remove water/oxygen related molecules from air and the graphene channel respectively. This result demonstrates that stable GFETs can be realized, even when
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using artificially grown graphene with a moderate level of defects, if the fabrication process is properly designed.
Acknowledgements This research was supported by Global Frontier Program through the Global Frontier Hybrid Interface Materials (GFHIM) of the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2013M3A6B1078873) and the Pioneer Research Center Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (2012-0009462).
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Cite this: DOI: 10.1039/c4nr06397j
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A facile process to achieve hysteresis-free and fully stabilized graphene field-effect transistors† Yun Ji Kim, Young Gon Lee, Ukjin Jung, Sangchul Lee, Sang Kyung Lee and Byoung Hun Lee* The operation of chemical vapor-deposited (CVD) graphene field-effect transistors (GFETs) is highly sensitive to environmental factors such as the substrate, polymer residues, ambient condition, and other species adsorbed on the graphene surface due to their high defect density. As a result, CVD GFETs often exhibit a large hysteresis and time-dependent instability. These problems become a major roadblock in the systematic study of graphene devices. We report a facile process to alleviate these problems, which
Received 30th October 2014, Accepted 27th January 2015 DOI: 10.1039/c4nr06397j www.rsc.org/nanoscale
1.
can be used to fabricate stable high performance CVD GFETs with symmetrical current–voltage (I–V) characteristics and an effective carrier mobility over 6000 cm2 V−1 s−1. This process combined a few steps of processes in sequence including pre-annealing in a vacuum, depositing a passivation layer, and the final annealing in a vacuum, and eliminated ∼50% of charging sources primarily originating from water reduction reactions.
Introduction
Graphene has attracted great interest due to its extraordinary mechanical, optical, and electrical properties.1,2 Consequently, diverse applications of graphene such as in electrodes, memory devices, various sensors, and channel materials for logic devices have been explored.3–7 Also, graphene growth processes have been significantly improved. Chemical vapordeposited (CVD) graphene larger than 30 inches has been demonstrated, and several approaches to obtain high quality graphene with a larger grain size have been reported.8 Yet the quality of artificially grown graphene has not reached the level of exfoliated graphene. So it is still a great challenge to grow large area and high quality graphene. Moreover, several additional problems, such as high contact resistance, mobility degradation, and poor stability, originating from wrinkles, grain boundaries, and physical defects in CVD graphene are limiting further progress in its application.9–12 Physical defects in particular make CVD graphene vulnerable to the influences of environmental factors such as the ambient condition, molecular adsorbates, and other metallic and organic contaminants.13–16 Thus, tremendous efforts have been focused on achieving high performance and stabilized CVD graphene field-effect
Center for Emerging Electronic Devices and Systems, School of Materials Science and Engineering, Gwangju Institute of Science and Technology, Oryong-dong 1, Buk-gu, Gwangju 500-712, Korea. E-mail: [email protected] † Electronic supplementary information (ESI) available. See DOI: 10.1039/ c4nr06397j
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transistors (GFETs) by adjusting the annealing, cleaning, and chemical doping; changing the substrate; improving the transfer method; depositing a passivation layer; and reducing the defect density.8,15–24 Metal oxides, such as Al2O3, HfO2 and TiO2, were deposited on graphene as the passivation layer and these metal oxides were directly grown on graphene by the atomic layer deposition (ALD) process, or they were formed by oxidation in air after deposition of metals.14,25–28 Also the nonmetal oxide passivation using polymer buffer layers, organic semiconductors and organic compounds has been reported.29–31 Yet, these processes cannot be used directly because the benefits of individual processes are not sustainable, or those processes are not compatible with the high temperatures used. The effects of annealing disappeared when the graphene was exposed to ambient air and the passivation without eliminating pre-existing contaminants was not enough to eliminate the hysteresis. Also, even though each of the above attempts has exhibited a certain degree of success in controlling the hysteresis and improving the mobility, these parameters do not directly provide information on the physical mechanisms involved in the improvement. Thus, we carefully combined a few processes so that the final process can be easily executed, and the effects of such a process can be sustainable and we also analyzed the benefits of each process by quantitatively monitoring the physical mechanisms related to the hysteresis and mobility degradation. This work presents a facile process to fabricate a hysteresisfree GFET with long-term stability, which consists of a few steps of processes in sequence: pre-annealing in a vacuum at
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250 °C for 2 h after keeping the devices in a vacuum for 48 h, depositing a passivation layer (30 nm Al2O3), and the final annealing in a vacuum at 300 °C for 1 h. Using this process, the carrier mobility was improved over 6000 cm2 V−1 s−1, even with CVD graphene, and nearly symmetric drain current–gate voltage (Id–Vg) curves with less than 3.16 × 1010 cm−2 of residual charge carriers were achieved. Also, a mechanism to improve hysteresis was investigated in detail by monitoring the step-by-step changes in the device characteristics using stateof-the-art electrical characterization methods, including the pulsed current–voltage (I–V) and discharging current analysis (DCA) methods.13,32,33 Our process will provide a robust protocol for fabricating high performance and stable GFETs using a combination of relatively simple processes.
2. Experimental A single layer of graphene grown on a Cu foil using a thermal CVD process was transferred to a SiO2 (90 nm)/Si substrate using a PMMA-assisted transfer technique. The PMMA was coated at 500 rpm for 5 s and at 3000 rpm for 50 s followed by a baking step at 80 °C for 5 min. The Cu foil was then etched in the Cu etchant for 15 min at 50 °C, and the PMMA/ graphene was wet-cleaned with a cycle of deionized (DI) water rinse/hydrogen chloride (27.78%) clean/DI water rinse. The SiO2/Si substrate was cleaned with a SC1 clean (NH4OH–H2O2– H2O = 1 : 1 : 5) at 80 °C for 10 min and rinsed with DI water for 5 min. Then, the PMMA/graphene film was transferred to a cleaned SiO2/Si substrate, and the bonded substrate was kept at room temperature over 24 h to improve the bonding strength. Finally, the PMMA layer was removed with acetone at 85 °C for 4 h. When the transfer process was complete, the quality of the graphene was assessed using Raman spectroscopy. The integrated ratio of Raman peaks, ID/IG, representing the quality of graphene was ∼0.12 (see ESI Fig. S1†).34 The presence of the D peak indicates that the quality is reasonably good, but a considerable number of physical defects are still present. To fabricate back-gated GFETs, a Au (20 nm) hard mask layer was deposited on the graphene using e-beam evaporation and then it was patterned using the Au etchant as shown in Fig. 1(a). The Au hard mask was adopted to pattern both the channel and source/drain regions of the graphene while minimizing the impact of photoresist residues on the graphene channel. The graphene layer was etched using O2 plasma (see Fig. 1(b)). Then, a 100 nm Au layer was deposited again using e-beam evaporation and patterned to form source/drain electrodes. The final structure of the back-gated GFETs is shown in Fig. 1(c). The typical device fabrication process for GFETs ends at this point. Then, we added a sequence of steps to stabilize and improve their device characteristics. These steps eliminate the residual water molecules and organic residues as graphically shown in Fig. 1(d)–(f ). The first step was pre-annealing at 250 °C for 2 h after keeping the devices in a vacuum
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(∼10−6 Torr) for 48 h.35 Then, the graphene channel region was passivated with 30 nm Al2O3. The Al2O3 layer was deposited at 130 °C by low temperature ALD. For each ALD cycle, trimethylaluminum (TMA)/N2 purge/H2O/N2 purge steps are repeated for 0.2 s/20 s/0.2 s/20 s, respectively. It has been known that the water related molecules are eliminated from the interface through a chemical reaction with TMA during the ALD process. This process known as the self-cleaning effect of ALD shifts the Dirac voltage of GFETs to the negative side and increases the current at the electron branch, as the hole density is reduced by the lower density of positively charged hydroxyl and oxygen/water related molecules.14,36 In addition, the Al2O3 layer protects the graphene from further exposure to air. Finally, the passivated samples were annealed under high vacuum (∼10−6 Torr) at 300 °C for 1 h to complete the process achieving stable GFETs. So far, the quality of GFETs has been roughly assessed using the mobility and hysteresis extracted from slowly measured Id–Vg characteristics. However, this approach cannot provide an accurate quantitative evaluation of the impact of the stabilization processes. In this work, pulsed Id–Vg characteristics and discharging current characteristics were measured using state-of-the-art electric characterization systems. Details of the electronic set-up for these measurement methods can be found in ref. 13 and 37. Mobility, hysteresis, and time constants of tunneling-induced charge trapping and chemical charge generation reactions can be accurately extracted from pulsed I–V measurements, and the density of charging sites causing the hysteresis can be extracted using the discharging current analysis (DCA) method.13,32,37 The DCA method quantitatively measures the number of carriers released from the defect sites near the surface of graphene or graphene itself by charging the bulk of graphene and nearby defects at different frequencies from 100 kHz to 200 kHz.32,37 All electrical measurements, except for the long term air stability test, were carried out in a vacuum (∼10−6 Torr) to minimize the influence of the atmosphere. The GFETs used for the pulsed I–V measurements were of 3 μm × 5 μm (channel length × width) dimensions. The pulse width was 1 ms, and the rise and fall time was 100 μs. For the DCA measurement, GFETs with a channel length × width of 4 μm × 2 μm were used. The pulse rise and fall times were 10 ns, and the baseline of the pulse was VDirac −5 V. The amplitude of the pulse was −10 V. The discharging current was measured from 1 kHz to 600 kHz. Details of the measurement set-up and further discussion about the principle of the DCA method can be found in ref. 32 and 37.
3. Results and discussion The representative conductivity, σ versus Vg curves measured after each added stabilization process is shown in Fig. 2(a). As stabilization processes were added, the Dirac voltage moved toward 0 V (Fig. 2(b)) and the conductivity of the electron branch increased. The σ–Vg curve in particular became nearly symmetric (inset figure of Fig. 2(a)) after the final annealing,
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Fig. 1 Schematic of the GFET fabrication flow. (a) Patterning of the Au (20 nm) hard mask to avoid photoresist contamination, (b) graphene channel patterning using an O2 plasma reactive ion etching process, (c) depositing an additional Au (100 nm) layer and patterning it to form source and drain regions, (d) pre-annealing in a vacuum at 250 °C for 2 h after keeping the devices in a vacuum for 48 h, (e) depositing a passivation layer (30 nm Al2O3 was atomic layer-deposited at 130 °C), and (f ) final annealing in a vacuum at 300 °C for 1 h.
Fig. 2 (a) Progressive improvement in the conductivity, σ, versus Vg curves with the processes added to stabilize device characteristics. The normalized conductivity versus Vg–VDirac curves are shown in the inset to compare the degree of symmetry. (b) Distribution of the charge density converted from VDirac after the processes are added.
indicating that residual charge trapping was successfully minimized. Average residual charges calculated from the ΔVDirac were reduced from 3.75 × 1012 cm−2 to 7.5 × 1011 cm−2. Mobility values, μFE,C, extracted using the constant mobility model after compensating for the contact resistance38 also improved dramatically in both hole and electron branches as shown in Fig. 3. After the final annealing, the peak μFE,C values of the holes and electrons reached 6146 cm2 V−1 s−1 and 6239 cm2 V−1 s−1, respectively. The average mobility of 20 devices was over ∼4500 cm2 V−1 s−1. While these values are still much lower than that of exfoliated graphene, they are among the best mobility values reported for CVD graphene, which inherently has a much higher defect density than exfoliated graphene.9,23,39,40 Also noteworthy is that the mobility of the electrons and holes is similar after the final annealing. This means that stable and symmetrical I–V characteristics can be
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Fig. 3 Progressive improvement in the field-effect mobility, μFE,C, as the additional processes to minimize the contaminants are applied in sequence. The markers on top of the upper panel indicate the corresponding process step shown in Fig. 1. The mobility values are calculated after compensating for the contact resistance.
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obtained from GFETs with a residual charge density of the order of 1011 cm−2, at least under low drain bias conditions. To understand how this improvement in device characteristics can be achieved by adding a few simple processes, charge trapping characteristics and the interface quality were investigated in detail by tracking the changes in the hysteresis and the number of total charging sites. The hysteresis was monitored using both ΔI and ΔVDirac as defined in Fig. 4(a). ΔI represents a time-dependent current change for a fixed pulse duration (1 ms) at a given gate bias, while ΔVDirac represents the shift in the charge neutrality level due to residual charges generated per cycle of I–V curve measurements. While ΔI gives a more quantitative comparison than ΔVDirac, the information from ΔI is limited to a response for a short period under a given pulse bias condition, i.e., Vg − VDirac = 7 V in this work. On the other hand, as shown in Fig. 4(a), ΔVDirac is defined as a difference in the Dirac voltage after one cycle of pulsed I–V measurements at an electron conduction branch (right side of the Dirac voltage). To compare the characteristics of GFETs with additional stabilization processes under the same overdrive conditions, the height of the pulse was fixed to Vg − VDirac = 7 V. As the stabilization processes were added, both ΔI and ΔVDirac decreased rapidly. After the final annealing, ΔVDirac decreased to nearly zero and the variations of ΔVDirac were reduced as well, indicating that the GFETs became nearly hysteresis-free and stable as shown in Fig. 4(b). Since the constant mobility model becomes inaccurate when the I–V curve is asymmetric, the residual charge density was roughly extracted
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from the simple equation, Q = CV, because I–V curves of less optimized devices were asymmetric.38,41 The total effective residual charge density, Neff = Cox × ΔVDirac/q, decreased by ∼85.6%, (from 2.19 × 1011 cm−2 to 3.16 × 1010 cm−2). The residual charge density, of the order of 1010 cm−2, is extremely low, even comparable to the interface density of well behaving silicon MOSFETs. Once the device is fully stabilized, the hysteresis only increased by 0.45 V even at Vg − VDirac = 35 V compared to 7 V, indicating that the overdrive condition has a very weak influence on the amount of hysteresis. As mentioned above, ΔI provides detailed information on the charge generation, which consists of two charging mechanisms, during a given pulse. So ΔI can be analyzed using a two-trap model, having two different time constants, shown below.13,42 t t þ B exp I ¼ I 0 A exp τA τB
ð1Þ
where I0 is the initial drain current, A and B are the relative ratios of the two mechanisms, and τA and τB are the trap time constants. We can classify these two mechanisms into fast and slow charge generation mechanisms. The fast charge generation is related to the direct charge transfer from the graphene to nearby trap sites through a carrier tunneling process.13 On the other hand, the slow charge generation is related to a chemical reaction-like process, which is primarily an oxygen reduction/oxidation, O2 + 2H2O + 4e ⇔ 4OH−.14 So
Fig. 4 Progressive improvement in (a) pulsed Id versus Vg–VDirac curves, (b) ΔVDirac with the processes added to stabilize device characteristics, (c) representative discharging current versus frequency curves, and (d) density of the charging sites calculated from the slope of the discharge current versus frequency curves.
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τA and τB represent the time constants of tunneling and chemical reactions, respectively. Also A and B are the relative contributions of tunneling and chemical reaction mechanisms, respectively. The averages of τA and τB extracted from the stabilized device were around 40.8 μs and 335.5 μs, respectively. These values match well with previously reported time constants (τA = 36.6 μs, τB = 466 μs) for graphene–SiO2 interfaces, indicating that the intrinsic transient charging mechanisms do not change even though our process drastically reduces the absolute amount of charge trapping.13 Fig. 4(c) shows the gradual change in the discharging current from the graphene channel as a function of the measurement frequency from 10 kHz to 100 kHz. The discharge current analysis method fills up the graphene channel and trap sites with majority carriers and then drains them. After extracting the number of charges drained from the graphene channel itself, charges released from the trap sites can be extracted by analyzing the frequency dependence of the total discharge current. Thus, the slopes of the curves shown in Fig. 4(c), δI/δf, can be converted to the total number of charge sites, Ncharge site, including the charges at the graphene and the graphene–substrate interface using eqn (2), N charge site
# 2 δI=δf C t ¼ ΔN o cm2 k Aq t cm2 C
ð2Þ
where ΔNo is the difference in the bulk carrier concentration in the graphene channel at the pulse peak and pulse baseline, respectively, A is the area of the graphene channel, and 2/k is a proportionality constant representing the charge loss during the measurement. A typical k value for CVD graphene is 1.0–1.5 in the 10 to 100 kHz region for the devices. The value of ΔNo is approximately 1012 cm−2 and can be ignored in eqn (2). The decrease in the slope of the curves means that the total number of charge generation sites is reduced by our stabilization processes.32,37 Fig. 4(c) shows that the final annealing step has a dominant influence on the slope, i.e. trap reduction, in both low and high frequency regions. The tunneling-induced charge trapping sites with a response time of 10–100 μs, analogous to process A in the two-trap model, are primarily detected from 10 kHz to 100 kHz. As the frequency increases from 100 kHz to 200 kHz, charge generation through a slow chemical reaction such as a water redox reaction induces an additional discharge current, not by a direct charge exchange, but by shifting the Dirac voltage. Quantitative analysis more clearly shows the relative contribution of each stabilization process. After the final annealing, both kinds of charge sites were significantly reduced as shown in Fig. 4(d). The average density of the charge sites representing the tunneling-induced charge trapping and chemical reaction-like charge trapping decreased to 0.98 × 1015 cm−2 and 0.24 × 1015 cm−2, respectively. The reduction rates for these two mechanisms are around 50% and 80%, respectively. In this work, the amount of the discharging current and its slope were higher than previously reported values because the discharging current was measured with a bias in a wider range;
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however, the physical meaning of the data is basically the same.32,37 Ncharge site of the order of 1015 cm−2 is several orders of magnitude higher than the residual charge density calculated from ΔVDirac, which is around 1010 cm−2. This difference is due to the difference in the relaxation time for DC I–V curve measurements and the discharge current analysis. Ncharge site accounts for all sites contributing to charge generation in tens of μs with minimal relaxation, but ΔVDirac represents the residual charges after a relatively long relaxation. Various parameters such as ΔVDirac, μFE,C, density, and fitting (A, B, τA, τB) related to the tunneling and chemical reaction measured after each stabilization process are summarized in Table 1 to examine the step-by-step improvement ratio. After the stabilization processes, the relative contributions of fast charging ( parameter A) and slow charging ( parameter B) changed from 65.4% : 34.6% to 88.3% : 11.7%. Among three process steps added to stabilize the GFETs, the effect of the final annealing is most pronounced (see ESI Fig. S2†), indicating that the impact of the stabilization processes is primarily related to the elimination of the residual water molecules from the graphene–Al2O3 interface. The effects of the stabilization processes have been further confirmed by checking the longterm stability of the GFETs. Fig. 5(a) shows the Id–Vg curves of a fully stabilized GFET repetitively measured for 330 hours. For two weeks, device characteristics did not change significantly. On the other hand, when GFETs were not passivated properly, their Dirac point shifted to the positive side and the amount of the shift was almost linearly proportional to the exposure time as shown in Fig. 5(b), which appears to be related to the gradual adsorption of hydroxyl and oxygen/water related molecules on graphene. This result further confirms that graphene devices should be properly passivated and exposure to air should be avoided to promote stable operation. It should be noted that proper annealing to densify the Al2O3 (30 nm) layer is also a crucial step not only because the as-deposited Al2O3 (30 nm) layer is not a good passivation material, but also because there are residual oxygen/water related molecules at the Al2O3–graphene interface which must be driven out by proper post deposition annealing. Therefore, the final annealing should be optimized properly to enhance the passivation. While the stabilization processes add some complexity to device fabrication, the result is noteworthy in that the average μFE,C of graphene reached over 4500 cm2 V−1 s−1 even with defective CVD graphene on the SiO2 substrate. Note that this improvement is achieved with only ∼50% reduction in the charge trapping sites (from 1.95 × 1015 cm−2 to 0.98 × 1015 cm−2). This result corroborates a previous report on the effect of pre-annealing under vacuum yielding excellent electrical characteristics for GFETs.24 We speculate that greater enhancements can be expected by further reducing the total charge trapping through better control of the device fabrication environment in a state-of-the-art semiconductor factory as well as through further improvement in the crystalline quality of the CVD graphene, which is closely related to the fast charging component.31 Also, an alternative substrate which can reduce the adverse effects of the SiO2 substrate might be useful for
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Table 1 ΔVDirac, μFE,C, and Ncharge site are measured from 20 GFETs, before and after the stabilization processes. The fitting parameters A and B representing the relative contribution of tunneling and chemical reactions averaged from 20 GFETs are calculated while fixing τA and τB to 40.8 μs and 335.5 μs, respectively, to minimize the error propagation μFE,C (×103 cm2 V−1 s−1)
Ncharge site (# × 1015 cm−2)
Pulse-fitting parameters
Process
ΔVDirac (V)
Hole
Electron
Fast
Slow
A (fast)
B (slow)
No process Pre-annealing Passivation Final annealing Ratio of improvement
1.83 ± 0.47 1.10 ± 0.34 0.80 ± 0.22 0.26 ± 0.14 0.86
1.79 ± 0.25 1.98 ± 0.31 3.23 ± 0.54 4.61 ± 0.63 1.58
1.18 ± 0.25 1.77 ± 0.36 2.92 ± 0.49 4.46 ± 0.67 2.78
1.95 ± 0.27 (61.1%) 1.59 ± 0.22 (66.9%) 1.44 ± 0.22 (71.6%) 0.98 ± 0.25 (80.3%) 0.50
1.24 ± 0.26 (38.9%) 0.79 ± 0.12 (33.1%) 0.57 ± 0.15 (28.4%) 0.24 ± 0.07 (19.7%) 0.81
0.122 ± 0.043 (65.4%) 0.104 ± 0.042 (71.4%) 0.094 ± 0.036 (78.9%) 0.068 ± 0.031 (88.3%) 0.44
0.064 ± 0.020 (34.6%) 0.042 ± 0.018 (28.6%) 0.025 ± 0.008 (21.1%) 0.009 ± 0.005 (11.7%) 0.86
Fig. 5 (a) Transfer characteristics of GFETs after the stabilization processes over 300 h; the inset indicates characteristics of GFETs fabricated without added processes for the same duration, (b) Dirac voltage change of GFETs fabricated with and without stabilization processes for the same duration as in (a).
further performance improvement. In addition, even though the physical quality of CVD graphene is not yet optimum, the performance and stability of GFETs using CVD graphene should not be a limiting factor in future electronic applications as long as the GFETs are properly fabricated.
4.
Conclusions
The impact of processes to obtain stabilized GFETs has been systematically analyzed using the pulsed I–V method and the discharging current analysis method. Properly sequenced processes consisting of annealing/passivation/annealing successfully eliminated the water-related slow charging mechanism, allowing stable GFETs to be obtained. The highest mobility values, over 6000 cm2 V−1 s−1, and stable device operation with a residual charge hysteresis lower than 1011 cm−2 were achieved. Both the average hole and electron mobility increased by about 158% and 278% respectively compared with the mobility without any treatment. Also the average residual charge was reduced by ∼86%. Finally, the stability of GFETs was drastically enhanced with the stabilization processes which block and remove water/oxygen related molecules from air and the graphene channel respectively. This result demonstrates that stable GFETs can be realized, even when
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using artificially grown graphene with a moderate level of defects, if the fabrication process is properly designed.
Acknowledgements This research was supported by Global Frontier Program through the Global Frontier Hybrid Interface Materials (GFHIM) of the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2013M3A6B1078873) and the Pioneer Research Center Program through the National Research Foundation of Korea funded by the Ministry of Science, ICT & Future Planning (2012-0009462).
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