A compact, multichannel, and low noise arbitrary waveform generator S. Govorkov, B. I. Ivanov, E. Il'ichev, and H.-G. Meyer Citation: Review of Scientific Instruments 85, 054702 (2014); doi: 10.1063/1.4873198 View online: http://dx.doi.org/10.1063/1.4873198 View Table of Contents: http://scitation.aip.org/content/aip/journal/rsi/85/5?ver=pdfcov Published by the AIP Publishing Articles you may be interested in A scalable, fast, and multichannel arbitrary waveform generator Rev. Sci. Instrum. 84, 124701 (2013); 10.1063/1.4832042 Arbitrary waveform generator for quantum information processing with trapped ions Rev. Sci. Instrum. 84, 033108 (2013); 10.1063/1.4795552 High voltage multichannel wave form generator for liquid crystal research Rev. Sci. Instrum. 71, 563 (2000); 10.1063/1.1150242 An improved method of generating analog waveforms from digital data Rev. Sci. Instrum. 69, 2569 (1998); 10.1063/1.1148960 A PC-controlled voltage pulse generator for electroanalytical applications Rev. Sci. Instrum. 68, 1879 (1997); 10.1063/1.1147961
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REVIEW OF SCIENTIFIC INSTRUMENTS 85, 054702 (2014)
A compact, multichannel, and low noise arbitrary waveform generator S. Govorkov,1 B. I. Ivanov,2,3 E. Il’ichev,2 and H.-G. Meyer2 1
Sema Systems, 302-5553 16th ave., Delta, British Columbia V4M 2H7, Canada Leibniz-Institute of Photonic Technology, PO Box 100239, D-07702 Jena, Germany 3 Novosibirsk State Technical University, K.Marx-Ave. 20, Novosibirsk 630092, Russia 2
(Received 10 October 2013; accepted 14 April 2014; published online 2 May 2014) A new type of high functionality, fast, compact, and easy programmable arbitrary waveform generator for low noise physical measurements is presented. The generator provides 7 fast differential waveform channels with a maximum bandwidth up to 200 MHz frequency. There are 6 fast pulse generators on the generator board with 78 ps time resolution in both duration and delay, 3 of them with amplitude control. The arbitrary waveform generator is additionally equipped with two auxiliary slow 16 bit analog-to-digital converters and four 16 bit digital-to-analog converters for low frequency applications. Electromagnetic shields are introduced to the power supply, digital, and analog compartments and with a proper filter design perform more than 110 dB digital noise isolation to the output signals. All the output channels of the board have 50 SubMiniature version A termination. The generator board is suitable for use as a part of a high sensitive physical equipment, e.g., fast read out and manipulation of nuclear magnetic resonance or superconducting quantum systems and any other application, which requires electromagnetic interference free fast pulse and arbitrary waveform generation. © 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4873198] I. HIGH SPEED PULSE AND WAVEFORM READOUT FOR PHYSICAL EXPERIMENTS
At present, the semiconductor technology allows the fabrication of high capacity Field Programmable Gate Array (FPGA) chips. This gives a great opportunity for experimentalists to create high functionality devices based on those FPGA and perform measurements according to the specific experimental requirements. One example of such type of low noise measurements is the nuclear magnetic resonance spectrometry and tomography,1 where it is required to provide a fast dynamical excitation by means of short time pulses. Another large area of perspective research is related to quantum superconducting circuits with Josephson junctions,2–6 since these systems have been found to be promising contenders for the quantum computer implementation.7 Since the number of quantum bits (qubits) on one chip was recently increased,8–10 it is necessary to control and manipulate them simultaneously with a high signal stability and low noise. Therefore, multichannel low jitter waveform generators with low output noise power are required. One possible solution in order to design waveform signal generators is to use FPGA. There are plenty of well-known commercial available devices providing scientists with waveform signals. But most of them are quite expensive, large, or do not offer enough signal flexibility. In this paper we present a compact, easy to reprogram, and digital noise free arbitrary waveform generator (AWG). It has 50 SubMiniature version A (SMA) output termination and can easily be installed in a 19 in. subrack.
II. AWG HARDWARE PERFORMANCE
The block diagram of the arbitrary waveform generator is shown in Fig. 1. This diagram shows the basic board structure, 0034-6748/2014/85(5)/054702/5/$30.00
which consists of three separate shielded compartments: power supply, digital compartment with an FPGA, and analog compartment with differential low-pass filters and low noise differential amplifiers (see DLPF and LNDA in Fig. 1). The FPGA performs the main board’s housekeeping function. Seven DAC blocks are responsible for providing the data to the 14-bit DACs, while six pulse blocks are generating pulse sequences with 78 ps resolution. The 48-bit timer generates sync pulse sequences, which trigger DAC and pulse circuits. All the programming of the FPGA is performed via link module. The AWG is assembled on a 8 layer printed circuit board (PCB) divided into three compartments (Fig. 2). The metallic shields of the compartments are soldered directly to the top and bottom ground planes of the PCB. For easy board debugging and signal characterization, the shields are equipped with removable leads. A digital compartment with a FPGA and fast DACs (digital-to-analog converters) is situated in the middle of the board, see Fig. 2(b). The Virtex-6 (xc6vlx75t2ff784) FPGA family is used for board housekeeping. There are three more Virtex-6 FPGA chips in the same pin compatible package. This allows one to increase FPGA resources up to 4 times by substituting the chip if required. The crystal oscillator is situated in the digital compartment and it generates the 500 MHz main clock of the board. It allows one to achieve a 2 ns coarse time resolution. The flash programmable readonly memory chip is used for downloading configuration files to the FPGA. A slow 16-bit digital/analog circuitry is presented on the board and is aimed to be used for low frequency measurements. Fast analog waveform outputs are generated with the 14bit MAX5890 DACs. This DAC chip has a low noise spectral density of −162 dBFS/Hz at fout 36 MHz, low voltage differential signaling digital inputs and less than 300 mW of power dissipation at the maximum frequency. It is capable of
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FIG. 1. A block diagram of the arbitrary waveform generator.
working up to 600 MHz clocking frequency. Four different modes of operation were developed in the FPGA firmware: Random Access Memory (RAM), Piece Wise Linear (PWL), Central Processor Unit (CPU), and zero waveform output mode. An extension to the 16-bit fast DACs from the same family does not improve the performance because they can offer only a 14-bit linearity performance. The circuits in the analog compartment (Fig. 2(c)) filter the incoming waveforms and amplify them with up to a maximum of 4 V peak-to-peak output voltage, depending on the channel number. The self voltage noise √ spectral density of the amplifiers corresponds to 1.1 nV / H z. All the analog outputs are filtered with 7th order Gaussian low-pass filters with either 100 MHz or 200 MHz cutoff frequencies. They are placed at the input of the analog compartment. The proper filter and PCB design provides more than 110 dB digital
noise suppression in the output signal lines. All the waveform filtering lines were primarily characterized with a network analyzer and have shown more than 110 dB stop band suppression up to 2 GHz frequency. Powder filters11, 12 or bandpass filters with high stop band suppression13 might be used if required. An off-the-shelf 5 V power supply is used to power the board. It is connected to the AWG board via an SMA power connector. All the power supply components are located in the power supply compartment of the board (Fig. 2(a)). Switching voltage regulators are used to generate all necessary voltage rails. The total power consumption of the board is mainly defined by the Virtex-6 FPGA and requires around 1.5 A of current (depending on the channel amount operating at the same time). In order to suppress the influence of DC-DC converters switching noise to the DACs’ analog outputs, double pi ferrite filters are used. III. AWG OPERATING MODES AND SOFTWARE A. RAM-, PWL-, CPU- modes
FIG. 2. A representation of the AWG board. (a) Power supply compartment, (b) digital part with DACs, and (c) analog compartment.
Each channel is equipped with a 32 K × 14 bit RAM block. By default, the RAM content is programmed with a single sine wave period. With 2 ns data point rate and continuous waveform generation, the default RAM content generates around 15 kHz sine wave. For higher frequencies, the RAM’s address counter may be incremented not by one but rather by a constant parameter Delta. For slower frequencies, a slower (once in N-clock times) reading from the RAM may be used. The RAM’s address counter may be rolled over (reset) when it reaches a preset limit. Using the ability to roll over the address counter and at the same time reprogram the RAM content, allows one to adjust the generated frequency by approximately 3 × 10−5 steps. This technique gives the possibility to generate a sine wave with frequencies from micro Hz up to 100 MHz. Therefore, the readout of superconducting devices in the classical14 as well as in the quantum15 regime can be performed using megahertz-range tank circuits. With the current realized PC USB 1.1 interface about 140 ms are required to reprogram the whole RAM content for one channel. A one shot mode is supported as well, when the RAM content
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may be read once after a delayed sync pulse is detected by the RAM address controller. A shorter than 32 K waveform may be read if required. A PWL engine is provided for each waveform channel. This engine allows one to “draw” straight lines via a set of predefined points. Two 32-bit numbers represent each PWL data point: an Increment and a Counter, which specifies how many clock cycles the Increment must be used. On each clock cycle, the PWL engine generates a new 32-bit value and a top 14-bit portion of it is sent to the 14-bit DAC. When the Increment equals zero, a constant value is generated for Counter clock cycles. Otherwise a rising (for a positive Increment) or falling (for a negative Increment) ramp is generated. Each point may last from 2 ns (one clock cycle) to more then 8 s. For example a single 8 s long ramp may be generated from one data point with the Increment = 1 and the Counter = 232 − 1 (maximum possible Counter’s number). When the Counter = 0, the Increment value is treated as an immediate value, which is sent to the DAC. This mechanism allows one to start the PWL waveform with a well-defined value or set a new value in the middle of the waveform if required. Setting this new value still requires a one-clock cycle (2 ns). In total 1024 points may be used for each channel. The PWL engine stops when it reaches the End-of-Packet (EOP) marker, which is stored together with the last PWL data point. The EOP marker is automatically inserted at the end of a new PWL packet sent by the host PC. One extra mode of operation (namely, CPU) is provided as well. Each channel has a tiny micro controller, which has a 250 MHz clock frequency and requires two clock cycles per instruction. This mode is intended to be used for a simple waveform generation like a saw tooth or any other waveform, that can be easily described by a simple software algorithm. An assembler language compiler together with a newly generated code loader are provided.
Rev. Sci. Instrum. 85, 054702 (2014)
(a)
(b)
FIG. 3. The experimental characteristic of the waveform signals in RAMand PWL-waveform modes for the third channel of the AWG board with 100 MHz bandwidth. We show the examples of sinus and Gaussian (red curve) waveforms with 1.4 V output peak-peak voltage amplitude (a) and an example of a 10 point PWL waveform (b).
10 PWL points is presented on the oscillogram (see Fig. 3(b)). In PWL mode 1 point needs roughly 10 μs for reprogramming, so in the case of 10 points, the reprogramming time for all the 7 waveform channels can be less then 1 ms. All three waveforms were generated by the same channel with cutoff (a)
B. Software
A special software was designed in order to handle and debug the board. A logic analyzer program with graphical interface was written using Dev-C++ from Bloodshed.16 This interface allows one to set the main parameters for the waveform signals, e.g., pulse amplitudes and delays (both the fine and the coarse), channel modes, etc. The AWG board can be handled by any programming language, which supports Dynamic Link Library (DLL) calls.
(b)
IV. SIGNAL CHARACTERISTICS A. RAM-mode, PWL-mode, and CPU-mode arbitrary waveform signals
The measured oscillograms of the operating RAM-mode waveforms are shown in Fig. 3. We generated a 20 MHz sinusoidal signal with a 1.4 V peak-to-peak amplitude and a zero offset. Another example of the RAM-mode waveform is the Gaussian signal (red curve in Fig. 3(a)). We also demonstrate a simple possibility to program a waveform by means of a piecewise linear function. A PWL-mode signal with only
FIG. 4. The measured pulse sequences of 2 pulse channels (SYNC0, PLS1) of the AWG board. (a) Two pulses with 2 ns and 4 ns lengths for the coarse mode. The 1 ns delay time between two pulses is demonstrated. (b) The 78 ps fine mode delay as the lowest time delay resolution between pulses is presented.
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(a)
(c)
Rev. Sci. Instrum. 85, 054702 (2014)
(b)
(d)
FIG. 5. The noise output spectra with zero waveform output at channel 0 of the AWG board. (a) The low frequency noise spectra demonstrates lack of parasitic power supply switching noise. (b) The 500 MHz clock noise suppression corresponds to 110 dB. (c) The wideband power noise spectra over the 100 MHz low-pass filter measured up to 1.8 GHz. (d) The pulse jitter with a long measurement term corresponds to 35 ps. The x-abscissa corresponds to time with 50 ps step and the y-ordinate corresponds to voltage with 50 mV step.
frequency fc = 100 MHz. An oscilloscope with 20 GSa/s sampling rate with 2000 display points was used for the signal characterization. B. Pulse generator
The pulse generator was fully characterized and the most outstanding parameters of the pulse channels are demonstrated by the oscillogram in Fig. 4. There are two pulse sequences with different amplitudes from channels PLS1 and SYNC0 of the AWG board. One pulse has 2 ns length and the other has 4 ns length. These two pulse sequences have 1 ns of delay between them and this coarse mode is presented in Fig. 4(a). We also show that the lowest time delay of the pulses can correspond to 78 ps for the fine mode and this is shown on the oscillogram Fig. 4(b). C. Noise performance, signal resolution, and jitter characterization
The main noise contributors to the output waveform signals of the board are the 500 MHz clock signal from the
local oscillator and the oscillating noises from switching power supply circuitry. In order to characterize the noise performance of the generator we measured the output spectra for all the channels by means of a spectrum analyzer. The zero waveform mode was characterized up to a frequency of 1.8 GHz. The experimental characteristic in Fig. 5(c) shows the suppression of the noise power up to 100 dB for the measured frequency range. A proper Gaussian low-pass filter design performs more then 110 dB suppression of the 500 MHz clock noise, see Fig. 5(b). The low frequency noise power for channel 0 is shown in Fig. 5(a). This curve demonstrates that the switching frequency noise signal from power the DC-DC converters were suppressed more than 115 dB. Experiments with superconducting persistent current qubits require high signal stability. Their characterization of coherence times is usually performed by means of short pulse excitation. Here the jitter plays an important role and defines the stability of the measurement. We characterized the long term jitter of the pulse generator. We applied two different pulses with 5 ns and 10 ns lengths to two input channels of the fast 50 terminated oscilloscope. The delay between the pulses was set to 8 ms. The first pulse was used for triggering
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is that it has built-in capability for an extension and multiple boards can be daisy chained, having the same clock, control, and trigger lines. The board may be assembled with bigger FPGA chips if required. There are three more Virtex-6 FPGA chips in the same pin compatible package. This allows one to increase FPGA resources up to 4 times if required. The completed AWG device with closed leads is presented in Fig. 6.
ACKNOWLEDGMENTS
FIG. 6. The photo of the implemented arbitrary waveform generator board with removable metallic leads and SMA output termination.
the oscilloscope and the jitter was observed on the rising edge of the second pulse. The jitter color diagram is presented in Fig. 5(d). The peak-to-peak value of the jitter corresponds to approximately 35 ps and is less than a half of the finest 78 ps step. V. CONCLUSION
In a frame of this work we designed and implemented a new high speed multifunction AWG board for physical experiments. The board has 7 differential fast output waveform channels and 4 slow output waveform channels. The fast channels have 14-bit and 2 ns resolution. According to the bandwidth and noise requirements, 7 waveform channels have different frequency bandwidths, namely, 5 channels have 100 MHz cutoff frequency with more than 100 dB noise isolation and 2 channels have 200 MHz cutoff frequency with more than 90 dB noise isolation. The waveform channels have amplitude control with a maximum amplitude up to 4 V. The pulse generator is realized as 3 amplitude control channels and 3 channels with a constant amplitude. The maximum pulse length and delay is 4 s and the minimum pulse length and delay is 1 ns. The AWG board is built around Xilinx Virtex-6 FPGA with 500 MHz main clock. The operation is controlled by free programming languages: Dev-C++ from Bloodshed or Python and requires simple single off-the-shelf +5 V with less then 2 A current power supply. All analog outputs are free from digital noise with more than 100 dB suppression. The board is linked to a PC via isolated bidirectional single wire interface. The main advantage of the AWG board
The research leading to these results has received funding from the European Community’s Seventh Framework Programme (FP7/2007-2013) under Grant No. 270843 (iQIT). The authors acknowledge for the partial support from the Russian Ministry of Education and Science through the project 2014/138 number 1176. B.I. acknowledges for the financial support from the Russian Foundation for Basic Research with a Grant No. 14-02-31601. The authors thank A. V. Krivetskiy, P. Macha, and G. Oelsner for valuable discussions. 1 Ya.
S. Greenberg, Rev. Mod. Phys. 70, 175 (1998). Makhlin, G. Schön, and A. Shnirman, Rev. Mod. Phys. 73, 357 (2001). 3 M. H. Devoret and J. M. Martinis, Quantum Inf. Process. 3, 163 (2004). 4 E. Il’ichev, N. Oukhanski, Th. Wagner, H.-G. Meyer, A. Yu. Smirnov, M. Grajcar, A. Izmalkov, D. Born, W. Krech, and A. Zagoskin, Low Temp. Phys. 30, 620 (2004); Fiz. Nizk. Temp. 30, 823 (2004). 5 J. Clarke and F. K. Wilhelm, Nature 453, 1031 (2008). 6 Q. You and F. Nori, Nature (London) 474, 589 (2011). 7 N. G. Dickson, M. W. Johnson, M. H. Amin, R. Harris, F. Altomare, A. J. Berkley, P. Bunyk, J. Cai, E. M. Chapple, P. Chavez, F. Cioata, T. Cirip, P. deBuen, M. Drew-Brook, C. Enderud, S. Gildert, F. Hamze, J. P. Hilton, E. Hoskinson, K. Karimi, E. Ladizinsky, N. Ladizinsky, T. Lanting, T. Mahon, R. Neufeld, T. Oh, I. Perminov, C. Petroff, A. Przybysz, C. Rich, P. Spear, A. Tcaciuc, M. C. Thom, E. Tolkacheva, S. Uchaikin, J. Wang, A. B. Wilson, Z. Merali, and G. Rose, Nat. Commun. 4, 1903 (2013). 8 M. Jerger, S. Poletto, P. Macha, U. Hübner, A. Lukashenko, E. Il’ichev, and A. V. Ustinov, Europhys. Lett. 96, 40012 (2011). 9 M. Jerger, S. Poletto, P. Macha, U. Hübner, E. Il’ichev, and A. V. Ustinov, Appl. Phys. Lett. 101, 042604 (2012). 10 Yu. Chen, D. Sank, P. O’Malley, T. White, R. Barends, B. Chiaro, J. Kelly, E. Lucero, M. Mariantoni, A. Megrant, C. Neill, A. Vainsencher, J. Wenner, Y. Yin, A. N. Cleland, and J. M. Martinis, Appl. Phys. Lett. 101, 182601 (2012). 11 K. Bladh, D. Gunnarsson, E. Hürfeld, S. Devi, C. Kristoffersson, B. Smalander, S. Pehrson, T. Claeson, and P. Delsing, Rev. Sci. Instrum. 74, 1323 (2003). 12 A. Lukashenko and A. V. Ustinov, Rev. Sci. Instrum. 79, 014701 (2008). 13 B. I. Ivanov, D. N. Klimenko, A. N. Sultanov, E. Il’ichev, and H.-G. Meyer, Rev. Sci. Instrum. 84, 054707 (2013). 14 E. Il’ichev, Th. Wagner, L. Fritzsch, J. Kunert, V. Schultze, T. May, H. E. Hoenig, H.-G. Meyer, M. Grajcar, D. Born, W. Krech, M. Fistul, and A. Zagoskin, Appl. Phys. Lett. 80, 4184 (2002). 15 V. I. Shnyrkov, Th. Wagner, D. Born, S. N. Shevchenko, W. Krech, A. N. Omelyanchouk, E. Il’ichev, and H.-G. Meyer, Phys. Rev. B 73, 024506 (2006). 16 See http://www.bloodshed.net/devcpp.html for information about C/C++ source files. 2 Yu.
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REVIEW OF SCIENTIFIC INSTRUMENTS 85, 054702 (2014)
A compact, multichannel, and low noise arbitrary waveform generator S. Govorkov,1 B. I. Ivanov,2,3 E. Il’ichev,2 and H.-G. Meyer2 1
Sema Systems, 302-5553 16th ave., Delta, British Columbia V4M 2H7, Canada Leibniz-Institute of Photonic Technology, PO Box 100239, D-07702 Jena, Germany 3 Novosibirsk State Technical University, K.Marx-Ave. 20, Novosibirsk 630092, Russia 2
(Received 10 October 2013; accepted 14 April 2014; published online 2 May 2014) A new type of high functionality, fast, compact, and easy programmable arbitrary waveform generator for low noise physical measurements is presented. The generator provides 7 fast differential waveform channels with a maximum bandwidth up to 200 MHz frequency. There are 6 fast pulse generators on the generator board with 78 ps time resolution in both duration and delay, 3 of them with amplitude control. The arbitrary waveform generator is additionally equipped with two auxiliary slow 16 bit analog-to-digital converters and four 16 bit digital-to-analog converters for low frequency applications. Electromagnetic shields are introduced to the power supply, digital, and analog compartments and with a proper filter design perform more than 110 dB digital noise isolation to the output signals. All the output channels of the board have 50 SubMiniature version A termination. The generator board is suitable for use as a part of a high sensitive physical equipment, e.g., fast read out and manipulation of nuclear magnetic resonance or superconducting quantum systems and any other application, which requires electromagnetic interference free fast pulse and arbitrary waveform generation. © 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4873198] I. HIGH SPEED PULSE AND WAVEFORM READOUT FOR PHYSICAL EXPERIMENTS
At present, the semiconductor technology allows the fabrication of high capacity Field Programmable Gate Array (FPGA) chips. This gives a great opportunity for experimentalists to create high functionality devices based on those FPGA and perform measurements according to the specific experimental requirements. One example of such type of low noise measurements is the nuclear magnetic resonance spectrometry and tomography,1 where it is required to provide a fast dynamical excitation by means of short time pulses. Another large area of perspective research is related to quantum superconducting circuits with Josephson junctions,2–6 since these systems have been found to be promising contenders for the quantum computer implementation.7 Since the number of quantum bits (qubits) on one chip was recently increased,8–10 it is necessary to control and manipulate them simultaneously with a high signal stability and low noise. Therefore, multichannel low jitter waveform generators with low output noise power are required. One possible solution in order to design waveform signal generators is to use FPGA. There are plenty of well-known commercial available devices providing scientists with waveform signals. But most of them are quite expensive, large, or do not offer enough signal flexibility. In this paper we present a compact, easy to reprogram, and digital noise free arbitrary waveform generator (AWG). It has 50 SubMiniature version A (SMA) output termination and can easily be installed in a 19 in. subrack.
II. AWG HARDWARE PERFORMANCE
The block diagram of the arbitrary waveform generator is shown in Fig. 1. This diagram shows the basic board structure, 0034-6748/2014/85(5)/054702/5/$30.00
which consists of three separate shielded compartments: power supply, digital compartment with an FPGA, and analog compartment with differential low-pass filters and low noise differential amplifiers (see DLPF and LNDA in Fig. 1). The FPGA performs the main board’s housekeeping function. Seven DAC blocks are responsible for providing the data to the 14-bit DACs, while six pulse blocks are generating pulse sequences with 78 ps resolution. The 48-bit timer generates sync pulse sequences, which trigger DAC and pulse circuits. All the programming of the FPGA is performed via link module. The AWG is assembled on a 8 layer printed circuit board (PCB) divided into three compartments (Fig. 2). The metallic shields of the compartments are soldered directly to the top and bottom ground planes of the PCB. For easy board debugging and signal characterization, the shields are equipped with removable leads. A digital compartment with a FPGA and fast DACs (digital-to-analog converters) is situated in the middle of the board, see Fig. 2(b). The Virtex-6 (xc6vlx75t2ff784) FPGA family is used for board housekeeping. There are three more Virtex-6 FPGA chips in the same pin compatible package. This allows one to increase FPGA resources up to 4 times by substituting the chip if required. The crystal oscillator is situated in the digital compartment and it generates the 500 MHz main clock of the board. It allows one to achieve a 2 ns coarse time resolution. The flash programmable readonly memory chip is used for downloading configuration files to the FPGA. A slow 16-bit digital/analog circuitry is presented on the board and is aimed to be used for low frequency measurements. Fast analog waveform outputs are generated with the 14bit MAX5890 DACs. This DAC chip has a low noise spectral density of −162 dBFS/Hz at fout 36 MHz, low voltage differential signaling digital inputs and less than 300 mW of power dissipation at the maximum frequency. It is capable of
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© 2014 AIP Publishing LLC
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Rev. Sci. Instrum. 85, 054702 (2014)
FIG. 1. A block diagram of the arbitrary waveform generator.
working up to 600 MHz clocking frequency. Four different modes of operation were developed in the FPGA firmware: Random Access Memory (RAM), Piece Wise Linear (PWL), Central Processor Unit (CPU), and zero waveform output mode. An extension to the 16-bit fast DACs from the same family does not improve the performance because they can offer only a 14-bit linearity performance. The circuits in the analog compartment (Fig. 2(c)) filter the incoming waveforms and amplify them with up to a maximum of 4 V peak-to-peak output voltage, depending on the channel number. The self voltage noise √ spectral density of the amplifiers corresponds to 1.1 nV / H z. All the analog outputs are filtered with 7th order Gaussian low-pass filters with either 100 MHz or 200 MHz cutoff frequencies. They are placed at the input of the analog compartment. The proper filter and PCB design provides more than 110 dB digital
noise suppression in the output signal lines. All the waveform filtering lines were primarily characterized with a network analyzer and have shown more than 110 dB stop band suppression up to 2 GHz frequency. Powder filters11, 12 or bandpass filters with high stop band suppression13 might be used if required. An off-the-shelf 5 V power supply is used to power the board. It is connected to the AWG board via an SMA power connector. All the power supply components are located in the power supply compartment of the board (Fig. 2(a)). Switching voltage regulators are used to generate all necessary voltage rails. The total power consumption of the board is mainly defined by the Virtex-6 FPGA and requires around 1.5 A of current (depending on the channel amount operating at the same time). In order to suppress the influence of DC-DC converters switching noise to the DACs’ analog outputs, double pi ferrite filters are used. III. AWG OPERATING MODES AND SOFTWARE A. RAM-, PWL-, CPU- modes
FIG. 2. A representation of the AWG board. (a) Power supply compartment, (b) digital part with DACs, and (c) analog compartment.
Each channel is equipped with a 32 K × 14 bit RAM block. By default, the RAM content is programmed with a single sine wave period. With 2 ns data point rate and continuous waveform generation, the default RAM content generates around 15 kHz sine wave. For higher frequencies, the RAM’s address counter may be incremented not by one but rather by a constant parameter Delta. For slower frequencies, a slower (once in N-clock times) reading from the RAM may be used. The RAM’s address counter may be rolled over (reset) when it reaches a preset limit. Using the ability to roll over the address counter and at the same time reprogram the RAM content, allows one to adjust the generated frequency by approximately 3 × 10−5 steps. This technique gives the possibility to generate a sine wave with frequencies from micro Hz up to 100 MHz. Therefore, the readout of superconducting devices in the classical14 as well as in the quantum15 regime can be performed using megahertz-range tank circuits. With the current realized PC USB 1.1 interface about 140 ms are required to reprogram the whole RAM content for one channel. A one shot mode is supported as well, when the RAM content
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may be read once after a delayed sync pulse is detected by the RAM address controller. A shorter than 32 K waveform may be read if required. A PWL engine is provided for each waveform channel. This engine allows one to “draw” straight lines via a set of predefined points. Two 32-bit numbers represent each PWL data point: an Increment and a Counter, which specifies how many clock cycles the Increment must be used. On each clock cycle, the PWL engine generates a new 32-bit value and a top 14-bit portion of it is sent to the 14-bit DAC. When the Increment equals zero, a constant value is generated for Counter clock cycles. Otherwise a rising (for a positive Increment) or falling (for a negative Increment) ramp is generated. Each point may last from 2 ns (one clock cycle) to more then 8 s. For example a single 8 s long ramp may be generated from one data point with the Increment = 1 and the Counter = 232 − 1 (maximum possible Counter’s number). When the Counter = 0, the Increment value is treated as an immediate value, which is sent to the DAC. This mechanism allows one to start the PWL waveform with a well-defined value or set a new value in the middle of the waveform if required. Setting this new value still requires a one-clock cycle (2 ns). In total 1024 points may be used for each channel. The PWL engine stops when it reaches the End-of-Packet (EOP) marker, which is stored together with the last PWL data point. The EOP marker is automatically inserted at the end of a new PWL packet sent by the host PC. One extra mode of operation (namely, CPU) is provided as well. Each channel has a tiny micro controller, which has a 250 MHz clock frequency and requires two clock cycles per instruction. This mode is intended to be used for a simple waveform generation like a saw tooth or any other waveform, that can be easily described by a simple software algorithm. An assembler language compiler together with a newly generated code loader are provided.
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(b)
FIG. 3. The experimental characteristic of the waveform signals in RAMand PWL-waveform modes for the third channel of the AWG board with 100 MHz bandwidth. We show the examples of sinus and Gaussian (red curve) waveforms with 1.4 V output peak-peak voltage amplitude (a) and an example of a 10 point PWL waveform (b).
10 PWL points is presented on the oscillogram (see Fig. 3(b)). In PWL mode 1 point needs roughly 10 μs for reprogramming, so in the case of 10 points, the reprogramming time for all the 7 waveform channels can be less then 1 ms. All three waveforms were generated by the same channel with cutoff (a)
B. Software
A special software was designed in order to handle and debug the board. A logic analyzer program with graphical interface was written using Dev-C++ from Bloodshed.16 This interface allows one to set the main parameters for the waveform signals, e.g., pulse amplitudes and delays (both the fine and the coarse), channel modes, etc. The AWG board can be handled by any programming language, which supports Dynamic Link Library (DLL) calls.
(b)
IV. SIGNAL CHARACTERISTICS A. RAM-mode, PWL-mode, and CPU-mode arbitrary waveform signals
The measured oscillograms of the operating RAM-mode waveforms are shown in Fig. 3. We generated a 20 MHz sinusoidal signal with a 1.4 V peak-to-peak amplitude and a zero offset. Another example of the RAM-mode waveform is the Gaussian signal (red curve in Fig. 3(a)). We also demonstrate a simple possibility to program a waveform by means of a piecewise linear function. A PWL-mode signal with only
FIG. 4. The measured pulse sequences of 2 pulse channels (SYNC0, PLS1) of the AWG board. (a) Two pulses with 2 ns and 4 ns lengths for the coarse mode. The 1 ns delay time between two pulses is demonstrated. (b) The 78 ps fine mode delay as the lowest time delay resolution between pulses is presented.
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(a)
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Rev. Sci. Instrum. 85, 054702 (2014)
(b)
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FIG. 5. The noise output spectra with zero waveform output at channel 0 of the AWG board. (a) The low frequency noise spectra demonstrates lack of parasitic power supply switching noise. (b) The 500 MHz clock noise suppression corresponds to 110 dB. (c) The wideband power noise spectra over the 100 MHz low-pass filter measured up to 1.8 GHz. (d) The pulse jitter with a long measurement term corresponds to 35 ps. The x-abscissa corresponds to time with 50 ps step and the y-ordinate corresponds to voltage with 50 mV step.
frequency fc = 100 MHz. An oscilloscope with 20 GSa/s sampling rate with 2000 display points was used for the signal characterization. B. Pulse generator
The pulse generator was fully characterized and the most outstanding parameters of the pulse channels are demonstrated by the oscillogram in Fig. 4. There are two pulse sequences with different amplitudes from channels PLS1 and SYNC0 of the AWG board. One pulse has 2 ns length and the other has 4 ns length. These two pulse sequences have 1 ns of delay between them and this coarse mode is presented in Fig. 4(a). We also show that the lowest time delay of the pulses can correspond to 78 ps for the fine mode and this is shown on the oscillogram Fig. 4(b). C. Noise performance, signal resolution, and jitter characterization
The main noise contributors to the output waveform signals of the board are the 500 MHz clock signal from the
local oscillator and the oscillating noises from switching power supply circuitry. In order to characterize the noise performance of the generator we measured the output spectra for all the channels by means of a spectrum analyzer. The zero waveform mode was characterized up to a frequency of 1.8 GHz. The experimental characteristic in Fig. 5(c) shows the suppression of the noise power up to 100 dB for the measured frequency range. A proper Gaussian low-pass filter design performs more then 110 dB suppression of the 500 MHz clock noise, see Fig. 5(b). The low frequency noise power for channel 0 is shown in Fig. 5(a). This curve demonstrates that the switching frequency noise signal from power the DC-DC converters were suppressed more than 115 dB. Experiments with superconducting persistent current qubits require high signal stability. Their characterization of coherence times is usually performed by means of short pulse excitation. Here the jitter plays an important role and defines the stability of the measurement. We characterized the long term jitter of the pulse generator. We applied two different pulses with 5 ns and 10 ns lengths to two input channels of the fast 50 terminated oscilloscope. The delay between the pulses was set to 8 ms. The first pulse was used for triggering
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is that it has built-in capability for an extension and multiple boards can be daisy chained, having the same clock, control, and trigger lines. The board may be assembled with bigger FPGA chips if required. There are three more Virtex-6 FPGA chips in the same pin compatible package. This allows one to increase FPGA resources up to 4 times if required. The completed AWG device with closed leads is presented in Fig. 6.
ACKNOWLEDGMENTS
FIG. 6. The photo of the implemented arbitrary waveform generator board with removable metallic leads and SMA output termination.
the oscilloscope and the jitter was observed on the rising edge of the second pulse. The jitter color diagram is presented in Fig. 5(d). The peak-to-peak value of the jitter corresponds to approximately 35 ps and is less than a half of the finest 78 ps step. V. CONCLUSION
In a frame of this work we designed and implemented a new high speed multifunction AWG board for physical experiments. The board has 7 differential fast output waveform channels and 4 slow output waveform channels. The fast channels have 14-bit and 2 ns resolution. According to the bandwidth and noise requirements, 7 waveform channels have different frequency bandwidths, namely, 5 channels have 100 MHz cutoff frequency with more than 100 dB noise isolation and 2 channels have 200 MHz cutoff frequency with more than 90 dB noise isolation. The waveform channels have amplitude control with a maximum amplitude up to 4 V. The pulse generator is realized as 3 amplitude control channels and 3 channels with a constant amplitude. The maximum pulse length and delay is 4 s and the minimum pulse length and delay is 1 ns. The AWG board is built around Xilinx Virtex-6 FPGA with 500 MHz main clock. The operation is controlled by free programming languages: Dev-C++ from Bloodshed or Python and requires simple single off-the-shelf +5 V with less then 2 A current power supply. All analog outputs are free from digital noise with more than 100 dB suppression. The board is linked to a PC via isolated bidirectional single wire interface. The main advantage of the AWG board
The research leading to these results has received funding from the European Community’s Seventh Framework Programme (FP7/2007-2013) under Grant No. 270843 (iQIT). The authors acknowledge for the partial support from the Russian Ministry of Education and Science through the project 2014/138 number 1176. B.I. acknowledges for the financial support from the Russian Foundation for Basic Research with a Grant No. 14-02-31601. The authors thank A. V. Krivetskiy, P. Macha, and G. Oelsner for valuable discussions. 1 Ya.
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