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A CMOS Micromachined Capacitive Tactile Sensor With Integrated Readout Circuits and Compensation of Process Variations Tsung-Heng Tsai, Member, IEEE, Hao-Cheng Tsai, Student Member, IEEE, and Tien-Keng Wu

Abstract—This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout CMOS circuits are integrated on a single chip by a TSMC 0.35 MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 . The overall power . dissipation is 132.8 Index Terms—CMOS integrated circuits, micromachining, tactile sensors.

I. INTRODUCTION

T

HE tactile sensors can measure the pressure or stress for many applications, for example, security identification systems, tire pressure monitoring, robotics or biomedical signal detections. Owing to the minimization of the sensors in the size and the power consumption, more and more sensing devices are implemented in the biomedical systems. Several types of micro-devices have been developed for various applications [1]–[8]. The minimally invasive surgery (MIS) has been rapidly developing nowadays for its small cut, less pain and less recovery time. A magnetic hydrogel-based microgripper for intravascular applications was developed in [3]. A system of mobile manipulation robot estimating both object class as well as the state of the grasped object from its tactile appearance is developed in [4]. When the surgery devices grasp human tissues or organs, the applied stress has to be well controlled.

Manuscript received March 07, 2014; revised July 07, 2014 and September 05, 2014; accepted September 09, 2014. Date of publication October 09, 2014; date of current version November 06, 2014. This work was supported by the Ministry of Science and Technology, Taiwan, under Grants MOST 103-2221-E194-057. This paper was recommended by Associate Editor R. F. Yazicioglu. T.-H. Tsai and H.-C. Tsai are with National Chung Cheng University, Chiayi, Taiwan 62102, Taiwan (e-mail: [email protected]). T.-K. Wu was with National Chung Cheng University, Chiayi, Taiwan 62102, Taiwan. He is now with Richtek, Hsinchu 30288, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TBCAS.2014.2358563

The stress generated by grasping with a thin forceps might damage the tissues. To avoid excessive stress, real time monitoring of the stress is essential [9], [10]. Triaxial micro-electro mechanical systems (MEMS) tactile sensors were attached to the tip of a forceps in [9] for measuring the pressure and shear stresses. The tactile sensors can detect the grasping force and two directional shear stresses at the same time. However, the readout circuits are not integrated on the tactile sensors. The long connection lines may introduce heavy loading and noise, which may limit the detectable pressure of the tactile sensors. In this work, an array of CMOS MEMS tactile sensors and the readout circuits are designed and integrated on a single chip. CMOS MEMS technology has become more and more popular for its advantages of compact size, low-power consumption and especially the integration with readout circuits and systems. Furthermore, parasitics can be reduced and signal to noise ratio (SNR) will be enhanced by integrating the sensors and the readout circuits on a single chip. Typically, tactile sensors by CMOS MEMS technology can be categorized into the piezoresistive and capacitive types. Piezoresistive tactile sensor detects the changes of the resistance which changes along with the deformation on the piezoresistive material caused by the pressure on it [11], [12]. Piezoresistive tactile sensor has better linearity, but it requires complicated fabrication, and is more sensitive to environment variations, such as temperature. Capacitive tactile sensor [13]–[15] is composed of two parallel electrodes. When the pressure is applied on the movable upper electrode, displacement of the upper electrode causes the change of the capacitance. Previous expectations of tactile sensors in biomedical engineering have been reviewed and the reasons for their failure to meet these expectations are discussed in [16]. In standard CMOS technologies, capacitors require no special fabrication steps. Compact integration with the sensing circuits can be achieved and can provide compensation to environment variations through calibration schemes. Fig. 1 illustrates the block diagram of the stress sensing system for MIS applications. When a user-defined motion is performed, the integrated MEMS tactile sensor and readout circuit transforms the pressure into the electrical signals. The analog-to-digital converter (ADC) converts the electrical signal into digital data, and the signal processing block generates a control signal to control the grasping force. When CMOS readout circuits are integrated in the same chip, variations on the sensing capacitance are introduced

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Fig. 3. The 3-D views from different angles of the proposed structure. The protrusion is built on the surface of the upper electrode of the capacitive tactile sensor to increase the sensitivity.

Fig. 1. CMOS micromachined capacitive tactile sensor for sensing the grabbing force in minimally invasive surgeries.

Fig. 2. The block diagram of the capacitive tactile sensor system.

by the fabrication process. Process variations inevitably vary the value of the sensing capacitor and require calibration to make the readout circuits accurate. In order to suppress the common-mode noise, a fully differential correlated double sampling (CDS) capacitor-to-voltage converter (CVC) circuit is employed in this work. The fabrication process of the proposed T-shaped structure is discussed in Section II. Mechanical measurement results of the sensors are also presented in Section II. Section III describes the implementation of the readout circuits and the analysis of the circuit noises. Experimental results and discussion are given in Section IV. Section V provides the conclusion of this work. II. SENSOR IMPLEMENTATION Fig. 2 illustrates the block diagram of the proposed capacitive tactile sensing system. The sensing capacitor is composed of 4 sensing capacitors in parallel. The change in capacitance is generally in the femto-farad level due to the compact size of the capacitive-based sensors. The resolution of the sensors is inevitably influenced by the process variations and noises introduced by the integrated readout circuits. A set of tunable capacitor array are also utilized as the reference capacitor to compensate the variations introduced by fabrication process. The switching capacitor array in the sensing system is calibrated at the beginning. Capacitance to voltage converter will convert the difference between the sensing capacitor and the reference capacitor into the corresponding output voltages. It can create a signal which controls the counter of the switching capacitor array through periodically sensing the output of the first stage CVC by a voltage comparator. The reference capacitor will approach to the sensing capacitor after the calibration is completed. The accuracy of the calibration is dependent on

the unit size of the reference capacitor array. The initial value of is designed to be . The 20 fF poly-insulator-poly (PIP) capacitors and 2.5 fF metal-oxide-metal (MOM) capacitors comprise the reference capacitor array in this work. Furthermore, in order to reduce the common mode noise, a fully differential CDS-CVC circuit is employed in the readout block of the capacitive tactile sensing system. To enhance the sensitivity of the capacitive-based sensors, the protrusions on the surface of the upper electrode can be utilized to increase the capacitance change when a normal force is applied, and the T-shaped protrusion, shown in Fig. 3, was reported to have the best performance in [13]. But producing the T-shaped protrusion structure requires several deposition steps and additional etching steps in the post-process in [13]. These post-processing steps are complex and increase the risk to damage the sensors. In this work, a T-shaped protrusion structure is proposed, which can be fabricated in a standard CMOS MEMS process technology with single etching step and without any deposition step. For the comparison of sensitivity, another set of typical structure was fabricated with the same post-process. Measurement results show that the sensitivity and reliability of the proposed structure are improved. On the other hand, because the change of capacitance is in the range of tens femto Farads, noise sources should be taken into consideration, such as thermal noise, flicker noise and the switching noises produced by clock feedthrough and channel charge injections. A. The Sensitivity and Reliability of the Proposed Structure In the utilized CMOS process technology, there are 2 poly layers and 4 metal layers. Metal-3 and Metal-4 layers, shown in Fig. 4(a), are the suitable choices for the upper electrode of the sensing capacitor. The material used for the electrodes affects the sensitivity and reliability of the sensors. Fig. 4(b) shows cross section of the fabrication structure in this work. It can be observed that there is a 1 of oxide layer on the top of Metal-3, whereas a 1.45 of passivation layer on the top of Metal-4. To verify that better sensitivity can be achieved by using Metal-3 as the top electrode of the sensing capacitor, simulations were carried out for these two structures, shown in Fig. 4(c) and (d). The Metal-3 and Metal-1 are used as the top and bottom electrodes of the sensing capacitor in the T-shaped sensor. These two electrodes were covered by the oxide layer separately to prevent these two electrodes from being etched by the etchant during the wet etching process. The thickness of the membrane is 2.64 . The composition of the membrane, from top to bottom, is the oxide (1 ), the Metal-3 (0.64 ) and

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Fig. 4. Fabrication process after completion of the standard CMOS process. (a), (b) Before post processing of the typical and the T-shaped structure. (c), (d) After sacrificial metal etching and removal of the passivation on the top of the bonding pads of the typical and the T-shaped structure, respectively.

the oxide (1 ) thin films. The sensing gap is 0.64 , which is the thickness of the sacrificial Metal-2 layer in the CMOS MEMS technology. On the other hand, for the typical structure, the thickness of the membrane is 3.375 . The composition of the membrane, from top to bottom, is the passivation (1.45 ), the Metal-4 (0.925 ) and the oxide (1 ) thin film. The sensing gap is 0.64 , which is the thickness of the sacrificial Metal-3 layer. Because of the difference between the consisting layers in CMOS process between these two structures, the sensing membrane of the T-shaped structure is thinner than that in the typical structure. Simulations were carried out for different structures under 1 MPa pressure to verify the sensitivity: (a) the typical structure with Metal-4 layer as the top electrode, (b) the typical structure with Metal-3 layer as the top electrode, and (c) the proposed T-shaped structure with Metal-3 layer as top electrode. The radius of the sensing area for all structures is 24 . Simulation results by CoventorWare show that the maximum displacement for the three architectures is 0.045 , 0.15 , and 0.16 , respectively. The sensitivity is better when using Metal-3 layer as the top electrode, and the proposed T-shaped protrusion further improves the sensitive.

Fig. 5. Von Mises stress simulations for different structures under 1 MPa pressure. (a) Typical structure with Metal-4 layer as the top electrode. (b) Typical structure with Metal-3 layer as the top electrode. (c) The proposed T-shaped structure with Metal-3 layer as top electrode.

Considering the reliability of the sensing structures, simulations on von Mises stress are conducted. Fig. 5 shows the simulation results when 1 MPa pressure is applied on the top electrodes of the three structures. The maximum von Mises stress of the Metal-4 structure is 280 MPa, and it is 300 MPa of the Metal-3 structure. With the same pressure applied, the higher von Mises stress on the structure may cause the higher possibility for the structures to be broken and decrease the reliability. The reliability of the Metal-3 structure is lower because the Metal-3 layer spreads more force to the beads on the edge of the sensors. Adding a T-shaped protrusion makes major portion of the stress distributed in the circle around the center evenly, and relieves the loading on the beads. Fig. 5(c) shows the simulation result of the proposed T-shaped structure. The maximum von Mises stress is 220 MPa, which is much lower than that of the typical flat structures. B. Manufacturing Process This capacitive tactile sensor is fabricated in a TSMC 0.35 two-polysilicon four-metal (2P4M) CMOS technology. Fig. 4 illustrates the flow of the fabrication process, showing that the steps of the post-process for both typical and the proposed T-shaped structures are the same. After the

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fabrication is completed by the foundry, most of the die surface area except the etchant holes is covered by a passivation layer. The proposed T-shaped structure uses the Metal-4 layer as the sacrificial layer. The etchant holes are utilized to etch the Metal-2 layer and achieve structural release. The T-shaped protrusion is consisted of passivation layer. By etching the metal only, the etchant can go through the etching channel (Metal-4, Via-34, Metal-3, Via-23), and etch the sacrificial layer, the Metal-2 layer. After the metal etching process, the microstructure can be released, and the T-shaped protrusion is formed. By wet etching, the microstructure can be released, and the T-shaped protrusion remains on the top of the sensing membrane. The location, size and shape of the T-shaped protrusion also can be designed precisely with careful layout. The etchant is a mixed solvent of . The wet etching time is 50 minutes and the etchant is heated to 100 . After the microstructure is released, wire bonding is utilized to connect the readout circuits for further measurements of the integrated readout circuits. In order to complete the package bonding on the die, the passivation on the bonding pads needs to be removed with the reactive ion etch (RIE) method. The value of sensing capacitance can be represented by (1) where is the permittivity of air, is the permittivity of silicon oxide. is the electrode area, is the total intermetal dielectric thickness, is the initial air gap and is the displacement of the upper electrode. C. Post Processing The T-shaped protrusions in this work are made of the top layer of the fabrication, which is the passivation layer. Typically, the passivation layer is used to protect the circuits only. We should be cautious to any post process step to the surface of the chip. The most critical one is the photo-resist (PR) layer, which is added by the foundry in the MEMS fabrications. Post fabrication is required to remove the passivation on the PADs before wire bonding. We designed test chips containing only the sensing structures to better understand the influence of the post processing. To prevent the MEMS structures from damages, after the fabrication is accomplished, the foundries usually apply a PhotoResist (PR) layer on the surface of wafers before dicing the wafers into chips. We have to remove the PR layer before the wet etching. The recipe of the PR stripping in this work is: 30 minutes in the acetone at 25 , 30 minutes in the alcohol at 25 , 15 minutes in the deionized water, and 5 minutes in the oven at 90 . After we use the recipe to remove the PR layer, we can observe the surface of the chip, shown in Fig. 6(a). The residue of PR layer is unpreventable, and the PR residue can usually be found on the top of the etching channels. As a result, the wet etching process may require more time to release the structure of the sensing capacitors. Observing the T-shaped structure in this work, shown in Fig. 6(b), when the chips are exposed in the etchant for much longer time during the wet etching process, the bottom of the

Fig. 6. Test chips with PR layer. (a) Before wet etching process. (b) After wet etching process.

T-shaped structure may be broken. It is observed several times in the experiments that proper wet etching time is critical to release the structure completely without making the T-shaped protrusions damaged or broken. The missing parts of T-shaped protrusions in Fig. 6(b) demonstrate that some of the T-shaped protrusions are broken. If the PR layer can be avoided in the fabrication processes, better circuit performance can be achieved. The pads of the MEMS chips are covered by passivation layer when it is fabricated by the foundries. In normal post process, the passivation layer can be removed directly. However, the T-shaped protrusions are formed of passivation layer in this work. Removing passivation layer will also damage the T-shaped protrusions at the same time. We remove the passivation layer by the RIE method. To prevent damage on the T-shaped protrusions during RIE process, we covered the chip surface by a dummy piece of the silicon chip before the RIE process. The silicon chip precisely covered the area of T-shaped protrusions and circuits, only the passivation layer on the pads is exposed to the RIE process. The machine which performed the RIE process is Cello Nasca-20, and the gas used in this work is . D. Mechanical Measurement Results Both of the typical structure and the T-shaped structure are radius and fixed by 8 designed in the disc shape with 24 supporting beams. The size of the support beams are . The T-shaped structure has the T-shaped protrusion on the membrane composed of two disc-shaped components of 20 radius at the top and 10 radius at the bottom. Fig. 7 is the picture of the fabricated sensors taken by scanning electron microscope (SEM). The hollow in the middle of the T-shaped protrusion is caused by the passivation process. Due to the Metal-4 layer in this structure, the passivation surface is higher at the top of the disc-shaped component. We measured the stiffness of these two structures by a nanoindenter. The force-displacement curves of both structures are presented in Fig. 8. The measured spring constants of the typical structure and the T-shaped structure are 8.46 kNewton/m and 7.87 kNewton/m, respectively. It is shown that the T-shaped structure has better sensitivity. Also, the proper post processing parameters, including the etchant recipe and the wet etching time without damaging the T-shaped protrusions, were obtained. After we verified the characteristics of the sensing structures, we further integrated the

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technique is usually used to reduce dc offset and low-frequency noises. A. Circuit Design

Fig. 7. The scanning electron micrographs of the fabricated sensors. (a) The flat surface structure. (b) T-shaped structure. The radius of both structures is . 24

Fig. 8. The measured force versus displacement curves of the typical structure and the T-shaped structure. The measured spring constants of the typical structure and the T-shaped structure are 8.46 kNewton/m and 7.87 kNewton/m, respectively.

proposed T-shaped sensor with the readout circuits. In order to relieve the sensitive specification of the sensing circuit, the radius of the sensors was increased to 54 um. Please note that increasing the radius can increase the electrode area and enhance the change of capacitance by (1). As a result, the T-shaped sensor of 320 fF, composed of four 80 fF capacitors in parallel, is implemented to integrate with the readout circuits. The sensors are designed and placed in a small size and can be applied to high-density tactile sensing systems. III. SENSING CIRCUITRY As shown in Fig. 9(a), a fully differential CDS-CVC [17] is used as the readout circuits in the capacitive tactile sensing system. Fully differential circuits are employed to suppress the common-mode noise. Through fabrication processes, variations on the capacitance may happen. A redundant capacitor can be used as a reference to improve the accuracy [18]. In this work, a tunable switching capacitor array is utilized instead of single reference capacitor. This will not only increase the process tolerance of the MEMS sensors, but also effectively suppress output offset voltage of the sensing circuits. On the other hand, it is important to reduce the noise in the circuits to improve the signal-to-noise ratio of the sensing system. To suppress the influence of the circuit noises, techniques such as auto-zeroing, chopper stabilization and correlated double sampling are widely used. The auto-zeroing

Please note that the switching capacitor array in the sensing system is calibrated at the beginning to compensate the process variations. The minimum step size of the tunable capacitance is 2.5 fF. The overall capacitance-to-voltage sensitivity is designed to be 18 mV/fF. Therefore, the reference capacitance calibration is finished when the differential output voltage of the two-stage amplifier is less than 45 mV. After calibration, equals when zero pressure is applied. will have a change of corresponding to the applied force, and the capacitance to voltage converter will convert into the corresponding output voltages. The sensing process requires three phases and the timing diagram of the readout circuits is shown in Fig. 9(b). The operating frequency of the sensing circuit is 1 kHz. In the first phase Ph1, the circuit resets and the lowfrequency noise from the input of the amplifier is stored on . In the second phase Ph2, switches to low, and the switching noise such as charge injection will be stored on . The switching output errors will be canceled because of the differential circuit architecture. In the third phase Ph3, the detected signal on the sensing capacitor is amplified and then the low-frequency noise and dc offsets are subtracted, which was stored on in previous phases. The output voltage of the sensing circuit can be represented as (2) In this work, the capacitance-to-voltage transductance of the readout amplifier is designed to be 18 mV/fF. According to (1), the sensing capacitance can be expressed as a function of displacement .

(3) where is the permittivity of air, is the permittivity of silicon oxide, which is usually approximated to , is the surface area of the sensing capacitor, is the initial air gap. In this design, the sensor dimension is . Given the process constants and the displacement is 205 nm, the sensing capacitance , about 78.65 fF, can be obtained. Hence, the theoretical displacement-to-capacitance transduction is 0.38 fF/nm. Assuming the relationship of the displacement of the upper electrode is proportional to the applied force , the transfer function from pressure to the output voltage can be shown as

(4) where is the force applied on the top electrode, is coefficient of the pressure to the displacement of the designed sensing capacitor. It is shown in (4) that the output voltage of the sensing

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Fig. 9. (a) A fully differential correlated double sampling capacitor-to-voltage converter is used as the readout circuit in the capacitive tactile sensing system. (b) The timing diagram of the readout circuits.

(a)

(b)

Fig. 11. The MOM capacitor. (a) Top view (b) Cross section.

Fig. 10. The circuit of the latch-type comparator.

circuit is a function of the sensing capacitance, and is proportional to the pressure. Because of the small change of the sensing capacitors, the small noises must be carefully analyzed. For achieving lower-power consumption, we use a latch-type comparator, shown in Fig. 10, to provide control signal to the switching capacitor array. It is a dynamic type comparator, and does not consume any static power. The comparator resets when the comparator enable signal is low. First, resets the source of and to , and reset the output to GND. When the enable signal is high, the comparator performs comparison. The cross coupled latch structure pulls the output ports to High or Low. Because this circuit resets in every sample period, the outputs will not suffer from memory effects. This helps to achieve better accuracy. To achieve the minimum error of the calibration capacitor array, the MOM type capacitor is used as the minimum unit capacitor. Illustrated in Fig. 11, the MOM capacitor is composed of crossed metal layers. MOM capacitors are much smaller than PIP type capacitors in size. In this work, PIP capacitors are used as large unit capacitors and MOM capacitor is the fractional unit capacitor. High tuning accuracy can be achieved without occupying large die area.

We use PMOS transistors as the input stage in all operational amplifiers because the larger parasitic capacitor makes lower noises at the gate. Besides, we can connect its source and body to reduce the body effect. The telescopic amplifier usually has lower noise and power consumption. The detailed circuit of the amplifier is shown in Fig. 12. On the other hand, a two-stage amplifier is employed in the second stage of the CDS-CVC for its larger output swing range and bigger closed-loop gain. This leads to the higher sensitivity of the overall capacitive tactile sensing system. B. Noise Analysis The thermal noise is produced by the random mobility of electrons, which leads to the voltage drop between conductors. In the MOSFET circuits, the most portion of the thermal noise is from the channel noise. When the long channel transistors are operating in the saturation region, the source of thermal noise can be considered as an additional current source which is connected between source and drain of the transistors. The power of thermal noise can be dedicated as (5) is Boltzmann constant, is the absolute temperature, where is a fabrication process constant, which is typically 2/3 for estimation, and is the transconductance of the transistors. Flicker noise is caused by the unconnected bonds which leaves a redundant energy level at the interface between the oxide layer and the silicon substrate. This will produce a current noise from the drain of the transistors. The flicker noise is

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Fig. 13. The circuit of the clock generator for control signal.

Fig. 12. The circuits of the operational amplifiers.

highly correlative to the fabrication process technologies, and can be expressed in (6). (6) and are fabrication constants, and are the where size of the transistors, and is the switching frequency. The larger size of the transistors makes flicker noise lower. Flicker noise usually dominates in low frequencies and the power of flicker noise inversely proportional to the switching frequency. According to the design specifications, we designed the transistor sizes in order to make the operation frequency to be larger than the corner frequency. In this work, the switching frequency is chosen to be 1 kHz. We designed relatively large values for the width of the transistors to make the corner frequency around 600 Hz. The unit frequency input noise power of the telescopic opamp can be shown as

(7) where is Boltzmann constant, and is absolute temperature. and are the noise coefficients of NMOS and PMOS. According to (7), scaling up the width and length of the MOSFETs can decrease the unit frequency input noise power. If there is any mismatch introduced in the fabrication process, dc offset voltages at the output port of the operational amplifier will deviate the dc bias from the designed values. A set of output common-mode feedback (CMFB) circuit is necessary to control the current source and generate the desired dc bias at the output. Discrete time CMFB circuit is utilized to stabilize the output common-mode voltage in this design. It is composed of 4 capacitors and 8 switches, and has the advantages of low power consumption and high output swing. Compared with the continuous-time structures, the switching capacitor structure has lower power consumption. The clock generator is shown in Fig. 13. CLK is an external reference clock of 4 kHz, and is the enable signal for the calibration scheme. The non-overlap clock and are created for preventing the channel charge injection.

Fig. 14. The chip micrograph. The sensing capacitor and the test key are on the top of the chip, where the sensing capacitor is marked.

IV. EXPERIMENTAL RESULTS AND DISCUSSION Fig. 14 is the chip micrograph. Two different colors can be observed clearly in the middle and in the surrounding of the chip after RIE is finished. The middle area of the chip is covered by a dummy silicon piece during RIE process to prevent this area from etching. The test board was set under a set of piezoelectric actuator system. The machines used in the piezoelectric actuator system were THORLABS DRV120, controlled by THORLABS BPC301. With instructions from a personal computer, the tip of the piezoelectric actuator can be controlled with minimum step size of 5 nm. Fig. 15 shows the micrograph of tip of the piezoelectric actuator with the proposed chip. Monitored by a microscope camera, the proposed chip is placed at the exact place to be pressed by the piezoelectric actuator. The measurement system is set on an anti-vibration table in order to prevent the accidental vibrations. The distance between the tip of the piezoelectric actuator and the surface of the chip is only several micrometers. The T-shaped protrusion structure may be broken due to the surface damage. Any damage to the surface of the chip should be avoided. The spring constant of the proposed sensor with integrated circuit is measured by the nano-indenter without connecting the power supply and the oscilloscope. The sensor dimension is . The measured spring constant is 2.19 . Then, the dc power supply, the pulse generator, and the oscilloscope were connected to the test board with the piezoelectric actuator. The dc bias of the sensing capacitor array and the reference capacitor array is 1.5 V. The operation frequency of the sensing circuit is 1 kHz. With several displacement applied by the piezoelectric actuator, the output voltages of the sensing circuits are obtained. Fig. 16 shows

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OF

TABLE I SENSOR SPECIFICATIONS

Fig. 15. The piezoelectric actuator tip and the chip under test.

the measured output voltages of the second stage amplifier when different displacement is applied by the piezoelectric actuator. The supply voltage of the sensing circuits is 3 V, the operation frequency is 1 kHz, and the measured displacement-to-voltage transductance is about 7.15 mV/nm. Hence, the sensitivity is 3.26 and the dynamic range of the overall system is within the displacement of 205 nm by 448.95 . On the other hand, the total average noise referred to the output of the amplifier in the frequency band of 1 Hz to 500 Hz can be estimated about 1.976 by (7). To achieve the signal-to-noise ratio (SNR) better than 60 dB, the minimum force is estimated to be 0.6 . Table I provides the summary of the measurement results and comparison with the prior arts is also given. The total power dissipation of the amplifiers is 132.8 . In this work, the CMOS readout circuits are integrated on the same chip. The sensitivity is enhanced.

Fig. 16. Measured output voltage verusu the displacement applied on the top electrode of the sensing capacitator. The measured voltage-to-displacement transductance is about 7.15 mV/nm.

V. CONCLUSION A capacitive tactile sensor with high sensitivity is presented. The T-shaped protrusion is formed by the passivation layer in the standard CMOS MEMS process. By single wet etching after the conventional CMOS process, the microstructure can be released. Measured results show that the proposed T-shaped capacitive tactile sensor achieves better sensitivity than the typical flat surface structures. A set of CDS-CVC circuit with switching capacitor array is employed to convert the pressure to voltages. The reference capacitor array is implemented with a calibration scheme to compensate process and environment variations so that the readout circuits can suppress common-mode noise and achieve high accuracy. The calibration capacitors occupy extra die area and the calibration scheme requires extra time before the sensor can be

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used. To further reduce the overall power dissipation, the capacitance-to-voltage transduction without employing operational amplifiers can be considered. For example, current-mode amplifiers can be utilized to readout the pressure with phase-lock loops to compensate process variations in the background. ACKNOWLEDGMENT The authors would like to acknowledge fabrication support provided by National Chip Implementation Center (CIC), the National Center for High-Performance Computing (NCHC) for support of the simulation tools. REFERENCES [1] S. Tottori, L. Zhang, F. Qiu, K. K. Krawczyk, A. Franco-Obregon, and B. J. Nelson, “Magnetic helical micromachines: Fabrication, controlled wwimming, cargo transport,” Adv. Mater., vol. 24, no. 6, pp. 811–816, Feb. 2012. [2] G. Kosa, P. Jakab, and G. Szekely, “MRI driven magnetic microswimmers,” Biomed. Microdev., vol. 14, no. 1, pp. 165–178, Feb. 2012. [3] J.-C. Kuo, S.-W. Tung, and Y.-J. Yang, “A hydrogel-based intravascular microgripper manipulated using magnetic fields,” in Proc. IEEE Int. Conf. Solid-State Sensors, Actuators and Microsystems, Jun. 2013. [4] S. Chitta, J. Sturm, M. Piccoli, and W. Burgard, “Tactile sensing for mobile manipulation,” IEEE Trans. Robot., vol. 27, no. 3, pp. 558–568, Jun. 2011. [5] E. Ghafar-Zadeh and M. Sawan, “A hybrid microfluidic/CMOS capacitive sensor dedicated to lab-on-chip applications,” IEEE Trans. Biomed. Circuits Syst., vol. 1, no. 4, pp. 270–277, Dec. 2007. [6] H. C. Powell, Jr., M. A. Hanson, and J. Lach, “On-body inertial sensing and signal processing for clinical assessment of tremor,” IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 2, pp. 108–116, Apr. 2009. [7] S.-S. Je, F. Rivas, R. E. Diaz, J. Kwon, J. Kim, B. Bakkaloglu, S. Kiaei, and J. Chae, “A compact and low-cost MEMS loudspeaker for digital hearing aids,” IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 5, pp. 348–358, Oct. 2009. [8] M. A. Miled and M. Sawan, “Dielectrophoresis-based integrated lab-on-chip for nano and micro-particles manipulation and capacitive detection,” IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 2, pp. 348–358, Apr. 2012. [9] K. Kuwana, A. Nakai, K. Masamune, and T. Dohi, “A grasping forceps with a triaxial MEMS tactile sensor for quantification of stresses on organs,” in Proc. Int. Conf. IEEE Engineering in Medicine and Biology Soc., Jul. 2013. [10] A. Talasaz and R. V. Patel, “Integration of force reflection with tactile sensing for minimally invasive robotics-assisted tumor localization,” IEEE Trans. Haptics, vol. 6, no. 2, pp. 217–228, Apr.–Jun. 2013. [11] M. Shikida, T. Shimizu, K. Sato, and K. Itoigawa, “Active tactile sensor for detecting contact force and hardness of an object,” Sens. Actuators A, Phys., vol. 103, pp. 213–218, Jan. 2003. [12] N. Galy, B. Charlot, and B. Courtois, “A full fingerprint verification system for a single-line sweep sensor,” IEEE Sensors J., vol. 7, no. 7, pp. 1054–1065, Jul. 2007. [13] N. Sato, S. Shigematsu, H. Morimura, M. Yano, K. Kudou, and T. Kamei et al., “Novel surface structure and its fabrication process for MEMS fingerprint sensor,” IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 1026–1032, May 2005. [14] T. Salo, K. U. Kirstein, T. Vancura, and H. Baltes, “CMOS-based tactile microsensor for medical instrumentation,” IEEE Sensors J., vol. 7, no. 2, pp. 258–265, Feb. 2007. [15] J.-C. Liu, Y.-S. Hsiung, and M. S.-C. Lu, “A CMOS micromachined capacitive sensor array for fingerprint detection,” IEEE Sensors J., vol. 12, no. 5, pp. 1004–1010, May 2012. [16] M. I. Tiwana, S. J. Redmond, and N. H. Lovell, “A review of tactile sensing technologies with applications in biomedical engineering,” Sens. Actuators A, Phys., vol. 179, pp. 17–31, Jun. 2012.

[17] P. Cong, N. Chaimanonart, W. H. Ko, and D. J. Young, “A wireless and batteryless 10-bit implantable blood pressure sensing microsystem with adaptive RF powering for real-time laboratory mice monitoring,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3631–3644, Dec. 2009. [18] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996. [19] Y.-C. Liu, C.-M. Sun, L.-Y. Lin, M.-H. Tsai, and W. Fang, “Development of a CMOS-based capacitive tactile sensor with adjustable sensing range and sensitivity using polymer fill-in,” J. Microelectromech. Syst., vol. 20, no. 1, pp. 119–127, Feb. 2011. [20] A. Wisitoraat, V. Patthanasetakul, T. Lomas, and A. Tuantranont, “Low cost thin film based piezoresistive MEMS tactile sensor,” Sens. Actuators A, Phys., vol. 139, no. 1/2, pp. 17–22, Sep. 2007. [21] C.-C. Wen and W. Fang, “Tuning the sensing range and sensitivity of three axes tactile sensors using the polymer composite membrane,” Sens. Actuators A, Phys., vol. 145/146, pp. 14–22, Jul./Aug. 2008. [22] Z. Chu, P. M. Sarro, and S. Middelhoek, “Silicon three-axial tactile sensor,” Sens. Actuators A, Phys., vol. 54, no. 1–3, pp. 505–510, Jun. 1996. Tsung-Heng Tsai (S’99–M’05) received the B.S. degree in control engineering from National Chiao Tung University, Hsinchu, Taiwan, the M.S. degree in electrical engineering from the University of Southern California, Los Angeles, CA, USA, and the Ph.D. degree in electrical and computer engineering from the University of California, Davis, CA, USA, in 1994, 1998, and 2005, respectively. Since 2005, he has been with the faculty of the Department of Electrical Engineering, National Chung Cheng University, Chiayi, Taiwan, where he is currently an Associate Professor. He served as the Executive Secretary of the Heterogeneous Integration Consortium of Ministry of Education, Taiwan, from 2009 to 2011. His main research interests are in CMOS mixed-signal integrated-circuit designs for energy harvesting systems and biomedical sensor systems. Dr. Tsai was the recipient of the Outstanding Teaching Award from National Chung Cheng University in 2011. He is Vice Chairman of the Tainan Chapter, IEEE Solid-State Circuit Society (2013–2014). He has served on the Technical Program Committees of the IEEE International Symposium on Bioelectronics and Bioinformatics and the IEEE Asian Solid-State Circuits Conference.

Hao-Cheng Tsai (S’13) received the B.S. degree in electronic engineering from National Chung Cheng University, Chiayi, Taiwan, in 2010. Currently, he is working toward the Ph.D. degree at National Chung Cheng University. His research interests include sigma-delta analog-to-digital converters, mixed-signal circuits, and micro-electro-mechanical systems. He also researches the field of audio recording engineering and HI-FI audio designs.

Tien-Keng Wu received the B.S. degree in electronic engineering from National Yunlin University of Science and Technology, Yunlin, Taiwan, and the M.S. degree from National Chung Cheng University, Chiayi, Taiwan, in 2010 and 2013, respectively. His research interests include micro-electro-mechanical systems and analog circuit designs.